BannerforSemiWiki 800x100 (2)
Semiconductor Expert Forum

Posted on

HiFi audio…in all the devices

HiFi audio…in all the devices
by Paul McLellan on 01-09-2012 at 6:00 am
Categories: Uncategorized

The big challenge with audio is that there are so many standards. Some of this is for historical reasons since audio for mobile (such as mp3), for the home (Dolby 5.1) and for cell-phone voice encoding/decoding have all had very different requirements, different standard setters and so on. But gradually everything is coming together. You will expect your smartphone to be able to play a movie with the same DTS sound your BluRay can provide.

The proliferation (and constant change) of standards has been an opportunity for Tensilica whose HiFi product line has become the standard for many semiconductor and system companies. By designing a custom audio processor and then supplying software for each standard, it is fairly easy to support any portfolio of standards and even be able to change the code as standards evolve, possibly even being able to update devices after they are in the customers’ hands.

The technical challenge for any audio solution is to get the lowest MACs/W/area/price which translates into designing a small processor that can implement the audio standards of interest at the lowest possible clock frequency. Power is a big driver since a lot of audio is either in portable devices (battery) or living room devices (no fans). The obvious solution of just running code on the ARM processor that is (probably) already on the chip is too power hungry. Building an optimal sillicon hardware implementation is too expensive both in design time and area (if different standards require different dedicated silicon).

HiFi 2 is a DSP with dual 24-bit MACs. HiFi EP is a version with improved memory and other optimizations. This week at CES Tensillica is announcing HiFi 3 which is a quad-mac solution which can be configured either as dual 32-bit MACs or as 4 24-bit MACs or some other configurations. The hardware is 3-slot VLIW processor, issuing 3 instructions on each clock cycle. The improvements are large. For example, a 32-tap FIR takes 2090 cycles on HiFi EP but only 997 on HiFi 3, less than half. DTS processing for movie sound needed 362MHz with HiFi 2 but only 233 MHz with HiFi 3.

HiFi 3 is source compatible with HiFi 2 codecs and even has a little performance improvement, maybe 10%. But by updating the code to take better advantage of HiFi 3’s capabilities a typical codec is improved by over 20%.

HiFi 3 will enable more post processing of home entertainment, for example matching the processing to the room and speaker environment. Similarly smartphones will require much more complex audio for immersive gaming experience. On the voice coding, the requirement are actually outpacing what even Moore’s law can deliver, requiring increasing processing to deliver better noise suppression, noise dependent volume control and so on.


Posted on

Synopsys, the first 25 years

Synopsys, the first 25 years
by Paul McLellan on 01-08-2012 at 8:00 pm
Categories: EDA, Synopsys

Synopsys was started in 1986 and so 2011 was its 25th anniversary. They created a little timeline with some of their history. As with most companies, the earlier history is the most interesting, before it was clear what the future would bring. From 1986 to 1990 they grew to $22M in revenue, which was explosive growth. So explosive that Geoffrey Moore used them as an example in his follow-up to Crossing the Chasm, called Inside the Tornado.

One area they list on the timeline are the key acquisitions. It is interesting to look at these and see the focus of both Synopsys, broadening out from being a pure synthesis company, and EDA in the wider sense broadening and addressing new challenges.

  • Zycad 1990 VHDL simulation (they didn’t acquire the hardware acceleration biz)
  • Logic Modeling 1994 high level functional modeling
  • Epic 1997 transistor level analysis
  • Viewlogic 1997 quad motive timing, sunrise test, some system products
  • Avant! 2002 place and route, physical verification, circuit simulation, cell libraries
  • InSilicon 2003 silicon IP
  • Numerical Technologies 2003 DFM lithography technology
  • Synplicity 2008 FPGA synthesis
  • Virage Logic 2010 IP portfolio
  • Ora 2010 optical design

and, of course (probably):

  • Magma 2012 place and route, timing verification, circuit design, physical verification, analog design

When I was at Cadence we had a sort of family tree that showed all the acquisitions. Not just the ones Cadence had made but the prior ones that went into making up the companies that were acquired. It would be interesting to see a similar family tree for Synopsys if it exists. We have some of the raw data hereon the EDA Mergers and Acquisitions Wiki but without the graphic design and the logos.

Posted on

Interface Protocols, USB3, HDMI, MIPI… the winner and losers in 2011

Interface Protocols, USB3, HDMI, MIPI… the winner and losers in 2011
by Eric Esteve on 01-07-2012 at 11:30 am
Categories: Uncategorized
3 Comments

Releasing a new protocol like ThunderBolt, HDMI or SuperSpeed USB has not only to do with bandwidth performance or form factor of the connector as a guarantee of success. Some non-scientific parameters also play a role in the alchemy, that’s why forecasting the success of a certain protocol is such a hard task, and can’t be reduced to a feature list comparison table. That’s why, even if good marketing campaign can help (in fact is a necessary condition), properly marketing a technically attractive protocol is not sufficient to make it successful in the mass market. Do I know the magic recipe to cook an interface protocol generating high penetration in the mass market? I would be rich if I knew it! But I can try, at least, to understand which protocols are the winners in 2011, demonstrating high market penetration (and becoming “de facto” standard in certain market segments), or fast growing penetration (which is even more useful if you want to grow your business, developing around this protocol). Then, if we can identify winners, some losers should exist as well…

The winners in 2011

HDMIis certainly the most successful protocol, both in term of market penetration in the Consumer/HDTV segment and in term of pervasion in various segments like PC, Wireless Handset (smartphone), Set-Top-Box, DVD players and recorders, Digital Video Camera and more. Analyst consensus is that 2 billion HDMI ports have been shipped since the inception (2004 for the protocol definition, 2006 for the first devices shipped in the market). That’s huge number, and very fast growth rate, as 250 million ports have been shipped in 2007 and we can reasonably expect 1 billion ports to be shipped this year. If we look at the protocols in competition with HDMI, we find DisplayPortand, to a certain extent, SuperSpeed USB.

DisplayPort has been defined at the same time than HDMI, by the Video Electronic Standard Association (VESA) a non-profit organization. The important word here is profit: when Silicon Image was developing a worldwide and very aggressive strategy to push HDMI standard, creating subsidiaries like HDMI Licensing (to license the technology) and Simplay Labs (to offer testing and certification capabilities, in fact a mandatory step to get the HDMI stamp), as the company wanted to be in a position to get the maximum benefit from the technology they had developed, VESA was… very quiet!

Things are changing now, as DisplayPort is starting to see a real momentum, this is why the protocol is in the winner list. Effectively, DisplayPort adoption has strongly grown in 2011, for various reasons: at first, the protocol is well tailored for interfacing a PC and a screen, that’s naturally here that the adoption is high. The second reason has to see with the marketing effort made by two heavyweight of the electronic industry: Intel and Apple. Apple is using DisplayPort for some time now, and Intel has created a strong buzz around DisplayPort, not directly, but when promoting ThunderBolt(defunct Light Peak), multiplexing DisplayPort and PCI Expressin the same link. Anyway, the result is there: DisplayPort technology start to be used, the Verification IP for the protocol are selling well (which is a sign, in advance from the mass market real sales, that developments are occurring, leading to product launch a few quarter later). SuperSpeed USB or USB 3.0 has been mentioned in this paragraph, in fact it is “a contrario” (I like Latin words, it make me feel highly educated), as USB 3.0 should be ranked in the losers, no doubt about it, as we will see in the next paragraph.

Another protocol is seeing a wide adoption, and very fast growing IP sales: DDRn. Even if it can be questionable to rank it in the Interfaces Protocol, DDRn is a mean to interconnect a SoC with memory, using a digital part (Controller) and a physical media access (PHY), so it’s built like every other modern high speed serial technology, even if it’s still parallel, “scricto sensu”. As we have shown in the “Interface IP Survey”, DDRn adoption is now a matter of fact for any SoC design, the key point is that design team tend now to source it externally, one of the reasons being the growing difficulty to manage higher speed transfer rate (up to 2 GT/s for DDR4). IPNEST has forecasted DDRn IP sales to be the largest, when compared with the other Interface IP, passing $100M in 2013.

MIPIis a specification (not a standard according with the MIPI Alliance) that smartphone users are probably running everyday (every second), but they don’t know it. I don’t think we will ever see a marketing campaign labeled “MIPI inside”, as MIPI is more like a commodity, allowing various IC to speak together inside the handset, for now, and other mobile electronic devices in the near future, than a flagship technology. Even if the technology is very smart, allowing to standardize many different interfaces with IC controllers for Camera, Display, Flash, RF or audio.

So far, IPNEST evaluation is that 700 million IC supporting MIPI have been shipped in 2011, exclusively in the handset/smartphone segment (more than 400 million smartphones have been shipped over the same period). Looking at the IP sales for MIPI is a bit disappointing, as these are far to be at the level of HDMI in 2011, the reason is simply that the first MIPI adopters, the Application Processor chip makers, have probably used internally designed IP rather than source it to IP vendors. This will certainly change when the Tier 2 chip makers for Application Processor and the companies targeting other market segments like PC and Media Tablet or Consumer (Mobile) Electronic Devices will adopt MIPI. Which is funny here is that the end user will probably never know that he is using MIPI, when he certainly knows that his device support HDMI or USB.

Still in the winner list, but at a lower extent, we can rank PCI Expressand SATA. PCI Express pervasion has been strong in almost every segment (except in Wireless handset, Consumer electronic or Automotive), generating growing IP sales year after year to reach $40M in 2010, when SATA is obviously staying strong in storage equipment, but only here. Five years back, some people thought that SATA could be replaced by other protocols (USB 3.0 or PCI Express) but this will not happen. Which is likely to occur is the merger between SATA and PCI Express, to generate something called SATA Express, to serve the new needs generated by Flash based storage.

And now the losers…

To me, one of the most disappointing events of 2011 was the take off absence of SuperSpeed USB. This coming after the same disappointment in 2010… and in 2009. The technology was ready (back in 2008), proven (at least the PHY, very similar to PCI Express gen-2) and expected by the market. But Intel decided to delay, over and over, the support of USB 3.0 in their PC chipset, expected now to come in April 2012! It seems that, five or six years back, the USB-IF has strongly missed their mission. The market was expecting high speed interface protocol, that they could use to download or exchange video. At that time, HDMI was just about to be launched and High Speed USB was already five years old. It was the right time to launch SuperSpeed USB, with an attractive slogan “10 time faster than USB HS”. What did USB-IF? They launch USB On-The-Go, which maybe is a nice to have feature, but far to be revolutionary! More like an engineer’s dream than a marketing vision if you prefer.

I am afraid that, even if USB 3.0 will certainly see a wide adoption in 2012 and 2013, seeing IP sales doubling in 2012, USB standard has missed the right window, and will never recover (in term of penetration) as in the meantime HDMI has became the “de facto” standard for imaging. Because integrating too many connectors is prohibiting in term of cost on the consumer market, OEM will have to make a choice and you can guess that they will not get rid of HDMI connector (even if they are hungry to pay 4 cent per port to Silicon Image). SuperSpeed USB market will survive and generate IP sales, but will never reach the level of ubiquity that USB has reached in the past.

I realize that I did not talk about ThunderBolt, but what to say about it? It has been adopted by Apple, to be used in the high end PC segment and some Digital Still Camera makers will propose it. But, as of today, ThunderBolt controller can’t be integrated into a SoC, it can’t be sold as an IP function, this means it will be more difficult to build an ecosystem around it. It’s perceived as an Intel/Apple “proprietary” function, this may not be the best way to a wide adoption (think about FireWire).

There is still some high speed serial, differential, protocol standards that I did not mentioned: Serial RapidIO, Hyper Transportor Infiniband. If you don’t know it, if you don’t use it now, you can keep in peace, as all of these should stay in their niche, or even disappear…

Eric Esteve – from IPNEST– Above graphic extracted from “Interface IP Survey” available here

Posted on

Economist on ARM vs Intel

Economist on ARM vs Intel
by Paul McLellan on 01-06-2012 at 7:16 pm
Categories: Arm, Intel Foundry, IP

The Economist has a big article (may need a subscription, can’t tell because I have one, it’s in the print edition too) about ARM versus Intel. It is an interesting read since I think it misses so much of what really drives semiconductor. It tells the story about Intel trying to get into mobile (because it’s main market isn’t growing, but ignoring margins and memories) and ARM trying to get into servers (ignoring almost everything important).

It is an interesting mixture of perceptive insight into the business combined with total ignorance of technology. How about this for crystallizing the RISC vs CISC argument:Acorn, a then-marginal and now-defunct British computer-maker, had a niche in designing chips good at carrying out only a few types of calculation, but which did so very quickly. This reduced-instruction-set computing (RISC) approach requires software that can make up for the limitations of the chips, but uses less power than other approaches.

And, as a 15-year veteran of VLSI Technology, this paragraph was an painful cut:In 1990 Apple, struggling itself, needed a chip for its Newton, a personal digital assistant that was to restore the company’s fortunes. It liked Acorn’s chip designs: the two formed Advanced RISC Machines as a joint venture with a chipmaker.

A chipmaker. Whose name must not be spoken. Although to be fair since VLSI was swallowed by Philips and spun out into NXP and then sold to ST-Ericsson (mostly), maybe that is too much of a distraction.

I think the article is clearly written by someone based in London, with a bit of ARM rose-tinted glasses. It portrays Intel as vulnerable and ARM, with its ecosystem, as having high barriers to entry (which it does for someone new, although for Intel maybe not so much).

For a magazine called the Economist, it misses a lot of the economics of semiconductor, namely how much money Intel makes per chip and how little ARM does. Plus the fact that Intel is 1-2 process generations ahead of any of ARM’s licensees (well, technically Intel is an ARM licensee having bought Infineon’s cell phone business, although it is switching everything to Atom).

But it’s nice to see a mainstream coverage of a niche that usually is only covered by less prestigious “newspapers” (as the Economist insists on calling itself) such as…err…SemiWiki. We may not have the prestige but we do, mostly, know what we are talking about.

Posted on

VLSI 2012 in Hyderabad

VLSI 2012 in Hyderabad
by Paul McLellan on 01-06-2012 at 3:59 pm
Categories: EDA

Atrenta will be on a panel session at VLSI 2012 next week in Hyderabad in the center of India. Since I had a development group there over a decade ago this is actually one of the few cities in India that I have visited. Beautiful but very hot at the time I was there.

Atrenta will be represented by Sathyam Pattanam the director of engineering for GenSys and SpyGlass Low Power products. The panel is titled “SoC Realization — a bridge to new horizons or a bridge to nowhere?” It won’t be a surprise to discover that Sathyam is on the new horizons side of the argument.

The other panelists are:

  • Broadcom – Subhash Chintamaneni, Senior Manager, DTV Division
  • Cadence – Raju Pudota, Group Director, Flash IP Engineering
  • Freescale – Ganesh Guruswamy, Vice President and Country Manager
  • InfoTech Enterprises – Ram Gollapudi, General Manager, Hi-tech Business Unit
  • Seer Akademi – Srikanth Jadcherla, Chairman and CEO, Electronics Education Company
  • ST – Rajamohan Varambally, Director Technology R&D
  • Synopsys – Vikas Gautam, Director, Verification and IP products
  • TI –Mahesh Mehendale, TI Fellow and Director, Center of Excellence for VLSI Architectures

The panel will be moderated by Professor P.P. Chakrabarti of IIT Khragpur. It takes place on Monday 9th January from 5.25pm to 6.40pm at the Hyderabad International Convention Center.

Details on the conference are here. It’s actually worth a look just to see an “interesting” web design. I think they managed to use every HTML tag in existence on just one page.

UDPATE: HOW THE PANEL SESSION DEVELOPED

Due to some last-minute changes, the panel was moderated by Sathyam K. Pattanam, Senior Group Director from Atrenta Inc.

The final list of panelists were: Subhash Chintamaneni (Senior Manager, DTV Division, Broadcom), Raju Pudota (Group Director, Flash IP Engineering, Cadence), Sanjay Gupta (R&D Head, Automotive and Industrial Engineering, Freescale), Ram Gollapundi (General Manager, High Tech Business Unit, Info Tech Enterprises), Srikanth Jadcherla (Chairman and CEO, Electronics Education, Seer Akademi), Rajamohan Varambally (Director, Technology R&D, ST), Vikas Gautam (Director, Verification and VIPs , Synopsys), Mahesh Mehendale (Fellow and Director, Center of Excellence for VLSI Architectures, TI) and Sathyam K. Pattanam (Senior Director Engineering, Atrenta). There was good representation from electronics system, semiconductor, and design automation companies.

The session was attended by over 200 engineers from various companies and universities. The panel topic was introduced by Sathyam, followed by each panelist’s viewpoint, a Q&A session and then a final summary.

The panelists discussed the challenges of designing SoCs with over 100 million gates for a wide range of markets, including wireless, set top box, automotive and medical. Challenges include rising costs, time-to-market pressure and increasing SoC complexity. The group emphasized the need to close the gap between today’s System Realization and Silicon Realization disciplines. SoC Realization holds promise to accomplish this with new methodologies and tools for: IP readiness and reuse, SoC architecture definition, assembly and verification, power, performance and area estimation/analysis, hardware/software optimization and system verification.

Posted on

Tracking the Big Semiconductor Story of 2012

Tracking the Big Semiconductor Story of 2012
by Ed McKernan on 01-06-2012 at 3:56 pm
Categories: Foundries, Intel Foundry, TSMC

It’s just a matter of time – perhaps just a few months – before the greatest mystery of the semiconductor industry is revealed and the peaceful co-existence of the Fab vs Fabless world is blown apart. An arms race was started by Intel to challenge TSMC and Samsung on who would control not only the high valued processor but soon to be much higher valued NAND Flash and SRAM that define mobility and data center peak performance efficiency. It is not, as many may claim, a battle between x86 and ARM architectures, it is rather an SRAM – NAND dominant memory based platform battle. The shift in our understanding will help explain the mystery as to why Intel is doubling Fab capacity starting in 2012 with the 22nm process even though the PC and server markets are expected to grow in low double digits.

I have written previously about the $10.8B capex build that Intel just completed in 2011. During these past 12 months at every earning call or analyst conference, Intel executives have been cross checked on the wisdom of the massive build out and whether there would be delays, slowdowns, cancellations, pushouts etc… Otellini and company stuck to the strategy and to add a little gasoline to the fire decided to bedevil the analysts with dividend hikes and massive stock buybacks, which will accelerate earnings in 2012 and beyond. This is like FDR telling the war department to get cranking on 50 more aircraft carriers in 1944-45 after having built 83 in the two years prior even though the remaining Japanese carriers numbered in the single digits and the Germans had none to begin with.

It finally occurred to me over the holidays as I was reading the estimates of the Ivy Bridge die size at roughly 25% smaller than the 32nm Sandy Bridge die that Intel had much bigger plans in store for 2012. Ivy Bridge is a shrink of Sandy Bridge with a beefed up graphics controller in order to support DirectX 11 but unlike previous shrinks – there are no additional processor cores. And yet Intel has rushed the conversion of three fabs to 22nm, added a 4[SUP]th[/SUP] fab for 22nm, broke ground on a 14nm development fab that is 60% larger than the previous in order to ramp production immediately and then to top it off decided to build a new 14nm production Fab for late 2013 production ramp. According to Intel, total fab square footage by end of 2013 will be twice what it is today. There are three possible markets, beyond what Intel is building for today that will take advantage of this capacity – and I believe all three will see the light of day in 2012.

The first and obvious one is that Apple will be moving into Intel’s Fabs starting sometime in 2012. Apple’s incredible growth planned for 2012 based on roughly 300M CPUs (Closing in on the number of x86 chips Intel ships) can only be stopped by the words “Lines Down.” The Japanese earthquake and Thailand Floods have exposed the fallacy of the taut just-in-time manufacturing philosophy. No amount of build-ahead stocking can be as effective or economical to Apple as having multiple Fabs building the same product worldwide with guarantees of upside to replace any loss due to “Acts of God” or the imposition of trade barriers that are in the thoughts of many politicians. Furthermore, one can not overlook the trashing of the US dollar that has taken place during the Bush-Obama years that works to the favor of companies who have production facilities in the US (thus Samsung’s new Fab in Texas). Ensconced in Taiwan, TSMC’s business model is at risk to being uncompetitive if the dollar continues to decline. Intel, on the other hand is way ahead of the curve with Fabs in Oregon, Arizona, New Mexico, Ireland and Israel. And when all the dust settles, will probably pickup a certain fab in Dresden at fire sale prices in order to setup a very public cross Atlantic Ocean auction to decide who will be home for the world’s first 450mm wafer. Unless America has a Sputnik Moment, my bet is on the region with the better Bureaucrats.

Tim Cook’s master logicians have implemented the world’s first Virtual Vertical Manufacturing Operation with relatively little money down but first dibs on the latest technologies at Costco prices. They will not have the same leverage with Intel but they will gain access to the process technology that Qualcomm, nVidia, Broadcom and the rest will not have. So Intel can still make 60% Gross Margins while Apple undercuts their rivals in die size, packaging size, power and cost. 22nm is the process that is sending fears through the fabless community (as Morris Chang recently noted) as Intel has reduced standby power by 10X, meaning ARM’s mobile advantage is gone. Though they operate on different game plans, Intel and Apple have a common goal of knocking Samsung out of the game in order to dominate their respective markets and so they will become Allies in this endeavor. Longer term, Apple will need Intel’s process technology in order to smother Amazon’s tablet effort before it gains steam.

Micron’s latest earnings conference call can be described in short as toss the DRAM overboard, it’s Game-On in the battle for NAND Flash Supremacy. The Intel-Micron joint venture looks to leverage Intel’s process lead with Micron’s low overhead business model to win the battle for not only SSDs but also in the die stacked x86CPU+Chipset+NAND configuration that will see uplift in the ultrabook market in 2013. Intel will drive ultrabooks in ever smaller, thinner formfactors while raising their semiconductor content to the exclusion of AMD and nVIdia. If Samsung wants a piece of the action, then they may need to acquire AMD and head down the same road. The market dynamics here offer tremendous upside to Intel and will be the 2[SUP]nd[/SUP] area of Fab capacity utilization.

The third market segment that Intel will attack with its new fab capacity is one that is so logical that I can’t believe it is not being discussed more in the semiconductor techno-sphere. And yet to understand it you have to make a connection to the business opportunity that has been discussed in bits and pieces by Otellini and Data Center VP Kirk Skaugen. Back in the first half of 2012, Skaugen mentioned that Intel’s highest end Xeon processor that sells for over $4000 offered the best ROI to data center customers. The payback they saw in using high end Xeons was in months not years. Furthermore, Intel has raised prices on Xeon and not seen push back, meaning prices will continue to march higher. The ROI is driven by the large Level 3 (L3) caches that allow workloads to stay on chip instead of going to DRAM. So the logical conclusion is that Intel should build even bigger caches and charge more money. However the current Xeons are maxed out on die size.

This is where I see Intel building L4 caches stacked with the Xeon die and offering a new level of performance/watt that can be priced hundreds to thousands of dollars more than the current Xeons. What’s more this new business opportunity allows Intel to ramp 14nm sooner (as they have stated is their goal) with an SRAM product that serves as the process pipe cleaner and is a natural as a much faster yield ramp than any processor Intel builds. The new L4 Cache can eat up lots of wafers, effectively that generate 80-90% gross margins and become a new multi-billion $ business.

In just two short years, as 14nm begins to ramp, Intel will be completely transformed as a company. The x86 vs ARM battle will not be fought as the analysts expect. Dominance in the semiconductor business will have been fought over the superiority of the closely coupled CPU – SRAM – NAND platform of which the latter two will play a greater roll in the value of a platform and end up consuming the most die area and wafers in the Fab. The CPU instruction set and architecture are small potatoes in the overall platform.

Of the three contenders, Intel is the best positioned with process technology and current market standing to move mobiles and servers over to the new memory dominating platforms. Samsung is fighting a two front war with Apple and Intel. TSMC is behind in process technology and SRAM design and does not have a play in NAND – perhaps we will see a partnership form with a leading NAND player.

And so now we can sit back and watch how the biggest semiconductor story of 2012 unfolds as Intel launches its 22nm process.

FULL DISCLOSURE: I am Long AAPL, INTC, ALTR, QCOM

Posted on

What Dolpin Technology Uses for SPICE Circuit Simulation of IP

What Dolpin Technology Uses for SPICE Circuit Simulation of IP
by Daniel Payne on 01-06-2012 at 12:32 pm
Categories: Uncategorized
8 Comments

Mo Tamjidi founded two Semiconductor IP companies Virage Logic and Dolphin Technology. After reading a press release about how Dolphin Technology is using FineSIM SPICE from Magma I decided to contact him and learn more about why they are now using that circuit simulator in the design of their memory, standard cells, and IO cells.

Continue reading “What Dolpin Technology Uses for SPICE Circuit Simulation of IP”

Posted on

EDA Vendors Providing Secure Remote Support for an IC Design Flow

EDA Vendors Providing Secure Remote Support for an IC Design Flow
by Daniel Payne on 01-05-2012 at 5:38 pm
Categories: EDA, Siemens EDA

In my last corporate EDA job I had customers in Korea that were evaluating a new circuit simulator and getting strange results. When I asked, “Could you send me your test case?” the reply was always, “No, we cannot let any of our IC design data leave the building because of security concerns.”
Continue reading “EDA Vendors Providing Secure Remote Support for an IC Design Flow”

Posted on

Is Indian Semiconductor Relevant?

Is Indian Semiconductor Relevant?
by Daniel Nenni on 01-03-2012 at 9:42 pm
Categories: General

A common discussion amongst semiconductor professionals is the ROI of development activity in India. An interesting number I remember hearing at Virage Logic was that the development groups in India had a 30%+ turnover rate. Is that still the case? If so, that is very hard on the ROI.

Here are the 2012 SemiWiki geographical statistics from India as another data point on the relevance of semiconductor in India:

According to LinkedIn there are 14,897 semiconductor professionals in India out of a total of 137,799 on LinkedIn (10%+). All of the big semiconductor companies are there: 1,994 have worked for Intel, 321 for Samsung, 786 AMD, 474 Qualcomm, and 495 Broadcom. EDA companies as well: 167 Mentor Graphics, 557 Cadence, 699 Synopsys. IP companies too: 322 ARM. Data is so much fun to play with.

So you tell me, is India relevant for semiconductor design and manufacturing? Is the Indian Government helping? What does the future hold?

Speaking of Indian Semiconductor (nice Segway) it was interesting to read that one of my favorite EDA companies, Berkeley Design Automation, was announced as the winner of the Indian Semiconductor Association’s TECHNOVATION 2011 award. This award is one of the most prestigious for Electronics and Semiconductors in Asia. The award recognizes the most innovative multinational company with R&D operations in India.

“The ISA Technovation awards of December 2011 have been constituted with an aim to recognize and honor India’s best individual contributors and organizations that drive the semiconductor and ESDM industry forward,” said Mr. PVG Menon, President of ISA. “Berkeley Design Automation won this award as recognition of the company’s breakthrough leadership and technical innovation in nanometer circuit verification.”

BDA competed against 80 other multinational companies with operations in India and came out on top for innovations and advances in nanometer circuit simulation. Believe it or not, BDA was the first EDA company to win this award!

The other news I have from India is the 25[SUP]th[/SUP] International Conference on VLSI Designwill be next week in Hyderabad. Unfortunately/fortunately, next week I will be in Las Vegas for CES with my beautiful wife. You can meet us at the GlobalFoundries party, on the floor of the conference, or the Hilton Resorts Spa.

Magma CEO Rajiv Madhavan is a keynote speaker, that should be interesting. Other keynotes are from Intel, AMD, Zilinx, IMEC, Cadence, and some University people. The most interesting panel looks to be:

“SoC Realization – A Bridge to New Horizons or a Bridge to Nowhere?” System on Chip (SoC) Realization is the emerging market that bridges the gap between an electronic system concept and its implementation in silicon.Professor P.P. Chakrabarti, IIT Kharagpur, will moderate the panel to explore and discuss the meaning of SoC Realization and its impact on the cost and schedule for advanced SoC designs.

  • Atrenta – Mr. Sathyam Pattanam, Senior Director Engineering
  • Broadcom– Subhash Chintamaneni, Senior Manager, DTV Division
  • Cadence– Raju Pudota, Group Director, Flash IP Engineering
  • Freescale– Ganesh Guruswamy, Vice President and Country Manager
  • InfoTech Enterprises– Ram Gollapudi, General Manager, Hi-tech Business Unit
  • Seer Akademi –Srikanth Jadcherla, CEO, Electronics Education Company
  • ST– Rajamohan Varambally, Director Technology R&D
  • Synopsys –Vikas Gautam, Director, Verification and IP products
  • TI–Mahesh Mehendale, TI Fellow and Director, Center of Excellence for VLSI


Atrenta is also a favorite of mine. Offering a superior level of abstraction, they put the realizationin SoC Realization! With a superior level of accuracy, BDAputs the realizationin Silicon Realization!

Posted on

Altera’s New Dual ARM® Cortex™-A9 SoC Arria® and Cyclone® V FPGA Families

Altera’s New Dual ARM® Cortex™-A9 SoC Arria® and Cyclone® V FPGA Families
by Daniel Nenni on 01-03-2012 at 7:29 pm
Categories: Arm, FPGA, IP

Altera recently introduced versions of their new Arria® and Cyclone® V FPGA families that incorporates a dual ARM®Cortex™-A9 MPCore hard core. These parts are particularly interesting to NARD as it’s consistent with the NARD concept of offering platforms unified by a common ARM® host core and a variety of controller/coprocessor cores. Continue reading “Altera’s New Dual ARM® Cortex™-A9 SoC Arria® and Cyclone® V FPGA Families”