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VLSI 2012 in Hyderabad

VLSI 2012 in Hyderabad
by Paul McLellan on 01-06-2012 at 3:59 pm

 Atrenta will be on a panel session at VLSI 2012 next week in Hyderabad in the center of India. Since I had a development group there over a decade ago this is actually one of the few cities in India that I have visited. Beautiful but very hot at the time I was there.

Atrenta will be represented by Sathyam Pattanam the director of engineering for GenSys and SpyGlass Low Power products. The panel is titled “SoC Realization — a bridge to new horizons or a bridge to nowhere?” It won’t be a surprise to discover that Sathyam is on the new horizons side of the argument.

The other panelists are:

  • Broadcom – Subhash Chintamaneni, Senior Manager, DTV Division
  • Cadence – Raju Pudota, Group Director, Flash IP Engineering
  • Freescale – Ganesh Guruswamy, Vice President and Country Manager
  • InfoTech Enterprises – Ram Gollapudi, General Manager, Hi-tech Business Unit
  • Seer Akademi – Srikanth Jadcherla, Chairman and CEO, Electronics Education Company
  • ST – Rajamohan Varambally, Director Technology R&D
  • Synopsys – Vikas Gautam, Director, Verification and IP products
  • TI –Mahesh Mehendale, TI Fellow and Director, Center of Excellence for VLSI Architectures

The panel will be moderated by Professor P.P. Chakrabarti of IIT Khragpur. It takes place on Monday 9th January from 5.25pm to 6.40pm at the Hyderabad International Convention Center.

Details on the conference are here. It’s actually worth a look just to see an “interesting” web design. I think they managed to use every HTML tag in existence on just one page.

UDPATE: HOW THE PANEL SESSION DEVELOPED

Due to some last-minute changes, the panel was moderated by Sathyam K. Pattanam, Senior Group Director from Atrenta Inc.

The final list of panelists were: Subhash Chintamaneni (Senior Manager, DTV Division, Broadcom), Raju Pudota (Group Director, Flash IP Engineering, Cadence), Sanjay Gupta (R&D Head, Automotive and Industrial Engineering, Freescale), Ram Gollapundi (General Manager, High Tech Business Unit, Info Tech Enterprises), Srikanth Jadcherla (Chairman and CEO, Electronics Education, Seer Akademi), Rajamohan Varambally (Director, Technology R&D, ST), Vikas Gautam (Director, Verification and VIPs , Synopsys), Mahesh Mehendale (Fellow and Director, Center of Excellence for VLSI Architectures, TI) and Sathyam K. Pattanam (Senior Director Engineering, Atrenta). There was good representation from electronics system, semiconductor, and design automation companies.

The session was attended by over 200 engineers from various companies and universities. The panel topic was introduced by Sathyam, followed by each panelist’s viewpoint, a Q&A session and then a final summary.

The panelists discussed the challenges of designing SoCs with over 100 million gates for a wide range of markets, including wireless, set top box, automotive and medical. Challenges include rising costs, time-to-market pressure and increasing SoC complexity. The group emphasized the need to close the gap between today’s System Realization and Silicon Realization disciplines. SoC Realization holds promise to accomplish this with new methodologies and tools for: IP readiness and reuse, SoC architecture definition, assembly and verification, power, performance and area estimation/analysis, hardware/software optimization and system verification.

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