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Semiconductor Expert Forum

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SystemVerilog from Nevada?

SystemVerilog from Nevada?
by Daniel Payne on 08-16-2012 at 10:58 am
Categories: Aldec, EDA

When I think of EDA companies the first geography that comes to mind is Silicon Valley because of the rich history of semiconductor design and fabrication, being close to your customers always makes sense. In the information era it shouldn’t matter so much where you develop EDA tools, so there has been a gradual shift to a wider geography. Aldec is one of those early EDA companies that started in 1984, just three years after Mentor opened it’s doors, however Aldec is headquarteredin Nevada instead of Silicon Valley. I wanted to learn more about Aldec tools and decided to watch their recorded webinar on System Verilog.

The first time that I used Aldec tools was back in 2007 when Lattice Semiconductor replaced Mentor’s ModelSim with the Aldec Active-HDL simulator. I updated a Verilog training class and used Active-HDL for my lecture and labs delivered to a group of AEs at Lattice in Oregon. Having used ModelSim before it was actually quite easy for me to learn and use Active-HDL. For larger designs you would use the Aldec tool called Riviera-PRO.

Webinar

Jerry Kaczynski presented the webinar, he’s a research engineer at Aldec, and has been with the company since 1995. His background includes working on simulator standards. With 53 slides in just 65 minutes the pace of the webinar is brisk, and filled with technical examples, no marketing fluff here.


SystemVerilog came about because Verilog ran out of steam in the verification side. Accellera sponsored SystemVerilog and the first standard to extend Verilog in 2005, then by 2009 Verilog and SystemVerilog became merged. SystemVerilog has various audiences:

  • SystemVerilog for Design (SVD) – for hardware designers
  • SystemVerilog Assertions (SVA) – both design and verification
  • SystemVerilog Testbench (SVTB) – mostly verification
  • SystemVerilog Application Programming Interface (SV-API) – CAD integrators

SVD
Verilog designers get new features in SystemVerilog like:

  • Rich literals: a= ‘1; small_array='{1,2,3,42};
  • User-defined data types
  • Enumeration types (useful in state machines)
  • Logic types (can replace wire and reg)
  • Two-value types (bit, int) – simulates faster than 4 state
  • New operators (+=, -=, *=, /=, %=, &=, |=, <>=)
  • Hardware blocks (always_comb, always_latch, always_ff)
  • Implicit .name connections for modules, also implicit .* connections in port list
  • Module time (timeprecision, timeunit)
  • Conditional statements (unique case, priority keyword – replaces parallel case and full case pragmas)
  • New do/while Loop statement
  • New break and continue controls

  • Simpler syntax for Tasks and Functions
  • New procedural block called final
  • Aggregate Data Types (Structures, Unions, Arrays – Packed, Unpacked)
  • Structures added (like the record in VHDL or C struct)
  • Unions added
  • Array syntax simplified

  • Special unpacked arrays (Dynamic, Associative, Queues) – not synthesizable
  • Packages – organize your code better using import

SVA
Assertions are used in property based design and verification, and they look at the design from a functionality viewpoint.

  • Look for illegal behavior
  • Assumptions on inputs
  • Good behavior, coverage goals

  • HW designers add assertions in code to document and verify desired behavior
  • System level designers can add protocol checkers at top level
  • Verification engineers can add verification modules bound to an object to monitor behavior

SV Interfaces
For communicating between modules SV Interfaces bring new abilities and less typing:

SV Testbench

  • Class is used for OOP
  • Inheritance – reuse previous classes
  • Polymorphism – same name do different things depending on class
  • Abstract classes – higher level
  • Constrained random testing (CRT)
  • Spawn threads

  • Mailbox (type of Class) – FIFO for message queue
  • Functional Coverage – coverage analysis (covergroups, coverpoints, bins)

Verification Methodologies

  • Verification Methodology Manual (VMM) – created by Synopsys, both testbench and design as SystemVerilog
  • Open Verification Methodology (OVM) – created by Mentor and Cadence, has SV and SystemC testbench with design files in any language
  • Universal Verification Methodology (UVM) – created by Accellera to unify VMM and OVM
  • Teal/Truss – by Trusster as Open Source HW verification utility and framework in C++ and SV

Q&A
Q: What tools support SVA?
A: SVA is included in Riviera-PRO simulator.

Q: How could I use SystemVerilog in my VHDL testbench?
A: You could bind SystemVerilog as checkers, then connect them to entities or components in VHDL.

Q: What is difference between logic and reg?
A: Logic is more than reg, also used where wire was used.

Q: Can I connect VHDL inside of SystemVerilog?
A: That’s not controlled by a standards body, so it’s tool specific.

Q: Can I synthesize a queue?
A: No, not really today.

Q: How are modports related to assertions?
A: Not directly related, modports used to define directions of interconnect.

Q: Can we execute random in modules?
A: Random is used for classes.

Q: Will associative arrays handle multi-dimensions?
A: not yet.

Q: Good SV books?
A: Depends on if you do design or verification. Many good choices. Design subset – Sutherland’s book. Browse Amazon.com.

Q: Constrained random test generation details?
A: Just an overview today, sorry.

Summary
SystemVerilog gives the designer richer ways to express hardware than Verilog, more clearly defined intent, better verification with assertions, and use fewer lines of code. It’s about time to upgrade from classic Verilog to SystemVerilog in order to reap the benefits. VHDL designers may benefit from using SV for verification.

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40 Billion Smaller Things On The Clock

40 Billion Smaller Things On The Clock
by Don Dingee on 08-15-2012 at 8:00 pm
Categories: Cadence, EDA

Big processors get all the love, it seems. It’s natural, since they are highly complex beasts and need a lot of care and feeding in the EDA and fab cycle. But the law of large numbers is starting to shift energy in the direction of optimizing microcontrollers.

I mulled the math in my head for a while. In a world with 7 billion people and a projected 50 billion “connected devices”, there are conservatively speaking at least 40 billion smaller things with powerful microcontrollers inside. That’s not counting the small package, jelly bean MCU parts inside a toaster. I’m talking about 32-bit MCUs powerful enough to drive a networking stack, display, and user interface. Billions and billions, as Carl Sagan used to say.

The same art that has gone into designing high-end microprocessors will turn into designing this new breed of microcontroller, with one big difference: power consumption will rule designs, from beginning to end. The microcontroller world has gotten away predominantly with 99% sleep (something I’ve recently seen referred to as “near death” mode, depressing) and relatively low clock rates as the way to conserve power, but that’s going to change as the expectations for connectivity and performance in these new connected devices shift.

Microcontroller and SoC designs turned to massive clock gating a generation ago as a power management technique, dynamically shutting down logic paths not in use at a particular moment. Clock gating on this scale has been a highly manual art, well worth the investment in a large part. (See the discussion on P. A. Semi in my post on the Apple A5 SoC family.)

A little more than a year ago, Cadence quietly purchased Azuro, proponents of clock concurrent optimization. CCOpt does timing-driven placement, logic re-sizing, and clock gating in a single step, rather than leaving the clock gating to man-months of post-design hand optimization, or considering clock gating separately from timing considerations. They’ve integrated that capability into their Encounter Digital Implementation System 11.1.

Broadcom was one of the first companies to grab the CCOpt capability, but they have looked at it from a performance and timing closure perspective, and as a way to increase EDA design throughput by reducing cycle time. It’s a good first step, and they admit one goal is more performance for the same watts.

When the world’s largest MCU company, Renesas, grabs CCOpt and starts using it, they find something quite interesting as they try to reduce MCU power. Their take is the clock network itself consumes 1/3 of the overall MCU power, even on a relatively pedestrian 160MHz part. By using CCOpt, Renesas teams pulled out a 30% reduction in MCU clock power – that’s around 10% of the overall chip power just by optimizing the clock network.

That doesn’t sound like much, but consider there are cars with upwards of 100 MCUs inside, and many of them are always on managing safety, performance, and environmental systems. Renesas shares their outlook for MCUs in cars, and what power consumption means to them.

Automotive is just one area where advanced MCUs will make an impact. Reducing MCU power as 40 billion devices are more and more in the “on” state will draw increasing amounts of EDA attention in the next few years. We’ll see more love flow from the clock gating and optimization practices for big processors down to MCUs soon.

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What’s Inside Your Phone?

What’s Inside Your Phone?
by Daniel Nenni on 08-14-2012 at 7:35 pm
Categories: Ceva, IP

Now that the mobile market is keeping us all employed, take a close look at what is actually inside those devices we can’t live without. Before SoCs you could just read the codes on the chips. Now it is all Semiconductor IP so you have to do a little more diligence to find out what is really powering your phones and tablets. One thing you can be sure is that there are multiple DSP cores doing a variety of tasks and there is a 70% chance they are from CEVA.

CEVA is the world’s leading licensor of DSP cores and platform solutions for themobile,digital home andnetworking markets. For more than twenty years, CEVA has been licensing a portfolio of DSPs, platforms and software to leading semiconductor vendors and original equipment manufacturer (OEM) companies worldwide. CEVA’s IP portfolio includes comprehensive technologies forcellular baseband (2G / 3G / 4G), multimedia,HD video,HD audio,Voice over IP (VoIP),Bluetooth,Serial Attached SCSI (SAS) andSerial ATA (SATA).

CEVA’s technologies are deployed in hundreds of millions of smartphones and handsets every year, and currently power one in every three handsets shipped worldwide. From cellular baseband processing, to audio, voice, multimedia and Bluetooth, CEVA’s broad portfolio of low-power DSP cores and platform IP are ideally suited to wireless handsets applications.

CEVA even has a very nice Wikipedia page:

CEVA was created through the combination of the DSP IP licensing division ofDSP Group (NASDAQ:DSPG) and Parthus Technologies plc in November 2002.[SUP][2][/SUP]The company develops advanced technologies for multimedia and wireless communications chips. CEVA is the world’s #1 DSP architecture deployed in cellular baseband processors[SUP][3][/SUP]In 2011, CEVA reported revenues of $60.2 million and its technology was used in more than 1 billion cellular and electronic entertainment devices. CEVA may be only Israeli company involved in the production of the iPhone.[SUP][4][/SUP]

Combined shipments of smartphones and tablets are expected to grow more than 40% in 2012. Single core devices will become duel core, duel core devices will become quad core, speeds will double again. To date, more than 3 billion CEVA-powered chips have been shipped worldwide. In 2011 alone, CEVA licensees shipped more than 1 billion CEVA-powered products. Recent industry data from The Linley Group reported CEVA’s share of the DSP IP market at 70%.

With more than 200 licensees and 300 licensing agreements signed to date, CEVA’s comprehensive customer base includes many of the world’s leading semiconductor and consumer electronics companies. Broadcom, Icom, Intel, Intersil, Marvell, Mediatek, Mindspeed, MStar, NEC, NXP, PMC-Sierra, Renesas, Samsung, Sharp, Solomon Systech, Sony, Sequans, Spreadtrum, ST-Ericsson, Sunplus, Toshiba, VIA Telecom and Xincomm all leverage CEVA’s industry-leading DSP cores and IP solutions. These companies incorporate CEVA IP into application-specific integrated circuits (“ASICs”) and application-specific standard products (“ASSPs”) that they manufacture, market and sell to consumer electronics companies.

The semiconductor IP business model has evolved into quite a profitable one. The CEVA business model consists of three components; upfront license fees; royalty revenue from every chip sold by customers incorporating CEVA IP, and; revenues from related customer support, development tools and maintenance. CEVA’s 2012 second quarter was the strongest licensing quarter in 3+ years driven by 20+ LTE design wins. Check out the CEVA gallery of products HERE. Impressive!

A Brief History of Semiconductor IP

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Chip-Package-System Solution Center

Chip-Package-System Solution Center
by Paul McLellan on 08-14-2012 at 5:48 pm
Categories: Ansys, Inc., EDA

One of the really big changes about chip design is the way over the last decade or so it is no longer possible to design an SoC, a package for it to go in and the board for the package using different sets of tools and methodologies and then finally bond out the chip and solder it onto the board. The three systems, Chip-Package-System have become so interrelated that everything needs to be concurrently designed. The situation only gets worse once thru-silicon-vias and interposer and true 3D designs are considered.

There are a large number of different issues that come together. The most obvious is various aspects of power, primarily getting the power into the package and distributed across the chip and then getting the heat out again, while also accounting for how the variation in temperature will affect performance. Increasingly, in a modern SoC, everything affects everything else. The temperature goes up which affects the performance which affects the power which affects the temperature.

The leader in having technology for handling this has been Apache. In fact the growth of importance of CPS and the need to adopt a much more formal analysis approach has been one of the drivers of Apache’s revenues and, clearly, one reason that Ansys acquired them.

Apache has a lot of technology in this area and historically it has required trawling their website to pull together everything that you might need. And maybe even going to the Ansys site too. But now everything is in one place the ANSYS/Apache CPS subweb:

  • CPS methodology
  • CPS education
  • CPS new & information
  • CPS blogs
  • CPS user group

If you are interested (and you pretty much have to be if you are doing any of this stuff) in CPS then this is a great resource center. As a starting point, if you have not already read it there is a white paper Chip-Package-System Convergence: ANSYS and Apache Technologies for an Integrated Methodologythat is a pretty good overview of the area.

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Ajoy Bose and Hogan: SoC Realization

Ajoy Bose and Hogan: SoC Realization
by Paul McLellan on 08-13-2012 at 6:47 pm
Categories: EDA

Tomorrow night in Sunnyvale at the National Institute of Technology Alumni meeting, Ajoy Bose and Jim Hogan will talk about different aspects of SoC Realization. I’ve been saying for some time that design is changing and the block level is really where the action is. That is the right level to put together a virtual platform so that the software can be developed, and it is increasing the level at which chips are put together. Increasingly a chip is an assembly of blocks of IP and that assembly process is known as SoC Realization.

Ajoy Bose will talk about how SoC Realization is where high-level concepts are refined to implementation readiness. Legacy and third-party IP blocks are chosen and integrated and the overall chip is prepared for back-end implementation. Getting it right at this stage will dramatically reduce implementation challenges and iteration times. “getting it right” during SoC Realization could lead to the creation of new markets and renewed growth for the industry, but first completing the flow and implementing the vision will require the collaboration of many.

Jim Hogan will talk about Making Money from SoC Realization. Jim wants to focus his EDA investments over the next 5 years in SoC Realization. Part of SoC Realization is validating IP quality and functionality, design assembly and IP integration, design data management, power, performance, and area feasibility checks, debug and analysis tools, memory and memory controllers and bare metal software development.

Increasingly chips are designed using IP and software and the methodologies need to change to adapt to this. There is still often an unspoken assumption that chips are designed by creating a lot of RTL and then running it through synthesis, place and route etc but the reality is that most of the design is re-use of existing IP and software customization.

Look at something like Apple’s A5 chip. Most of the area is a dual ARM core and a quad-core Imagination GPU. Yes, I’m sure there is a little Apple secret sauce in there but primarily large IP blocks being hooked together.

Details on the meeting are here. I’m pretty sure you don’t have to be an alumnus/a from NIT India to attend.

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Interview with Brien Anderson, CAD Engineer

Interview with Brien Anderson, CAD Engineer
by Daniel Payne on 08-13-2012 at 11:15 am
Categories: Cliosoft, EDA

I first met Brien Anderson on LinkedIn because we share common groups and interests, so I decided to interview him and discover how CAD tools enabled IC design at Synpatics, a company with capacitive sensing technology used in smart phones, tablets and touch screens.

Continue reading “Interview with Brien Anderson, CAD Engineer”

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A Brief History of Semiconductor IP

A Brief History of Semiconductor IP
by Daniel Nenni on 08-12-2012 at 7:00 pm
Categories: IP

It is important to note that the System On Chip (SoC) revolution that is currently driving mobile electronics has one very important enabling technology and that is Semiconductor Intellectual Property. Where would we be without the $6B+ commercial semiconductor IP market segment? Computers and phones would still be on our desks for one thing. Semiconductor IP; soft cores, hard cores, physical IP, interface IP, etc… not only reduce the cost and time to market of SoCs, it also dramatically raises the innovation bar.

One of the most interesting and enabling things about the semiconductor IP market segment is the business model that has evolved so I’m going to focus on that. Correct me if I’m wrong here but this is how I remember it.

One of the key enablers for the semiconductor IP market segment was process migration. I remember working with Sagantec in the late 1990’s, their DREAM layout migration tool not only moved IP to new process nodes, it also migrated many different types of IP to multiple foundries including standard cells, embedded memories, and custom IP blocks. One of Sagantec’s biggest customers was Intel who migrated x86 processors down the process road map for multiple generations. This migration technology, IMHO, was one of the catalysts for the semiconductor IP revolution that we are experiencing today.

The other catalyst was the economic downturn of the 1990’s. Semiconductor companies jettisoned internal IP groups to cut costs. These engineers later became IP companies providing products and services to the executives that cut them. Artisan Components and Virage Logic are two of the most notable but there were literally hundreds of others. Both Artisan and Virage were Sagantec migration customers by the way.

While enabling the commercial IP market, layout migration technology also limited the migration tools’ total available market. Standard cells for example; Artisan would build one standard cell library for TSMC and migrate it to multiple foundries and process nodes virtually eliminating internal standard cell library development at semiconductor companies. Virage Logic did the same for SRAMs and many other companies followed suit in other semiconductor IP market segments.

Unfortunately, the IP market got very crowded and ASPs dropped quickly from $1M to $50k for a standard cell library forcing a business model change. Artisan Components gets full credit for this one in my book, they changed from an upfront licensing model to a royalty model backed by the foundries. Seriously, what once cost $1M was now free to customers with a royalty paid to the IP companies by the foundries based on wafer sales. ARM ended up buying Artisan for $900M and Synopsys bought Virage Logic for $350M. The royalty based IP business model was certainly behind these “healthy” valuations, absolutely.

Not to be held hostage by overly aggressive royalty demands, foundries started internal IP development as a complimentary service to promote design starts and wafer sales. Today TSMC has the largest commercial IP catalog and silicon validation program enabling semiconductor IP companies around the world. The TSMC IP effort is industry leading with hundreds of millions of dollars invested in the fabless semiconductor design enablement ecosystem.

ARM has done a similar transformation of the microprocessor market blindsiding even the mightiest of semiconductor companies Intel Corporation. ARM also enabled the SoC revolution with a more balanced business model of upfront license fees, royalty revenue from every chip sold by customers incorporating ARM IP, and revenues from related development tools and customer support. Today the resulting ARM ecosystem is second to none which makes the David and Goliath battle against Intel for mobile, laptop, and cloud SoCs a fair fight.

A Brief History of Semiconductors
A Brief History of ASICs
A Brief History of Programmable Devices
A Brief History of the Fabless Semiconductor Industry
A Brief History of TSMC
A Brief History of EDA
A Brief History of Semiconductor IP
A Brief History of SoCs

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A Brief History of SPICE

A Brief History of SPICE
by Daniel Payne on 08-10-2012 at 4:06 pm
Categories: EDA

SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis and represents a class of EDA software used by circuit designers at the transistor-level to predict the timing, frequency, voltage, current or power of an IC or interconnect before fabrication.

In 1971 there was a tool called CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation) from Laurence Nagel while studying under Professor Ronald Rohrer. SPICE was then developed at UC Berkeley by Nagel in 1972 and first announced on April 12, 1973 by Professor Donald Pederson at the 16th Midwest Symposium on Circuity Theory. Continue reading “A Brief History of SPICE”

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Qualcomm Acquires Intel’s Playbook

Qualcomm Acquires Intel’s Playbook
by Ed McKernan on 08-10-2012 at 12:00 pm
Categories: Arm, Foundries, Intel Foundry

The Mobile Tsunami wave has yet to crest and the surfers strong enough to mount it are dwindling fast to the dismay of market watchers and experienced analysts. The distraction of these past few days is the courtroom drama being played out between the sumo wrestlers, Apple and Samsung, which in the end will not result in a cessation of the Mobile World War. In the background though is a much more interesting battle that is taking place between Intel and Qualcomm. Intel’s game plan is set while Qualcomm rushes to take advantage of open field opportunities. The latest announcement that Qualcomm has hired Intel’s ex-mobile chief Anand Chandrasekher signals an important shift for the communications leader.

The Mobile Tsunami market, which I claim includes Smartphones, tablets andmobile PCs is such a large and growing pie that on first thoughts one could say that there is room for many players to enjoy the spoils. When I was at Transmeta, the CEO would say all we need is 10% of Intel’s x86 market and we will be worth $15B. We didn’t execute at Intel’s cadence and we were rolled. Intel could have been generous and spotted us 10% but it would have disappeared at the next process node. It is important to point out that the larger the market, the more fronts you have to play in and do so competitively to win. Intel is already geared to play in every segment and Qualcomm is not due to their lack of an x86 solution. Going forward though I contend that Intel, Qualcomm, Apple and Samsung are the only players that have the wherewithal on the semiconductor side to build in all segments.

Nvidia just reported their quarterly earnings. Sales were $1.04B up $80M from last quarter. Next quarter sales are to increase by another $100M – $200M. That’s all very nice, now pick up your bat and glove and jump on the next bus to the minor leagues. Neither AMD nor nVidia are scaling their businesses at the rate of Mobile Tsunami and so the undertow will take them out to sea. Perhaps if Broadcom bought nVidia, then the combined company could be a player, given Broadcom’s communications strength and nVidia’s graphics capability. But time is a wasting!

By hiring Anand Chandrasekher, Qualcomm has taken a step that seems to signify that they are about to broaden their focus to include mobile PCs with x86 processors running Windows (yes it will be around for eternity). Intel acquired Infineon’s communications group last year for the purpose of selling the entire platform in PCs, smartphones and tablets. Baseband is the key value added function as we will see with the rollout of 4G LTE this fall. It is a technology that will be available in ultrabooks some time soon. If played right it can exceed the value of Intel’s x86 processors in mobiles.

Anand has in his head the x86 mobile roadmaps, as they existed when he left Intel in May 2011 as well as the understanding of how to fight and win in the mobile PC market. Intel lawyers, no doubt, have sent a nice letter to Anand and Qualcomm stating that Anand must not share any proprietary data in his new work. Don’t worry, the Qualcomm folks will figure out ways to ask questions that hint at the right road to take. Anand, would it be best if we took the road to the left or right today? Mobile Tsunami is about winning in all fronts and Qualcomm knows they have the upper hand with 4G LTE. The demand is so great that they are scrambling to get supply in place to meet demand. The tapeouts to four different Fabs is a sign that they need a massive step ramp on today’s and future products. In addition, they need to be able to negotiate lower wafer pricing with TSMC. It is the alternative to writing a $5B check ahead of time.

However, they can’t rest with just the ARM based Snapdragon. They need to put in place an x86 + 4G LTE product family in order to take Intel’s high mobile ASP advantage away from them and to increase their presence and revenue in a segment that will represent roughly 250MU in three years. It is not, as most have guessed a battle of x86 vs. ARM that determines the winner rather it is an entire mobile platform battle and both processors will coexist. That’s why as an investment strategy investors may decide to own both going forward.

Full Disclosure: I am Long AAPL, INTC, ALTR, QCOM. This article is not a recommendation to buy any stocks mentioned above or in any other one of my postings. Investors must do their own research.

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While you’re reading the SoC manual

While you’re reading the SoC manual
by Don Dingee on 08-09-2012 at 8:30 pm
Categories: EDA, IP, Siemens EDA

There was a day, not too long ago, when a software developer could be intimate with a processor through understanding its register set. Before coding, developers would reach for a manual, digging through pages and pages of 1s and 0s with defined functions to find how to gain control over the processor and its capability. One bit set or cleared in the right place could be the key to making an application work.

Leaps in processor performance and increases in memory size made hand-crafted code less important, and high level languages took hold as a way to increase coding productivity. Developers graduated from bit-twiddling I/O to more sophisticated functions like disk storage and networking stacks and GUIs, and the real-time operating system emerged with code to set up and manage peripherals.

Peripherals started to coalesce on functional standards like USB and SATA, reducing the variety of interfaces programmers had to deal with. Standardized interfaces like PCI and PCI Express and RapidIO further abstracted the peripheral, seamlessly extending the processor beyond the boundaries of its local bus while allowing complex functions to be added.

Then, a funny thing happened: the system-on-chip (SoC) movement took all the exposed functions developers were used to, glued them together and buried them deep inside a complex beast of a chip. While this drove an incredible revolution in size and performance, it has made a nightmare for developers to really optimize their execution environment, accounting for all the capability an SoC presents. In many cases, the IP blocks inside an SoC are black-boxes to developers who hope beyond hope to get a driver that works for an operating system.

While it’s still possible to figure out programming an SoC, excavating into what in some cases is over 2000 pages of documentation for the part not to mention docs for the operating system, it all takes precious time. Developers have to be experts on their application, and smaller departments have little hope of time left over to develop a deep understanding of the SoC inside. This used to be a gap the board vendors would fill, in taking an operating system and creating a board support package with the drivers packaged together. As the value-add of a board vendor working with an SoC diminishes, fewer board vendors are interested, and this task is swinging back to the semiconductor and operating system firms.

In practice today, that’s the only hope for applications running on SoCs: a tight relationship between the semiconductor company and the operating system company that produces abstracted and optimized support for the myriad of functions inside. Otherwise, developers have to be experts on processor cores, caching and MMU operation, graphics, networking, storage, USB, DSP, audio, compression, encryption, and more functions. That’s a 7 or 8 dollar figure effort for a large project, and it’s impossible for projects with typically embedded volumes of a couple thousand.

This new model is taking shape in quite a few places, but perhaps nowhere as broadly as Mentor Graphics. This week, Mentor announced up-to-date support for 42 embedded SoC boards on their RTOS and Linux environments (proving the answer to the universe and everything embedded is actually 42). The philosophy is Mentor’s embedded software teams live with the SoC vendors at the front end, so you don’t have to in order to get a solid starting point for software. Again, they’re not unique in this type of effort, but the range of relationships and architecture support Mentor is putting together is impressive.

You can still read the SoC manual, if you have time. Seriously, what are your views? Is this type of support for SoCs valuable, or can a development team with enough caffeine still do without it? Does open source (read: free) provide enough, or is value-added support worth a reasonable expenditure? Do you know of an example where this type of integrated, value-added support boosted productivity and got a project done faster than thought possible? Or saved a project that got in trouble?

(Disclaimer: Been away a while, long story, happy to be writing again)