SILVACO 073125 Webinar 800x100
Semiconductor Expert Forum

Posted on

Using PCB Automation for an AI and Machine Vision Product

Using PCB Automation for an AI and Machine Vision Product
by Daniel Payne on 12-12-2023 at 10:00 am
Categories: EDA, Siemens EDA

machine vision testing

I knew that HDMI was a popular standard used to connect consumer products like a monitor to a laptop, but most professional video and broadcast systems use the SDI (Serial Digital Interface) connector standard. Pleora Technologies, founded in 2000, currently serves the machine vision and manufacturing markets, including those for military and security high-reliability applications built upon AI and machine vision automation products. One of these is the RuggedCONNECT Smart Video Switcher, used for video capture, processing, streaming, and display. This switcher supports RS-170/NTSC/PAL or 2 HD-SDI video inputs, plus two independent HD-SDI single link displays. Customers require products from Pleora that meet their unique size, energy, and bandwidth requirements.

This blog follows how Pleora got their smart switch to market using EDA tools from Siemens EDA. For video connectivity products the requirement is to network multi-vendor cameras, displays, processors and sensors using standards. Gigabit Ethernet was used in their video switcher, along with GPU and software to enhance video with AI and computer vision processing, enabling situational awareness and ADAS features.

In the case of the RuggedCONNECT Smart Video Switcher, military requirements meant that its boards had to be 1275 certified, as 28V vehicle batteries have to function with voltage spikes up to 250V in magnitude, while remaining quiet to meet rugged emission standards.

EDA Tools

Robert Turzo, Principal Hardware designer at Pleora used the Xpedition Enterprise and HyperLynx tools for the smart switch product design. Critical PCB signals were listed in the constraint manager, plus the DRC feature was used in Xpedition Layout to mitigate issues. They had 13 boards for their system design, and for design reuse they would clone part of an original design to seed the other designs. The seven different via types were stored in a central library with Xpedition, for easy sharing.

Automation performed the matching of the DDR3 and DDR4 interface, instead of manual efforts to meet specifications more quickly. The sketch router feature allowed human-guided auto-routing for multiple nets at a time, saving time and enabled meeting their schedule.

Lab testing of a multi-board system

The smart switcher boards had four stack-ups for their rigid PC, and the fifth stack-up for a rigid-flex PCB. Each impedance-controlled trace was verified on the boards by running the HyperLynx tool. SI/PI (Signal Integrity, Power Integrity) analysis also was performed with HyperLynx in both front-end and back-end of the design process. Only one revision board was required prior to production.  Simulation results performed during design did match the measurements after fabrication, so all that design analysis paid off. Thermal analysis with the Siemens Simcenter Flotherm tool was made easier by using PCB thermal data from HyperLynx.

RuggedConnect, Pleora

Summary

Pleora was successful in their PCB design flow by using Xpedition and HyperLynx software tools on a project with buried vias, stacked micro vias and rigid-flex boards. SI/PI goals were met through analysis in HyperLynx. At the 29th annual Siemens Xcelerator Technology Innovation Awards, Pleora won 1st pace in the multi-board systems category. Read the complete case study online.

Related Blogs

Posted on

Automated Constraints Promotion Methodology for IP to Complex SoC Designs

Automated Constraints Promotion Methodology for IP to Complex SoC Designs
by Kalar Rajendiran on 12-12-2023 at 6:00 am
Categories: EDA, IP, Synopsys

Synopsys Timing Constraints Manager

In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that the design meets its intended objectives. There are also system-level constraints that address requirements and specifications at a broader level, encompassing the entire system or a collection of interconnected components.

As such, applying constraints accurately at various levels of the design hierarchy is essential, whether it is an IP block or a complete SoC that is being designed. At the same time, this process poses significant challenges, particularly across different levels of a complex design hierarchy. As design specifications evolve and intricate IP blocks are integrated into System-on-Chip (SoC) designs, the intricacies of timing, power, and area constraints become tricky. The manual management of this process is highly error-prone, often resulting in inconsistencies and conflicts that may go undetected until later stages of the design cycle.

Additionally, as a design evolves, constraints are refined to meet performance targets, introducing further complexities. The need for precision in propagating constraints from the system level to IP blocks, coupled with the dynamic nature of design iterations, underscores the importance of automated tools and methodologies. Automated constraint management becomes a critical enabler for achieving design predictability, reliability, and ultimately, successful tape-outs. An automated constraints promotion (ACP) methodology not only streamlines the constraint extraction, mapping, and propagation processes but also contributes to error reduction, ensuring that constraints remain accurate and coherent throughout the design evolution.

Synopsys recently hosted a webinar to address the topic of timing constraints management, covering the ACP methodology in the context of utilizing Synopsys Timing Constraints Manager. The webinar closed with the presentation of results from a case study that focused on early release PCIe® Gen6 subsystem timing constraints management.

Synopsys Timing Constraints Manager (TCM) Tool

Synopsys TCM empowers designers with a visual inspection and review capability for promoted constraints, offering a clear representation of their application across various levels of the design hierarchy. This feature facilitates a comprehensive understanding of how constraints are influencing different aspects of the design. Furthermore, TCM’s integration with verification tools plays a critical role in ensuring the accuracy and alignment of promoted constraints with the design intent and specifications. Thorough verification is facilitated through this integration, providing design teams with the confidence that the constraints are in line with the project’s requirements.

Key aspects of TCM’s value proposition include dedicated flows for constraints verification, promotion, and demotion, ensuring constraint integrity across different design hierarchy levels. Equally important is its scalability, catering to diverse IPs and configurations, making it adaptable to the varied complexities of semiconductor projects. TCM’s automation capabilities contribute to a notable turnaround time, reducing constraint-related activities from weeks to days without compromising the integrity of IP constraint reuse.

QuickStart Implementation Kits (QIKs)

Complementing TCM’s capabilities, the Fusion  QuickStart Implementation Kits (QIKs) enhance productivity for design teams using Synopsys Fusion Compiler™, providing a swift start with tailored automation features. Fusion QIKs play a pivotal role in expediting the design process by providing designers with a valuable starting point. Specifically, these kits come equipped with pre-configured constraints, offering a consistent and reliable foundation for design teams embarking on their projects. This jumpstart proves invaluable especially when dealing with intricate designs such as a PCIe Gen 6 subsystem.

Furthermore, Fusion QIKs contribute to the efficiency of the design flow by simplifying the process of viewing and verifying results. Designers can leverage these kits to visualize and inspect results effectively, ensuring that the promoted constraints align with the design intent. This visualization step is crucial for designers to verify the accuracy and coherence of constraints, providing insights at the early stages of the design process and allowing for prompt identification and resolution of any potential issues. Ultimately, Fusion QIKs serve as a valuable tool in enhancing both the speed and reliability of the design process, ensuring a solid foundation for subsequent stages in the semiconductor design workflow.

The Benefits of the TCM/QIK Combo

The integration of TCM, coupled with the strategic use of Fusion QIKs increases the efficiency and accuracy of the design process. This is particularly crucial when dealing with high-speed and complex designs such as PCIe Gen 6 subsystems. The emphasis on early constraint promotion becomes a cornerstone for achieving enhanced design predictability and meeting the demanding timing requirements inherent in intricate designs. The above benefits were corroborated during a case study centered around an early release PCIe Gen6 subsystem configuration. The study spotlighted the critical importance of precise and early constraint promotion at the outset of the design process. Leveraging the Synopsys TCM tool enabled designers to not only address timing constraints but also to identify optimization opportunities related to power and area constraints specific to the PCIe Gen 6 subsystem.

Summary

Synopsys TCM helps streamline the creation and management of timing constraints for subsystems and System-on-Chips (SoCs), mitigating the challenges associated with manual approaches. TCM offers a comprehensive suite of functionalities, covering the entire spectrum from creation and verification to promotion, demotion, and equivalence checking. By adopting Synopsys’ tools and methodologies, design teams can navigate the challenges of the design process more effectively, contributing to successful outcomes in the development of advanced semiconductor products and electronics systems.

For more details, visit the Synopsys Timing Constraints Manager product page.

To listen to the webinar, watch on-demand here.

Also Read:

Synopsys.ai Ups the AI Ante with Copilot

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability

Synopsys Debuts RISC-V IP Product Families

Posted on

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
by Daniel Nenni on 12-11-2023 at 10:00 am
Categories: Defacto Technologies, EDA, Events

Blog UPF Picture1

Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.

WEBINAR REGISTRATION

With the increasing complexity of such designs including challenging power optimization requirements, power intent should be managed right from the start through the design assembly process. RTL & power intent management requires nowadays to be less painful and with a higher degree of automation.

Indeed, a seamless and joint RTL & power intent integration process is beneficial at different levels knowing that power intent management is tightly correlated to the RTL integration process and vice versa. This is mainly explained by the numerous interactions which are needed between logic (RTL) and power intent (UPF) during the building processes and the correlation between RTL and power intent files. Consequently, a joint flow seems to be the good approach to avoids back and forth iterations between SoC/RTL and power engineers.

This joint flow must be able to cope with different scenario and maturity levels of the design project, such IP cores which have or not UPF files, missing power intent definitions at both IP and top levels between RTL and UPF, etc. with almost press button fixes.

The ultimate goal of the tight integration processes is to generate top level, for both RTL and UPF views, ready for synthesis and simulation. A joint flow should be easy to use in order to  enable even non-UPF experts to run the overall logic and power intent integration process.

Figure 1: Tight integration of RTL and power intent in a joint design flow
Key automated capabilities are expected from such a joint RTL & UPF flow as summarized below.
  • RTL vs UPF vs libraries consistency checks

It is key to detect early any inconsistency between logic design and power intent descriptions, including design libraries and any source of information which covers power intent attributes.  Such checks need to be applied at both IP and subsystem levels. A typical example is a port naming mismatch between an RTL and a UPF file (for one or several power control signal). Another one is a   missing power attribute a liberty cell and UPF, etc.

  • Enable fast design learning

Since the joint flow is intended also for non-power experts, design learning capabilities need to be provided though simple APIs to help exploring existing power intent information (power state tables (PST), power switching strategies, etc.) including 3rd party IP cores and subsystems. During the learning process, designers should be able to easily catch missing power intent information such as power definitions and rules.

  • Cross reporting APIs between RTL and UPF

As a joint flow, this should enable to provide cross reporting queries between RTL design and Power intent information. As a typical example, reporting the list of instances with the related power domains and associated supplies will really help designers to understand the correlation between RTL and UPF.

Of course, the related APIs should be intuitive for designers and straightforward.

  • Automated Check & Fix capabilities

The flow should leverage check & fix features between RTL and UPF files. An incoherent name for instance would lead to a press button fix with an automatic update and file generation. Any fix should be automatically reflected from RTL to UPF and vice-versa. Also, power attributes from technology libraries need to be correctly reflected into the generated UPF files.

The power intent consistency must be checked at any time to ensure its completeness. Typically, the detection of missing level shifters and dangling supplies must happen the earliest in the flow to prevent further issues.

Finally, any RTL editing event like adding a new port, renaming a signal or other, should automatically lead to a UPF update.

  • UPF generation at any hierarchical levels

Once the UPF for all the IPs is validated, the Top level UPF needs to be generated. No designer wants to write the Top level UPF manually. Starting from a clearly specified/captured power strategy, the UPF should be generated press-button.

  • Consistent RTL/UPF hierarchical manipulation

As RTL hierarchical changes need to be automated, the same expectation is required for power intent. In a divide and conquer design strategy with physically awareness, hierarchical manipulation is expected to help in many situations such as parallel synthesis, RTL with UPF simulation, etc.

  • Enable efficient Design reuse & data extraction

Power intent needs also to be considered in a reuse process when building new SoC subsystems. Both RTL and UPF require smooth and automated extraction for a particular subsystem specification. UPF promotion and demotion capabilities are subsequently expected to help in this reuse process.

Figure 2: Promotion & Demotion towards an automated power intent management

With its 20 years of expertise in RTL management and more than 10 years in UPF support, Defacto Technologies is providing a mature design solution to answer above needs and requirements from a joint RTL and power assembly flow.

Defacto’s SoC Compiler with its major release 10 covers all of the above requirements regardless UPF versions and RTL languages.

This solution joint RTL & power intent assembly flow pre synthesis is silicon proven and already got excellent results in particular on the UPF promotion and demotion.

Defacto will be holding a webinar by next week (December 14 at 10:00AM PST) where the Defacto experts with present a complete joint RTL & power intent assembly flow including all the steps describes above in the blog:

WEBINAR REGISTRATION

Following the webinar, a Whitepaper will also be available covering detailed explanations on the different steps of the joint flow through a typical design use case.

If any questions or to give a try to this joint flow, the Defacto team can also be contacted through their website: https://defactotech.com/contact

Also Read:

Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology

Defacto Celebrates 20th Anniversary @ DAC 2023!

Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy

Posted on

The First Automotive Design ASIC Platform

The First Automotive Design ASIC Platform
by Daniel Nenni on 12-11-2023 at 8:00 am
Categories: Alchip, Automotive, Semiconductor Services

Alchip Automotive ASIC Design Platform

Alchip Technologies, Ltd. is a company that specializes in ASIC (Application-Specific Integrated Circuit) design and manufacturing. They are known for providing high-performance and customized ASIC solutions for a variety of applications. Alchip works with clients to design and develop integrated circuits that meet specific requirements and deliver optimal performance for their intended purposes.

The company offers services such as ASIC design services, production services, and IP services. Their expertise lies in creating tailored solutions for clients in industries such as artificial intelligence, data centers, networking, and now they have announced the first Automotive Design ASIC Platform.

Last week Alchip celebrated its 20th Anniversary at the Taipei Marriott with a gala event that thanked and recognized luminaries representing Alchip’s investors and partners for the company’s success. Alchip was founded in 2003 with 23 employees and went public in 2014 on the Taiwan Stock Exchange with an initial capitalization of US$195 million. This year, the company achieved a market cap of approximately US$7 billion and employs nearly 600 people in 13 locations around the globe.

Last month Alchip unveiled the  industry’s first Automotive ASIC Design Platform. This is in lock step with TSMC and their automotive push and as you might know Alchip and TSMC are close partners. Alchip is a TSMC-certified Value Chain Aggregator, and is a founding member of the TSMC 3DFabric Alliance®.

Alchip Automotive ASIC Design Platform

The platform consists of six modules: Design for Autonomous Driving (AD)/ Advanced Driver Assistance System (ADAS), Design for Safety, Design for Test, Design for Reliability, Automotive Chip Sign-off, and Automotive Chip Manufacturing (MFG) Service.

Design for AD/ADAS is the platform’s starting point. Its Ultra-scale design capabilities integrates Central Processing Unit (CPU) and Neural Processing Unit (NPU) into the smallest possible die size, while meeting aggressive higher performance and lower power consumption required by automotive applications.

The Design for Safety module follows the ISO26262 pre-scribed flow that includes required isolated TMR/Lock-Step design methodology. The module also features an experienced safety manager and includes the mandated Development Interface Agreement (DIA) that defines the relationship between the manufacturer and the supplier throughout the entire automotive safety lifecycle and activities.

Design for Reliability includes enhanced Electromigration (EM) as part of silicon lifecycle management. It also covers AEC-Q grade IP sourcing and implementation.

The Automotive Chip Manufacturing Service works with IATF16949 approved manufacturing suppliers. Services include tri-temp testing by target AEC-Q grade, automotive wafer, automotive substrate, assembly and burn-in.

Design for Test capabilities support In System Test (IST) and MBIST/LBIST design, critical and redundancy logic for yield harvest, automotive-level ATPG coverage, and physical-aware ATPG.

The final sign-off module covers an aging library based on a customer mission profile, OD/UD/AVS/DVFS library support, and the final Design for Manufacturing sign-off.

“This is a huge step forward for ADAS and autonomous driving ASIC components and the global automotive electronics industry, said Johnny Shen, CEO of Alchip.” It will speed up the development and time-to-market of essential safety-critical ADAS applications, while significantly advancing the innovation with increasing complex autonomous driving implementation and features.”

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global provider of silicon and design and production services for system companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3DIC design, CoWoS/chiplet design and manufacturing management. Customers include global leaders in AI, HPC/supercomputer, mobile phones, entertainment device, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).

For more information, please visit the Alchip website: http://www.alchip.com

Also Read:

Alchip is Golden, Keeps Breaking Records on Multiple KPIs

Achieving 400W Thermal Envelope for AI Datacenter SoCs

Alchip Technologies Offers 3nm ASIC Design Services

Posted on

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
by Kalar Rajendiran on 12-11-2023 at 6:00 am
Categories: Chiplet, EDA, IP, Synopsys

Pike Creek UCIe Test chip

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details on this later in this writeup. This announcement marked a critical milestone in the journey toward an open and interoperable chiplet ecosystem and highlights the UCIe standard’s commitment to driving the chiplet revolution forward.

Proofpoint of UCIe InterOp

The significance of Intel’s announcement lies in its emphasis on interoperability—the ability of chiplets to communicate seamlessly and effectively, regardless of origin. The announcement marks the public debut of functioning UCIe-enabled silicon, featuring an Intel UCIe IP manufactured on Intel 3 process node and a Synopsys UCIe IP fabricated on the advanced TSMC N3E process node. These two chiplets in the Pike Creek test chip communicate via Intel’s EMIB interconnect bridge, ushering in a new era of heterogeneous chiplet technology.

The Pike Creek test chip serves as a tangible demonstration of UCIe’s capabilities, showcasing how chiplets from different vendors can work together efficiently within a single system. Intel has announced plans to transition from proprietary interface to the UCIe interface on its next-generation Arrow Lake consumer processors. This demonstrates Intel’s commitment to fostering an open, standardized ecosystem for chiplets and aligning with the industry’s shift towards UCIe.

The Backdrop

In recent years, industry leaders such as Intel, AMD, NVIDIA and others have embraced chiplet-based multi-die systems—an innovative approach that involves integrating small, specialized, heterogeneous or homogeneous dies (or chiplets) into a single package. However, the predominant focus has been on of captive systems, where all chiplets within a package are developed by the same vendor. However, this approach limits innovation that arises from incorporating specialized chiplets from different sources.

Heterogeneous integration offers the potential for more versatile and powerful systems by allowing chiplets from various vendors to seamlessly work together in a multi-die system. To fully unlock the potential of chiplet-based multi-die systems, the industry recognizes the imperative of heterogeneous integration. The success of a chiplet-based industry in turn depends heavily on encouraging a broad base of vendors to enter and grow an open chiplet ecosystem. But without a standardized interface for chiplet-to-chiplet communication, integrating chiplets from different vendors becomes complex. Interoperability (InterOp), the seamless communication between chiplets regardless of their origin, stands as a central goal for realizing the full potential of heterogeneous chiplet integration.

Heterogeneous Interoperability is Key

Addressing the heterogeneous interoperability need, the Universal Chiplet Interconnect Express (UCIe) standard was introduced in 2022 through a consortium. With promoter members such as Intel, AMD, TSMC and others and contributor members such as Synopsys, Amkor, Keysight and many others, the consortium is now 120+ members strong. Developed collaboratively by major players in the semiconductor industry, the UCIe standard aims to provide an open-source interface for chiplet interconnects interoperability. By standardizing communication between chiplets, UCIe not only simplifies the integration process but also fosters a broader ecosystem where chiplets from different vendors can seamlessly be incorporated into a single design.

Benefits of UCIe

UCIe consortium members have set ambitious performance and area targets for the technology. By categorizing target markets into two broad ranges with standard 2D packaging techniques and advanced 2.5D techniques, UCIe offers versatility in meeting the diverse needs of chip designers. Advanced 2.5D techniques include technologies such as Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) and TSMC’s Chip-in-Wafer-on-Substrate (CoWoS). Chipmakers can select chiplets from various designers and seamlessly incorporate them into new projects, significantly reducing design and validation work. UCIe allows designers and manufacturers to select chiplets based on their specific requirements, enabling a more flexible and diverse approach to semiconductor design.

In essence, UCIe helps accelerate time-to-market, reduce development costs, promotes innovation, broadens supplier base and enhances overall product development efficiency. Support for 3D packaging is on the roadmap.

Summary

As the semiconductor industry moves forward, the implications of UCIe are profound. The standard not only propels chiplet technology into the era of heterogeneous integration but also opens doors to a new wave of innovation. With a standardized interface in place, chip designers can mix and match chiplets with confidence, creating tailored solutions for a wide range of applications. For example, the potential for heterogeneous chiplets integration opportunities in the automotive market is tremendous. The UCIe consortium recently announced the UCIe 1.1 specification to deliver valuable improvements in the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. Enhancements for automotive usages include predictive failure analysis and health monitoring and enabling lower-cost packaging implementations.

Synopsys

As the leader in EDA and semiconductor IP, Synopsys offers comprehensive solutions to address the ecosystem needs for chiplets integration.

For more details on Synopsys UCIe IP, visit Synopsys UCIe IP Solutions.

Also Read:

Synopsys.ai Ups the AI Ante with Copilot

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability

Synopsys Debuts RISC-V IP Product Families

Posted on

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation
by Mike Gianfagna on 12-10-2023 at 2:00 pm
Categories: Events, Foundries, Intel Foundry
3 Comments

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

For more than 65 years, the IEEE International Electron Devices Meeting (IEDM) has been the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. As I post this, the conference is underway in San Francisco and Intel is presenting a series of first-of-a-kind advances to extend Moore’s Law. The palette of innovations being presented at the conference creates a new path to vertical device scaling, opening the opportunity for a trillion transistors on a package by 2030. This is a story with several parts. Here are the details of how Intel previews new vertical transistor scaling innovation at IEDM.

The Impact

Everyone knows about the incredible exponential scaling delivered by Moore’s Law over the past 50 years or so. We’ve also seen the monolithic effects of Moore’s Law slowing of late. Multi-die design is now adding to the exponential density increases the industry has come to rely on. But that’s not the whole story. It turns out on-chip transistor density scaling is alive and well and is a key contributor to semiconductor industry health.

And Intel, the birthplace of Moore’s Law, is leading the way with innovation that fuels both monolithic and multi-die trends.  In the area of advanced packaging to fuel multi-die design, you can read about Intel’s innovation with glass substrates here. The subject of this post is what Intel is doing to fuel the other trend – monolithic transistor scaling. This is a story of innovation in the Z-axis; how to stack devices on top of each other to deliver more in the same area.

It turns out there are two fundamental barriers to overcome here. First, how to stack CMOS devices to deliver reliable, high-performance characteristics. And second, how to get power to those devices without reducing reliability and performance.  There are a series of presentations at IEDM this week that present several innovations that address these problems. Here are some details…

A Preview of Intel’s Announcements

I was fortunate to attend a pre-IEDM briefing where some of Intel’s advanced researchers previewed what was being presented at IEDM. What follows is a summary of their comments.

Paul Fisher

First to speak was Paul Fisher, Director of Chip Mesoscale Processing Components Research at Intel. Paul began with an introduction to the Components Research Group. He explained this organization is responsible for delivering revolutionary process and packaging technology options that advance Moore’s Law and enable Intel products and services. Some of the research that came from this group and found its way into commercial Intel products includes strained silicon, high-K metal gate, the FinFET transistor, Power Via technology and the RibbonFET. The list is much longer – quite impressive.

Another remarkable characteristic of this organization is the breadth of its worldwide collaboration. Beyond US government agencies, Paul explained the group also collaborates with consortia around the world such as Imec, Leti, Fraunhofer, and others in Asia. The group also directly sponsors university work and mentors other programs through organizations such as the Semiconductor Research Corporation (SRC). The group also works with the semiconductor ecosystem to ensure the equipment and processes needed for new developments are available.

Paul then set the stage for the three briefings that followed. The first discussed innovations in backside power delivery. The second discussed three-dimensional transistor scaling and interconnect. And the third presented advances for on-chip power delivery using Gallium-Nitride (GaN). These three areas are summarized in the top graphic for this post.

Mauro J. Kobrinsky

Next to speak was Mauro J. Kobrinsky, Intel Fellow, Technology Development Director of Novel Interconnect Structures and Architectures. Mauro began by explaining that large, low resistance power routing competes with fine, low capacitance signal routing. The result is a compromise in density and performance. A significant advance that reduces this problem is back-side power delivery. Using this approach, power delivery routing can be done on the backside of the device, freeing critical front-side real estate for more optimal signal routing.

Mauro explained that Intel’s Power Via technology will move to production is 2024 and this will begin to open new options for back-side power delivery. Additional research will also be presented that takes back-side power delivery to a new level. This includes the development of back-side contacts to allow power to be delivered through the backside while signals are delivered through the front-side of the device.

Mauro also discussed critical enhancements for stacked device routing that are underway. Stacked devices present a unique set of challenges for both power and signal routing. In the signal area, new approaches for epi-epi and gate-gate connection must be developed and this is part of the research Mauro discussed.

Marko Radosavljevic

After Mauro, Marko Radosavljevic, Principal Engineer at Intel discussed three-dimensional transistor scaling and interconnect. Essentially what comes after RibbonFET. Marko explained that initial device stacking results were presented by Intel at IEDM in 2021.

What will be presented at IEDM this year is the implementation of a vertically stacked NMOS and PMOS RibbonFET device configuration with Power Via and direct back-side device contacts with a poly pitch of 60nm. The resultant compact inverter exhibits excellent performance characteristics, paving the way for more widespread use of vertical device stacking.

The final speaker was Han Wui, Principal Engineer, Components Research at Intel. Han discussed new approaches to on-chip power delivery. He explained that Intel proposed the first MOS power driver in 2004. This device, often called DrMOS is now used in a wide variety of products.

Han Wui

Han went on to explain that Gallium Nitride, or GaN devices are popular today for high-voltage applications like the 200-volt devices in many laptop charging “bricks”. It turns out GaN exhibits far superior performance at lower voltages (48-volt and below) when compared to CMOS power devices.

At this year’s IEDM, Han explained that Intel will show the first implementation of a process that integrates CMOS devices with GaN power devices on a 300mm wafer.  Dubbed DrGaN, Han explained that this technology will open new levels of performance and density for future designs by integrating CMOS drivers with highly efficient GaN power devices on the same wafer.

To Learn More

You can get a broader view of Intel’s device and process innovation here. And that’s how Intel previews new vertical transistor scaling innovation at IEDM.

Also Read:

Intel Ushers a New Era of Advanced Packaging with Glass Substrates

How Intel, Samsung and TSMC are Changing the World

Intel Enables the Multi-Die Revolution with Packaging Innovation

Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang

Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang
by Daniel Nenni on 12-08-2023 at 10:00 am

Dan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate Marketing groups. He is responsible for strategic business initiatives and partnerships, technical pre-sales activities and post-sales support, and corporate messaging and campaigns. Prior to SiFive, Jack held a variety of senior business development, product management, and product marketing roles at NVIDIA and Marvell with a long track record of successful, large-scale design wins. He also has over 20 U.S. patents from his time as a CPU design engineer.

Dan explores the growth of the RISC-V movement and SiFive’s contributions with Jack. The growth from embedded to end application is discussed, along with the attributes of the RISC-V architecture and ecosystem that are helping this growth. Many aspects of RISC-V are touched on in this far-reaching discussion, from China’s involvement to aerospace applications and ARM’s influence on the overall market.

Jack also discusses SiFive’s contributions and plans as the largest company. focused on RISC-V development.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

CEO Interview: Suresh Sugumar of Mastiska AI

CEO Interview: Suresh Sugumar of Mastiska AI
by Daniel Nenni on 12-08-2023 at 6:00 am
Categories: AI, CEO Interviews, RISC-V

profile image

Suresh is a technology executive with deep technical expertise in semiconductors, artificial intelligence, cybersecurity, internet-of-things, hardware, software, etc. He spent 20 years in the industry, most recently serving as an Executive Director for open-source zero-trust chip development at Technology Innovation Institute, Abu Dhabi, and in other Fortune 500 semiconductor companies such as Intel, Qualcomm, and MediaTek in various leadership roles, where he researched and developed high-performant, energy-efficient, post-quantum secure, safe microchips/ system-on-chips (SoCs)/ accelerators for the Datacenter, Client, Smartphone, Networking, IoT, and AI/ML markets. He holds 15+ US Patents and has published/presented at more than 20+ conferences.

Suresh is also actively serving in a leadership position at RISC-V International where he chairs the Trusted Computing Group to develop RISC-V confidential computing capability and chairs the AI/ML Group to develop RISC-V hardware acceleration for AI/ML workloads such as Transformer Large Language Models used in ChatGPT kind of applications. He also advises startups and venture capital firms on investment decision support, product strategy, technology due diligence, etc.

He earned an MBA from INSEAD, an MS from Birla Institute of Technology & Science Pilani, a Systems Engineering certificate from MIT, an AI certificate from Stanford, and an automotive functional safety certificate from TÜV SÜD.

Tell us about your company
“Mastiṣka AI” (Mastiṣka means Brain in Sanskrit) is an AI company focused on building brain-like computers to run foundation models more efficiently for Generative AI use cases of tomorrow.

What problems are you solving?
Given the benefits of AI/ GenAI, its demand is only bound to go up, and so will its side effects on our planet. How can we reduce or neutralize the side effects of AI on our planet? Carbon capture and nuclear power are in the right direction. But we need to fundamentally rethink the way we do AI, is it the wrong way to do tonnes of matrix multiplications?

Our brain can learn and do many tasks in parallel, in and under 10W, but why do these AI systems consume 10s of megawatts to train models?

Perhaps the future holds energy-efficient architectures such as neuromorphic architectures and spiking neural network-based transformers that are closest to the human brain, which might consume 100-1000x lower energy, hence reducing the cost of using AI, thereby democratizing it and saving our planet.

The current challenges we face with AI namely a) availability, b) accessibility, c) affordability, and d) environmental safety along with some recommendations to tackle them.

If we foresee in the future, some useful AGI concepts are demonstrated in the movie “HER”, where the character ‘Samantha’ – a conversational agent who is natural, understands emotions, shows empathy, is an amazing copilot at work — and runs on handheld devices the entire day, then we may have to address the below challenges right now.

Issue 1: Training an LLM can cost anywhere from 150K to 10+ million dollars, and it allows only those with deeper pockets to develop AI. On top, inferencing costs are huge too (costs 10x more than a web search)
—> We need to improve the energy efficiency of models/ hardware to democratize AI for the benefit of humanity.

Issue 2: Running ginormous AI models for conversational agents or recommendation systems, puts a toll on the environment in terms of electricity consumption and cooling.
—> We need to improve the energy efficiency of models/ hardware to save our planet for our kids.

Issue 3: The human brain is capable and can multitask, but consumes only 10 Watts instead of Megawatts.
—> Perhaps we should build machines like our brains and not the regular matrix multipliers faster.

Humanity can only thrive with sustainable innovations, and not by cutting down all forests and boiling the oceans in the name of innovation. We must protect our planet for the welfare of our children and future generations to come…

What application areas are your strongest?
Training and Inferencing of Transformer (and future neural architecture) based foundation models, at 50-100x more energy efficiently compared to today’s GPU-based solutions.

What keeps your customers up at night?
Issues for customers who currently use other products:

Electricity consumption for training humungous language models is beyond the roof, for example, training a 13B parameter LLM on 390B text tokens on 200 GPUs for 7 days costs $151,744 (Source: HuggingFace new training cluster service page – https://lnkd.in/g6Vc5cz3). And even larger models with 100+B parameters cost $10+M just to train. Then pay for inferencing every time a new prompt request arrives.

Water consumption for cooling, researchers at the University of California, Riverside estimated the environmental impact of ChatGPT-like service, and say it gulps up 500 milliliters of water (close to what’s in a 16-ounce water bottle) every time you ask it a series of between 5 to 50 prompts or questions. The range varies depending on where its servers are located and the season. The estimate includes indirect water usage that the companies don’t measure — such as to cool power plants that supply the data centers with electricity. (Source: https://lnkd.in/gybcxX8C)

Issues for non-customers of current products:

Can’t afford CAPEX to buy hardware
Can’t afford to use cloud services
Can’t innovate or leverage AI — stuck with services model that eliminates any competitive advantage

What does the competitive landscape look like and how do you differentiate?

  • GPUs dominiate training space, even though specialized ASICs also compete in this segment
  • Cloud & Edge inference has too many options available

Digital, Analog, Photonic — you name it people are trying to tackle the same problem.

Can you share your thoughts on the current state of chip architecture for AI/ML, meaning, what do you see as the most significant trends and opportunities right now?

Following trends:
Trend 1: 10 years ago, hardware-enabled deep learning flourished, and now the same hardware is inhibiting progress. Due to the huge cost of hardware and electricity costs to run models, it has become a challenge to access the hardware. Only companies with deep pockets are able to afford these and are becoming monopolies.

Trend 2: Now that these models are there, we need to use them for practical purposes so that the inferencing load will increase, allowing CPUs with AI accelerators to come to the limelight again.

Trend 3: Startups are trying to come up with alternative floating point number representations that the traditional IEEE format – such as logarithmic and posit-based — are good but not enough. PPA$ design space optimization explodes when we try to optimize one and another goes for a toss.

Trend 4: The industry is moving away from the service-based model of AI to hosting its own private models on its own premises — but access to hardware is a challenge due to supply shortages, sanctions, etc

Current state of affairs:
Availability of hardware and data fueled the growth of AI 10 years ago, now the same hardware is sort of inhibiting it — let me explain

Ever since CPUs were doing miserable and GPUs were repurposed to do AI, many things happened

Companies have been addressing 4 segments of AI/ML namely – 1) cloud training, 2) cloud inferencing, 3) edge inferencing, and 4) edge training (federated learning for privacy-sensitive applications).
Digital & Analog

Training side – a plethora of companies doing GPUs, customer accelerators based on RISC-V, wafer-scale chips (850K cores), and so on where traditional CPUs lack (their general purpose). Inference side – NN accelerators are available from every manufacturer, in smartphones, laptops, and other edge devices.

Analog memristor-based architectures also showed up some time ago.

We believe CPUs can be very good at inferencing if we enhance it with acceleration such as matrix extensions

RISC-V side of things:
On the RISC-V side of things, we are developing accelerators for matrix operations and other non-linear operations to eliminate possible bottlenecks for transformer workloads. Von Neumann bottlenecks are also being addressed by architecting memories closer to computing, eventually making CPUs with AI acceleration the right choice for inferencing.

Opportunities:
Unique opportunities exist to fill in the market of foundation models. Example – OpenAI have been mentioning they were not able to secure enough AI compute (GPUs) to continue to push their ChatGPT services… and the news reports about electricity costs of 10x of that of regular internet search and 500ml of water to cool down the systems for every query. There is a market to fill in here — its not niche, but its the entire market that will democratize AI tackling all the challenges mentioned above – a) availability, b) accessibility, c) affordability, and d) environmental safet

What new features/technology are you working on?
We are building brain like computer leveraging neuromodrphic technuques and tailoring models to take advantage of the energy efficient hardware, reusing may of open frameworks available

How do you envision the AI/ML sector growing or changing in the next 12-18 months?
As the demand for GPUs have soured (costing like $30K) plus some parts of the world are facing sanctions to buy these GPUs, some parts of the world are feeling they are frozen in AI research and development without access to GPUs. Alternate hardware platforms are going to capture the market.
Models perhaps will start shrinking — custom models or even fundamentally the information density would grow

Same question but how about the growth and change in the next 3-5 years?
a) CPUs with AI extensions would capture the AI inference market
b) Models would become nimble, and parameters will drop out as information density improves from 16% to 90%
c) Energy efficiency improves, CO2 foot print reduces
d) New architectures come up
e) hardware costs and energy costs go down so the barrier to entry for smaller companies to create and train models becomes affordable
f) people talk about pre-AGI moment, but my benchmark would be the characted Samantha (conversational AI) in movie “her”.. that maybe unlikely given the high cost of scaling up

What are some of the challenges that could impact or limit the growth in AI/ML sector?
a) Access to hardware
b) Energy costs and cooling costs and environmental harm

Also Read:

CEO Interview: David Moore of Pragmatic

CEO Interview: Dr. Meghali Chopra of Sandbox Semiconductor

CEO Interview: Dr. J Provine of Aligned Carbon

Posted on

Analysis and Verification of Single Event Upset Mitigation

Analysis and Verification of Single Event Upset Mitigation
by Jacob Wiltgen on 12-07-2023 at 10:00 am
Categories: EDA, Siemens EDA

Figure 1 Driving trends

The evolution of space-based applications continues to drive innovation across government and private entities. The new demands for advanced capabilities and feature sets have a direct impact on the underlying hardware, driving companies to migrate to smaller geometries to deliver the required performance, area, and power benefits.

Simultaneously, the application space is evolving, and mission parameters for these new applications are causing companies to evaluate non-traditional approaches. Commercial high-reliability processes (i.e., those developed for automotive designs) are being considered for aerospace as they meet both the survivability requirements of certain scenarios and provide reduced development timelines and cost.

Unfortunately, the advantages delivered in lower geometries come at a cost, and one of those drawbacks is that the underlying hardware is more susceptible to soft errors, commonly referred to as single event upsets (SEU). Traditional approaches of redundancy or triplication on salient (if not all) functions within the chip are quickly becoming cost prohibitive.

Fortunately, new flows and automation provide project teams insights into SEU mitigation and offer the ability to optimize the SEU mitigation architecture, also referred to as selective hardening.

Figure 1. Driving trends to selective radiation mitigation

First, let’s review the challenges.

Selective Hardening Challenges

Feedback from the aerospace industry suggests that the traditional approach to SEU mitigation has many pitfalls and leaves two important questions unanswered.

  1. For the design elements known to be mission critical, how effective is the implemented mitigation?
  2. How can I identify the potential of failure due to faults in design elements not protected?

The traditional approach to SEU mitigation is best summarized in a three-step workflow.

  • Step 1: Identify failure points through expert driven analysis
  • Step 2: Design engineers insert the mitigation (HW and/or SW)
  • Step 3: Verify the effectiveness of the mitigation
    • Simulation leveraging functional regressions and force commands to inject SEUs
    • Post-silicon functional testing under heavy ion exposure

Figure 2: The traditional approach to SEU mitigation

Unfortunately, the traditional approach has multiple drawbacks, including:

  • No common measurement (metric) which determines the effectiveness of SEU mitigation.
  • Expert driven analysis is not repeatable or scalable as complexity rises.
  • Manually forcing faults in functional simulation requires substantial engineering effort.
  • An inability to analyze the complete fault state space using functional simulation and force statements.
  • Late cycle identification of failures when testing in a beam environment alongside limited debug visibility when they occur.
Automation and Workflows Supporting Selective Hardening

The overarching objective of selective hardening is to protect design functions which are critical to mission function and save on cost (power and area) by leaving non-critical functions unprotected. Boiling that down a level, the methodology has three aims:

  1. Provide confidence early in the design cycle that the mitigation is optimal.
  2. Provide empirical evidence that what is left unprotected cannot result in abnormal behavior.
  3. Deliver a quantitative assessment detailing the effectiveness of the implemented mitigation.

Siemens has developed a methodology and integrated workflow to deliver a systematic approach in measuring the effectiveness of existing mitigation as well as determining the criticality of unprotected logic. The workflow is broken up into four phases.

Figure 3. The Siemens SEU mitigation workflow

Structural Partitioning: The first step in the flow leverages structural analysis engines to evaluate design functions in combination with the implemented hardware mitigation protecting the function. The output of structural partitioning is a report indicating the effectiveness of the existing hardware mitigation as well as insights into the gaps which exist.

Fault Injection Analysis: Mitigation which could not be verified structurally are candidates for fault injection. In this phase, SEUs are injected, propagated, and the impact evaluated. The output of fault injection analysis is a fault classification report listing which faults were detected by hardware or software mitigation and which faults were not detected.

Propagation Analysis: The SEU sites left unprotected are evaluated structurally under expected workload stimulus to determine per site criticality and its probability to result in functional failure. The output of propagation analysis is a list of currently unprotected faults which were identified to impact functional behavior.

Metrics Computation: Data from structural, injection, and propagation analysis feed the metrics computation engine and visualization cockpit. The cockpit provides visual insights into failure rate, the effectiveness of the mitigation, and any gaps that exist.

Every semiconductor development program has unique characteristics. The methodology described above is flexible and highly configurable, allowing project teams to adjust as needed.

Conclusion

Mitigation of single event upsets continues to challenge even the most veteran project teams, and this challenge is exacerbated as design complexity rises and technology nodes shrink. New methodologies exist to provide quantitative results detailing the effectiveness of SEU mitigation.

For a more detailed view of the Siemens SEU methodology and the challenges it will help you overcome, please refer to the white paper, Selective radiation mitigation for integrated circuits, which can also be accessed at Verification Academy: Selective Radiation Mitigation.

Jacob Wiltgen is the Functional Safety Solutions Manager for Siemens EDA. Jacob is responsible for defining and aligning functional safety technologies across the portfolio of IC Verification Solutions. He holds a Bachelor of Science degree in Electrical and Computer Engineering from the University of Colorado Boulder. Prior to Mentor, Jacob has held various design, verification, and leadership roles performing IC and SoC development at Xilinx, Micron, and Broadcom.

Also Read:

Siemens Digital Industries Software Collaborates with AWS and Arm To Deliver an Automotive Digital Twin

Handling metastability during Clock Domain Crossing (CDC)

Uniquely Understanding Challenges of Chip Design and Verification

Posted on

5G Aim at LEO Satellites Will Stimulate Growth and Competition

5G Aim at LEO Satellites Will Stimulate Growth and Competition
by Bernard Murphy on 12-07-2023 at 6:00 am
Categories: 5G, Ceva, IP

satellite min

Low earth orbit (LEO) satellites as an intermediary for communication became hot when Elon Musk announced Starlink (yeah, other options were available, but Elon Musk). This capability extends internet availability to remote areas and notably (for a while) to Ukraine in support of the war with Russia. Satellites can in principle provide line-of sight access anywhere, especially in areas lacking base stations (low population, mountainous, remote rural, etc). They even help in high latitude areas where access to geostationary satellites can be hampered by low-angle availability. 3GPP, the group of committees responsible for mobile communications standards, are now working on extending 5G to allow for communication through satellites, especially LEO and MEO (medium earth orbit) satellites. Thanks Elon, but we need competition to drive cost down and availability and service options up. The opportunity is significant, as are the challenges since this option isn’t just a simple extension to 5G.

Opportunity

While 75% or more of the US population lives in urban areas, only 55% of the worldwide population is urban. Nearly half the world likely does not live near a cellular base station, significantly limiting access to the internet and ability to make mobile phone calls. Even within the US or other western countries, our food production, cross-country shipping and at least 25% of the population have restricted access to those services. As any city dweller on a road trip quickly realizes.

In addition to Starlink, Amazon through their Kuiper project and T-mobile have active programs to support satellite-based communication. Market analysts estimate nearly a $30B market by 2030, with a CAGR of nearly 30%. That’s very tempting growth for operators, for infrastructure equipment makers and for handset makers if protocols can be standardized to drive growth and lower cost. Getting there will require not only extensions to 5G but also new hardware and software, as we’ll see next.

Challenges

Connecting through a satellite isn’t an incremental extension to terrestrial options. One problem is latency. Not simple there-and-back latency which for a LEO satellite runs maybe a few tens of milliseconds, not much worse than a ground-based cable link. One issue is handovers. LEO satellites orbit much closer to earth than say a geostationary satellite, which makes the coverage area much smaller for any given satellite at any given time. To maintain those orbits, LEO satellites must travel at high speed, requiring links be handed over quite frequently between satellites to maintain coverage with a ground-based device. Managing these handovers adds to latency.

Another challenge arises in managing Doppler shift in the link signal. LEO satellites travel at around 8km per second, fast enough to alter link frequencies noticeably and variably during the lifetime of a link to any given satellite. This problem isn’t a concern for terrestrial base stations traveling at 0km per second 😊

A third challenge is that the standard is not yet finalized. The 3GPP plan is aiming at support for up to tens to hundreds of Mbps bandwidth in the downlink and roundtrip delays down to a few tens of milliseconds. Those goals will require innovation in software for efficient handover management and in modems to manage the Doppler problem.

Who are you going to call?

The standard isn’t released, and production wireless solutions aren’t yet available, but that doesn’t mean you can’t start planning. This will be a competitive market demanding aggressive pricing for user equipment and for infrastructure. As usual, all components in the network must be very low power and these systems must remain compliant with baseline expectations for 5G and Open RAN. The days of dedicated phones for satellite access and proprietary solutions for large chunks of the network are far behind us.

Which makes CEVA an interesting company to talk to when planning your LEO satellite strategy. These guys have a track record for releasing solutions shortly after a standard is ratified. They already have well-proven cellular (and other wireless) IP solutions up to and including 5G, targeted to all aspects of mobile networks and UEs. Take a look at their Open RAN platform, and their  5G Modems platform for more details.