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Intel’s finfets too complex and difficult?

Intel’s finfets too complex and difficult?
by Tom Dillinger on 07-07-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC
1 Comment

Thanks to SemiWiki readers for the feedback and comments on the previous “Introduction to FinFET Technology” posts – very much appreciated! The next installment on FinFET modeling will be uploaded soon.

In the interim, Dan forwarded the following link to me “ Intel’s FinFETs too complicated and difficult, says Asenov“, which provides some (preliminary) analysis on FinFET behavior, from recently published TEM pictures of Intel’s Ivy Bridge designs:
Continue reading “Intel’s finfets too complex and difficult?”

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TSMC: Production Proven Design Services Driving SoC Innovation!

TSMC: Production Proven Design Services Driving SoC Innovation!
by Daniel Nenni on 07-06-2012 at 8:30 pm
Categories: Uncategorized

One of the truisms of today’s disaggregated semiconductor design and manufacturing model is counter-intuitive to the do-it-yourself focus that is at the heart of every engineer. And yet, time and time again, success rewards those who understand that with today’s ever increasing complexity, it is difficult, if not impossible, to be all semiconductor things to all people.

This lesson was reinforced during a presentation at DAC 2012 from Global Unichip that focused on the services bundled into their Flexible ASIC Model[SUP]TM[/SUP] that allows semiconductor designers to focus on their core competency. What impresses me about their approach, is that GUC doesn’t insist on a hard-and-fast hand off point, but rather provides the flexibility for each company to determine where their core competency begins and ends.

GUC’s business today is being driven by high gate count, advanced technology, and low power SoC designs. Low Power is definitely key to much of today’s innovation. GUC’s low power design services start with defining specific low power library and power gating techniques. It also encompasses DVFS and AVFS services along with low power verification. But the heart of their design services lies in their low power competency, their domain IP integration and their highly sophisticated design for test (DFT).

The GUC Low Power Competency goes under the brand name PowerMagic® and covers IP that provide both internal and external power shutdown that has been proven on more than 80 designs over the past five years. Dynamic power is a big concern for low power, high performance designs. Working through different methodologies GUC has mastered the ability to efficiently perform clock gating at the architecture level. They are also experts at designing for multiple supply voltages on a single chip and dynamic voltage frequency scaling. The key to their success is the ability to design-in changes to the supply voltage and frequency based on the current processor loading.

Another design variable that drives both design quality and time-to-market success is the ability to integrate high speed interface IP into low power designs at both the chip and system level. To that end, GUC began developing and designing its own high speed interface IP, including SerDes, PCI Express 3.0, USB 3.0, DDR2/3, LPDDR2/3 and a number of others starting at 65nm. Today, that high speed interface IP portfolio covers production nodes down to 28nm and continues to shrink to 20nm. Another GUC service is customizing IP for each application to meet required specification. To achieve comprehensive domain IP integration, package influences also need to be taken into consideration.

In parallel, GUC extends its high speed design capabilities through its Design for Test (DFT) services. The key objective is to improve yield by reducing peak power during testing so as to cut down the cost of testing.

While there is much more to the GUC low-power methodology than I can blog here, the point is that low power at high performance is a difficult design challenge, one that vexes many designers and requires a new found expertise. The bottom line is that it might be worth checking out silicon proven low power designs specialists the next time you face that specific challenge.


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Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance

Mind the Gap — Overcoming the processor-memory performance gap to unlock SoC performance
by Sundar Iyer on 07-06-2012 at 3:25 pm
Categories: IP

Remember the processor-memory gap— a situation where the processor is forced to stall while waiting for a memory operation to complete? This was largely a result of the high latency required for off chip memory accesses. Haven’t we solved that problem now with SoCs? SoCs are typically architected with their processors primarily accessing embedded memory, and accessing external memory only when absolutely necessary. However, while on-chip memory access latency is still a concern, embedded memories are also required to respond to back‐to‐back sustained access requests issued by a processor or processors. In fact, networking data pipelines and multicore processors can hammer memory with a multitude of simultaneous memory accesses to unique random addresses, and the total number of aggregated memory accesses has been dramatically increasing. So once again, system architects are up against a processor-memory gap, this time with embedded memory. And as a result, embedded memory performance has become the limiting factor in many applications (figure 1).

At Memoir Systems, we believe that the performance limitations of embedded memories are largely a result of the way that the problem has been conceptualized. In fact, we have found it is possible to improve memory performance by a factor of ten using currently available technology and standard processes. In the past, thinking about embedded memories was limited to a purely circuit- and process-oriented approach. Thus, the focus was on maximizing the number of transistors on a chip and cranking up the clock speed. This was successful up to a point, but as transistors approach atomic dimension, as an industry, we ran into fundamental physical barriers.

At Memoir we have taken an entirely new approach with ourAlgorithmic Memory technology. Algorithmic Memories operate by adding logic to existing embedded memory macros. Within the memories, algorithms intelligently read, write, and manage data in parallel using a variety of techniques such as buffering, virtualization, pipelining, and data encoding. These techniques are woven together to create a new memory that internally processes memory operations an order of magnitude faster and with guaranteed performance. This increased performance capability is made available to the system through additional memory ports such that many more memory access requests can be processed in parallel within a single clock cycle as shown in figure 2. The concept of using multi-port memories as a means of multiplying memory performance mirrors the trend of using multicore processors to increase performance over uniprocessors. In both cases, it is the parallel architecture rather than faster clock speeds that drive performance gains.

Algorithmic Memory technology is implemented as a soft RTL. The resulting solutions appear exactly as standard multi-port embedded memories. The new memories employ dozens of techniques to accelerate performance or reduce area and power requirements. However, perhaps the greatest benefits of Algorithmic Memory come not from the individual algorithms, but rather in how they are integrated into an elegant system (figure 3). In this system, the memories not only perform better, but their performance is fully deterministic. Furthermore, not only can new memories be created very rapidly, but they are also automatically exhaustively formally verified and, since they are built on existing embedded memories, no additional silicon validation is required.

Algorithmic Memory gives memory architects a powerful tool to rapidly and reliably create the exact memories they need for a given application. Most importantly, though, it empowers system architects with new techniques to overcome the processor-memory gap, and further unlock SoC performance.

Dr. Sundar Iyer
Co-Founder & CTO

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Cadence at Semicon West Next Week: 2.5D and 3D

Cadence at Semicon West Next Week: 2.5D and 3D
by Paul McLellan on 07-05-2012 at 5:32 pm
Categories: Cadence, EDA

Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:

  • 1.10pm to 1.25pm: Dr John Xie of Altera on Interposer integration through chip on wafer on substrate (CoWoS) process.
  • 1.25pm to 1.40pm: Ryusuku Otah of Fujitsu on Large SIP for computer and networking application with 2.5D, 3D structure.
  • 1.40pm to 1.55pm: Dr Huili Fu of HiSilicon Technologies on The demands and the challenges of TSV technology application in IC and system.

Then from 2.20pm to 3.30pm there is a panel session on Ecosystem and R&D collaboration. Cadence will be represented by Samta Bansal, who I talked to about Cadence’s joint work with TSMC that they announced at DAC.


As I’ve said before, I think that 2.5D (and eventually 3D) are going to be very important since it is not clear that we will be able to continue to keep on track with lithographic scaling. With double and triple patterning we can manufacture but it is very expensive and wafer prices are going up fast. EUV still looks a long way from possible commercialization and it may never get there. In the meantime, high levels of integration can be achieved with CoWoS along with the advantage of being able to mix die from different processes. We are at the early stages of this and there is still lots of work to be done, both on the EDA side but more so on the ecosystem and supply chain (who does what? when do you test? how do you ship ultra-thin silicon around without breaking it? etc). Since this is the topic of the panel session, it should be interesting to hear.

The session is free to attend if you are registered for Semicon.

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Minitel Shuts Down

Minitel Shuts Down
by Paul McLellan on 07-05-2012 at 5:02 pm
Categories: General

When I first came to the US, one project that we had going on at VLSI Technology was an ASIC design being done by a French company called Telic. The chip would go into something called “Minitel” which the France Telecom (actually still the PTT since post and telecomunications had not yet been separated) planned to supply to most customers in the country. One function of Minitel was to allow you to look up phone numbers and the system was paid for by the fact that France Telecom would no longer need to print white-pages phone directories and distribute them.

But that wasn’t the only use. Lots of what today we would call websites came into existence allowing catalog shopping, chat-rooms, booking travel and, yes, porn (minitel rose). It was a big success. Remember this is in the early to mid 1980s, long before the Internet escaped from its roots in academia and the military. Since nobody really yet had computers at home, Minitel included a keyboard and screen. It connected over the phone lines using modem technology (at 1200 bits/second download and 75 bits/second upload).

I didn’t know it at the time, but I would end up moving to France and living there for over 5 years, and so ended up making extensive use of Minitel. The service had several tiers. You would dial 3611 for a searchable phone directory which was free. Other numbers would have nominal per-minute charge for things like catalog shopping (where the site itself wasn’t really the main business) and premium numbers for things like chat-rooms (where using the site was the business).

Of course, in the end, this turned out to be a dead end as general purpose computers became widespread, the Internet became commercial and, eventually, we all have broadband. There has been a lot of debate about whether Minitel helped or hindered Internet penetration in France. Since there were so many primitive terminals in use, people didn’t need to buy a computer and they could still have many of the benefits of the Internet. But eventually as people had computers anyway, and as data speeds went to 56 kbit/second modems and then broadband, it was increasingly obsolete. Last week, France Telecom finally retired the service on June 30th.

Being first is sometimes a hindrance compared to waiting. The London Underground is primitive compared to many subway systems (especially new ones in Asia) because it was partially built in the 1860s before people could tunnel through hard rock effectively, so it is unnecessarily windy, and the tube diameter is comparatively small (so small that there is no room for air-conditioning on the trains).

EDA startup companies often try and commercialize some technology before the market really requires it, and this typically means that the company runs out of money or considerably dilutes all the founders. Often it is a different company that finally finds success in the market.

With the success of the Mac it is easy to forget that Apple’s first attempt to build a GUI-based computer was Lisa, which was a failure (not to mention Xerox’s own attempt, the Star, even earlier and more expensive).

So being first isn’t always best. It’s the second mouse that gets the cheese.

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IC Design at Novocell Semiconductor

IC Design at Novocell Semiconductor
by Daniel Payne on 07-05-2012 at 12:09 pm
Categories: EDA, IP, Tanner EDA
5 Comments

In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday. Continue reading “IC Design at Novocell Semiconductor”

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Managing Differences with Schematic-Based IC Design

Managing Differences with Schematic-Based IC Design
by Daniel Payne on 07-02-2012 at 2:41 pm
Categories: Cliosoft, EDA
3 Comments

At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.

The Challenge
Hand-crafted chip designs provide the highest performance and give the designer greatest control over silicon IP area and specs, however when you are part of a team of designers there is a need to communicate with other team members on what has changed on your schematic since the last version.

Approaches for Text Diff
When I started doing DRAM circuit design in the 1970’s we used colored highlighters during the compare of schematics versus the netlist. Word processors like the Microsoft Office suite added text comparison features so that as you worked on a document a history of what just changed could be seen.

Unix users have the difficulty, even my MacBook Pro today has diff on it for the occasional times that I use the terminal and need to compare text files.

In EDA you can even use an LVS (Layout Versus Schematic) tool like Calibre to compare two versions of a schematic or layout netlist and get some idea of what has changed.

Approaches for Graphic Diff
With a schematic-based design you need a visual way to markup your schematics or IC layout to see what has changed since the last rev. You could try several approaches for tracking schematic or layout changes:

  • Netlist your schematics into EDIF or SPICE files
  • On IC Layout do an XOR of the GDS versions

The netlist approach works only on Text, so you cannot really see what changed which is more intuitive.

The XOR approach shows you visually what changed on the layout, but not the difference on a schematic level which is more intuitive to a circuit designer.

The Visual Design Diff Approach
ClioSoft has created a visual diff tool that works in a Cadence Virtuoso design flow to quickly highlight what has changed on your schematic since the last rev.

You just click a new menu choice in Virtuoso under Design Manager to see changes to:

  • Nets
  • Instances
  • Layers
  • Labels
  • Properties

This new class of EDA tool can be used by both the circuit designer or the layout designer in determining what has changed between versions of either a schematic or layout. This kind of automation will eliminate hours and even days worth of manual work compared to the old way of managing changes manually.

In June 2011 ClioSoft added support for hierarchy in the visual diff tool, so now you can traverse all the levels of hierarchy of your designs and see the differences.

Also Read

ClioSoft Update 2012!

Hardware Configuration Management at DAC 2012

IC Layout Design at Qualcomm

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IC Test Sessions at SEMICON West 2012

IC Test Sessions at SEMICON West 2012
by Beth Martin on 07-02-2012 at 1:43 pm
Categories: EDA, Siemens EDA
1 Comment

SEMICON West is coming up this July 10-12 at the Moscone Center in San Francisco. It covers a broad swath of the microelectronics supply chain, but I was particularly interested in the test sessions. Here are two that I recommend.

“The Value of Test for Semiconductor Yield Learning” on Tuesday, July 10, at 1:30p. The focus of this presentation by Geir Eide, the manager of yield learning products at Mentor Graphicsis, is on using software-based diagnosis of test failures to find the defect type and location of failures “based on the design description, scan test patterns, and tester fail data.” Advanced techniques like the “diagnosis-driven yield analysis” he describes are becoming necessary with the emergence of design-sensitive defects. He’ll cover two of my favorite things: DFM-aware yield analysis, and machine learning techniques that allow for keen statistical analysis of diagnosis data. As a side note, if you are interested in test and yield issues, Semiwiki has a new forum on the topic.

On Wednesday, we get the greatest hits of the most recent International Test Conference ITC). It starts with Friedrich Hapke, the director of engineering for silicon test at Mentor Graphics in Germany reprising a popular ITC paper, “Cell-aware Analysis for Small-delay Effects and Production Test Results from Different Fault Models.” He describes how to find defects inside of standard cells. This “cell-aware” testing greatly improves overall defect coverage. He will show industrial results (from AMD) on 45nm and 32nm designs to support that claim.

Cell-aware testing uses user defined fault models (UDFM), and you can learn about that
from this Mentor whitepaper, User Defined Fault Models.

After taking in all the interesting test and yield analysis sessions, be sure to mosey over to the show floor for happy hour refreshments, and to tell me what you found most interesting. Happy hour is Wednesday at 3:30. Don’t forget to register for SEMICON West.

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Cadence’s NVM Express: fruit from subsystem IP based strategy

Cadence’s NVM Express: fruit from subsystem IP based strategy
by Eric Esteve on 07-02-2012 at 11:24 am
Categories: Cadence, IP

If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application Processor. Are we naïve if we think the next step should be subsystem IP? It would really make sense to use an IP aggregation, organized in such a way that it could support a specific application!

The list of benefits is long: at first, it will certainly speed up the design integration phase, thus offering a better Time-To-Market. Above mentioned SoC, designed on 28nm technology requires an investment in the $40M to $80M, and they have to hit the market on line with the end user expectations (better Video quality, lower power consumption offering longer time between batteries charging, higher data throughput allowing faster data download, and so on). Being able to deliver the right SoC just in time will allow to sell at the right price, offering enough gross profit margins (GPM), so the chip maker can satisfy investors and continue to invest and gain market share. Missing the market window could put the product line, if not the overall company, at risk.

A subsystem IP based approach will also speed up the software development and validation phase: if the IP provider is able to propose the right tools, like the associated Verification IP (VIP), the software development tools tightly coupled with the subsystem description model, as well as proper emulation and prototyping support, the (S/W & H/W) development team can simply go faster. Good for the TTM, allowing hitting the market window, good again for the GPM!


The Cadence Design IP for NVM Express is the industry’s first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market, and, to my opinion, an important step on the above mentioned SoC evolution, as this solution includes:

  • PCIe 8GT/s PHY IP
  • NVMe and PCIe Controller IP combine (reducing engineering effort while optimizing overall solution)
  • Firmware accelerates the HW/SW integration effort
  • Capabilities from VIP, UVM and IP products along with,
  • Fast prototyping and virtualized software products to simplify the design process

Cadence has not chosen NVM Express by chance, in fact the Denali acquisition has bring to Cadence IP port-folio both the PCIe Controller IP product and the Nand Flash Controller (Non Volatile Memory = NVM) IP product, complemented with a PHY IP coming from internal source.

The move from HDD to SSD is good news for end users (including myself, I definitely vote for HDD replacement by SSD!) and the move from SATA interface to PCI Express is also good news: PCI Express offers much more features than SATA (Virtualization, High Outstanding request count, to name a very few of them), and also offers scalability, that SATA does not, and configurability, which is good for a subsystem IP, as Cadence potential customers will need to differentiate each other’s. I may come back in a later blog and talk about the –potential- drawbacks with subsystem IP, but I am intimately convinced that the benefits coming from this type of IP solution are higher, and that the SoC evolution will go on.

Eric Estevefrom IPNEST–