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A Brief History of ClioSoft

A Brief History of ClioSoft
by Daniel Payne on 02-03-2013 at 8:05 pm

In the 1990s, software developers were established users of software configuration management (SCM) tools such as open source RCS/CVS or of commercial systems such as Clearcase. Hardware designers, however, managed design data in ad hoc home-grown ways. ClioSoft’s founder, Srinath Anantharaman, recognized that hardware development could benefit from some of the same techniques and methods as software development., Hardware design flows had some unique requirements not met by SCM tools and hardware designers were not as comfortable with Unix command line tools. Anantharaman wanted to fill this gap by creating a hardware configuration management (HCM) system that would help streamline hardware design teams just as SCM tools had done for software teams.

ClioSoft was launched in 1997, as a self-funded company, with the SOS (Save Our Software) design collaboration platform as its first product to help manage front end RTL flows. With the commercial deployment of the tool, ClioSoft soon realized that the greater need was to manage design data from analog/mixed-signal designs where Cadence Virtuoso® was the dominant flow. Designs were created using graphical tools like schematic or layout editors that produced large collections of binary files. Designers worked at the abstraction levels of libraries, cells, and views and were not familiar with the physical files created by the design tools. It would have been really difficult to use a file-based management method to manage Cadence Virtuoso data. ClioSoft joined the Cadence Connections™ program in 1998 and proceeded to work closely with Cadence to solve this problem. The result was a new product, SOS viaDFII, that seamlessly integrated the version control and design management features of SOS with the Cadence Virtuoso flow, allowing users of the Cadence Library Manager to manage revisions of schematics and layouts without worrying about the physical files.

Over time, the exponential increase in design complexity and shrinking market windows led to larger design teams. With increased globalization, design teams started getting distributed, recruiting the best talent wherever it was available. These dual forces increased the need for design management and efficient collaboration. To meet the new challenges, ClioSoft introduced the cache server in 2002. A cache server could be run at the remote sites to automatically cache the latest file revisions and serve these files to the users at the remote sites without having to get the data from the primary site. This made working at remote sites almost as efficient as working at the primary site and gave every engineer real time access to changes to design data without the requirement for a very high bandwidth connection.

As design team and design sizes grew, additional burdens were put on the already-stretched IT resources and staff at customer sites. File servers would run out of disk space and backups would never end. ClioSoft realized that much of the design data was being duplicated, since each engineer had entire copies of the design libraries in his or her workspace even though only a small portion of the design was being modified. Clearly there should be a way to avoid this duplication without taking away control of the workspace from the designer. ClioSoft solved this problem by introducing the capability to create workspaces with symbolic links into the cached revisions that already existed in the cache. Workspaces were now a lot smaller because most of the files were symbolic links to a file in the cache except for the few files the user was editing. ClioSoft cache server was now able to track how many users were using each revision of each file. It kept all revisions being used and automatically purged all unused revisions. The smart cache allowed optimum use of disk while still giving each user complete isolation and control of his or her workspace. This was widely adopted by design teams and now over 90% of design teams using SOS in the Virtuoso flow use workspaces with links to cache. This feature was a clear differentiator for ClioSoft as SCM systems created to manage relatively small text files did not support such optimization.

With software or digital front end design, engineers typically create design files using a text editor. So they are well aware of files created and which files should be checked in to the data management (DM) system. This is not the case with analog and custom designs where engineers use graphical tools like schematic or layout editors that produce collections of files for each design unit (such as Open Access cell-views) – some of which should be managed together as a co-managed set and others that should not be managed at all. This is a crucial difference between hardware and software design data and ClioSoft handles this by managing co-managed files as a composite object that gets checked in as a single object. This preserves the integrity of the design data in each revision and clearly identifies and versions the design units as a whole and not as multiple individual files.

With the continued commercial success of ClioSoft’s HCM offering, there was a demand to support other flows from customers and other EDA vendors. Mentor approached ClioSoft in 2004 to provide DM for their ICstudio flow and a joint development effort resulted in SOS viaICstudio to provide integrated HCM for Mentor’s ICstudio. Having a data management solution had now become a de facto standard requirement for design teams. Customers requested that ClioSoft support a variety of different tools, including tools developed in-house. One of the big challenges in managing data from different tools is to understand and manage the right set of co-managed files while keeping it simple for the user. To solve this problem, ClioSoft introduced a rule-based technology called the Universal DM Adaptor. A CAD administrator can specify pattern-based rules that SOS uses to automatically package co-managed files into a composite object and exclude files that should not be managed. ClioSoft was awarded a US patent for this technology in 2010. Using this powerful and flexible technology, with encouragement from customers and active cooperation from major EDA vendors, ClioSoft soon had developed custom DM interfaces for SpringSoft’s Laker™ and Synopsys’ Custom Designer. ClioSoft now had a seamlessly integrated HCM solution for all the major analog and mixed-signal flows in the market.

As design teams got better at managing the design data, they wanted to reuse their IP from one design in other designs and derivatives. In 2008, ClioSoft introduced the Enterprise Edition that allows design teams to reference and reuse designs or IP blocks from different projects. The ability to assign custom attributes to design objects and the available SOS web browser interface provided easy intranet access to find and reuse IP blocks from across the enterprise.

A question that is asked very often during design is: “What changed?” It can be asked for many reasons – to review before committing changes, to pinpoint regression failures, to identify the design changes made for an ECO and for design reviews, especially before tape-out. Revision logs maintained by engineers are often of little or no help. Expanding beyond data management, ClioSoft launched the Visual Design Diff (VDD) tool at DAC 2010 to answer this very important question. VDD was able to quickly identify and highlight changes between different versions of schematics or layouts even down the entire design hierarchy. The ease of use and the obvious ROI of VDD led to immediate commercial success even in companies using other DM systems.

ClioSoft’s customer base has grown steadily to allow the company to remain self-funded. Over 120 organizations trust ClioSoft SOS HCM to manage their design data. That customer trust has translated into similar confidence in ClioSoft among the major EDA vendors.

In September 2012, Cadence published the book Mixed Signal Methodology Guide, which assembles the collective wisdom of 13 experts from companies such as Boeing, Cadence, and Qualcomm and includes a chapter on data management for mixed-signal designs written by ClioSoft.

Mentor chose ClioSoft as the only commercial vendor to provide DM for their Pyxis™ Custom IC Design Platform design flow released in 2012. Similarly, Agilent chose ClioSoft as their DM vendor of choice for the Agilent Advanced Design System (ADS) design flow released in 2013.

Also Read

Using IC Data Management Tools and Migrating Vendors

Mixed-Signal Methodology Guide: Design Management

AMS IC Design at Rohde & Schwarz


SemiWiki Hits Major Readership Milestone!

SemiWiki Hits Major Readership Milestone!
by Daniel Nenni on 02-03-2013 at 7:00 pm


For those of you who follow SemiWiki and the fabless semiconductor ecosystem it has been a very interesting two years:

The Semiconductor Wiki Project, the premier semiconductor collaboration site, is a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem. Since going online January 1st, 2011 more than 500,000 unique visitors have been recorded at www.SemiWiki.com viewing more than 3.5M pages of blogs, wikis, and forum posts. WOW!


The month of January 2011

Unique Visitors: 5,756

The month ofJanuary 2012
Unique Visitors: 28,263

The month ofJanuary 2013
Unique Visitors: 55,372

Total Posts on SemiWiki: 7,217

According to LinkedIn, there are 496,815 LinkedIn members in the semiconductor industry. As of January 31[SUP]st[/SUP], 2013, SemiWiki.com has recorded 504,852unique visits which is an amazing feat if you really think about it. You also have to understand that the SemiWiki bloggers, myself included, all have day jobs inside the semiconductor ecosystem. Click over to our LinkedIn profiles and you will find that we have very diverse and very deep semiconductor experiences that we are happy to share with SemiWiki visitors.

Since Paul McLellan is the most famous amongst us let’s start with him:

Dr. Paul McLellanhas a 30 year background in semiconductor and EDA with both deep technical knowledge and extensive business experience. He works as a consultant in EDA, embedded systems and semiconductor. Paul was educated in Britain and spent the early part of his career as a software engineer at VLSI Technology both in California and France, eventually becoming CEO of Compass Design Automation. Since then he was VP of engineering at Ambit, corporate VP at Cadence, VPs of marketing at VaST Systems Technology and Virtutech, and CEO at Envis Corporation. He blogs at dac.com and at semiwiki.com and has published a book EDAgrafittion the EDA and semiconductor industries.

Dr. Eric Esteve has over 25 years of experience in the Semiconductor industry focused on ASIC and IP. He is the founder of IPnest, a company providing strategic consulting and IP related Market Surveys to high level customers: IP vendors, ASIC Design Service, Silicon Foundries and IDM/Fabless. Eric started his career as an ASIC designer, working for various companies in France, including VLSI Tech., TI and Atmel. Eric holds a PhD in Microelectronics from the University of PARIS Descartes.

Daniel Paynestarted out at Intel designing DRAM chips in 1978, then transitioned into EDA companies in 1986 with roles in applications, marketing and management. Freelance since 2004, Daniel offers EDA consulting services and is a founding blogger at SemiWiki.

Don DingeeStarted his professional journey at Cal Poly Pomona where he obtained a BSEE emphasizing in analog signal interfacing, and continued to the University of Southern California obtaining an MSEE in digital communication theory, including a radar design course with Irving Reed – as in “Reed-Solomon encoding”. After a stint as an test and design engineering at General Dynamics, he moved onto the marketing path as a sales contributor and marketing manager for Motorola, a consultant for Embedify, and an editor at OpenSystems Media. Currently, he is the voice behind Left2MyOwnDevices (his former magazine column), writing and consulting on embedded, mobile, and social tech.

Daniel Nenni
has worked in Silicon Valley since 1984 with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. Currently Daniel is a Strategic Foundry Relationship expert for companies wishing to partner with TSMC, UMC, SMIC, Global Foundries, and their top customers. Daniel is the founder of the Semiconductor Wiki Project (www.semiwiki.com).

What’s next? SemiWiki.com will continue to publish the latest blogs, wikis, and forum discussions revolving around semiconductors and the devices they enable. This is crowd sourcing so any registered member can participate providing a real-time feedback loop for the greater good of the semiconductor ecosystem.

SemiWiki will also publish books starting with “A Brief History of the Fabless Semiconductor Industry” co-authored by Paul McLellan and myself with more to follow. “Brief History of” blogs, building blocks of the book, can be found HERE.

Everybody at SemiWiki would like to thank the crowd of people that read our site, especially our registered members and participating companies, we could not have done it without you!


Common Platform Technology Forum February 5th 2013 Live or Online!

Common Platform Technology Forum February 5th 2013 Live or Online!
by Daniel Nenni on 02-03-2013 at 8:00 am

Can’t make it to Santa Clara? Join us online!

The detailed 2013 CPTF agenda is now up in preparation for the February 5th event at the Santa Clara Convention Center. This is one of the rare times that you can get a free lunch! Watch this quick video to see what is in store for us this year. Dr. Paul McLellan and I will be there so please introduce yourself, it would be a pleasure to meet people who follow us on SemiWiki. Space is limited so register today HEREor click on the banner below. Did I mention it is FREE? This is an excellent opportunity to mingle inside the fabless semiconductor ecosystem.

Agenda

[TABLE]
|-
| valign=”top” |
| valign=”top” | 8:00am – 9:00am
| valign=”top” |
| valign=”top” | Registration & Continental Breakfast
|-
| valign=”top” |
| valign=”top” |
| valign=”top” |
| valign=”top” | KEYNOTE SESSION
|-
| valign=”top” |
| valign=”top” | 9:00am – 9:20am
| valign=”top” |
| valign=”top” | Welcome & Introduction
Emcees:

  • Bruce Kleinman, Vice President, Product Marketing, GLOBALFOUNDRIES
  • Mike Cadigan, General Manager, IBM Microelectronics, Systems and Technology Group

|-
| valign=”top” |
| valign=”top” | 9:20am – 10:00am
| valign=”top” |
| valign=”top” | Innovations for Next Generation Scaling
Dr. Gary Patton, Vice President of Semiconductor Research & Development Center, IBM
|-
| valign=”top” |
| valign=”top” | 10:00am – 10:30am
| valign=”top” |
| valign=”top” | Common Technology Platform, Uncommon Solutions
Mike Noonen, Executive Vice President, Global Sales, Marketing, Quality and Design, GLOBALFOUNDRIES
|-
| valign=”top” |
| valign=”top” | 10:30am – 11:00am
| valign=”top” |
| valign=”top” | Technology Pioneer, Beyond HKMG Technology
Dr. KH Kim, Executive Vice President, Foundry Business, Samsung
|-
| valign=”top” |
| valign=”top” | 11:00am – 11:30am
| valign=”top” |
| valign=”top” | Partnering for Innovation to Drive Diversity
Dr. Dipesh Patel, Executive Vice President and General Manager, Physical IP Division, ARM
|-
| valign=”top” |
| valign=”top” | 11:30am – 6:00pm
| valign=”top” |
| valign=”top” | EXHIBITS OPEN IN PARTNER PAVILION
|-
| valign=”top” |
| valign=”top” | 11:30am – 1:00pm
| valign=”top” |
| valign=”top” | Lunch
|-
| valign=”top” |
| valign=”top” |
| valign=”top” |
| valign=”top” | TECHNICAL SESSIONS
|-
| valign=”top” |
| valign=”top” | 1:00pm – 1:30pm
| valign=”top” |
| valign=”top” | Fireside Chat

  • Handel Jones, Owner and CEO, International Business Strategies, Inc.
  • Brian Fuller, Journalist, EE Times

|-
| valign=”top” |
| valign=”top” | 1:30pm – 2:30pm
| valign=”top” |
| valign=”top” | Advances in 14nm FinFET Process & Manufacturing

  • Dr. Shawn Han, Vice President, Foundry Marketing, Samsung
  • Dr. Antun Domic, Senior Vice President and General Manager, Implementation Group, Synopsys

|-
| valign=”top” |
| valign=”top” | 2:30pm – 2:50pm
| valign=”top” |
| valign=”top” | Break w/Refreshments in Partner Pavilion
|-
| valign=”top” |
| valign=”top” | 2:50pm – 3:50pm
| valign=”top” |
| valign=”top” | Advanced Technology-Design-Manufacturing Co-optimization — A Triathlon

  • Subramani Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES
  • Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics

|-
| valign=”top” |
| valign=”top” | 3:50pm – 4:50pm
| valign=”top” |
| valign=”top” | Next Generation R&D and Advanced Tools for 14nm and Beyond

  • Dr. Mukesh Khare, Director, Semiconductor Technology Research, IBM Research
  • Dr. Supratik Guha, Director of Physical Sciences Department, IBM Research
  • Dr. Vassilios Gerousis, Distinguished Engineer & Technologist, Cadence

|-
| valign=”top” |
| valign=”top” | 4:50pm – 5:00pm
| valign=”top” |
| valign=”top” | Wrap-Up
Ana Hunter, Vice President of Foundry Business, Samsung
|-
| valign=”top” |
| valign=”top” | 5:00pm – 6:00pm
| valign=”top” |
| valign=”top” | RECEPTION IN PARTNER PAVILION
|-


Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs

Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs
by Eric Esteve on 02-01-2013 at 8:25 am

ASIC design service companies are an essential piece of the SC ecosystem, as well as Silicon Foundries, EDA and IP vendors. Their customers range from pure fabless with no ASIC design resources, who need a third party to turn a concept into a real product (IC) and then market and sale it, to large IDM temporarily lacking design resource to support a project. For a small fabless, building an efficient ASIC design team require a strong investment, covering H/W, up-to-date and expansive EDA licenses and also key peoples, able to successfully manage a project as well as a design team. All of the above represents a lot of energy that the management would have to spend, when the most important part of their job is the market understanding leading to the definition of the ideal system or of the “killer application” which will make their company successful. Using a third party can also be the best way to avoid traps linked to advanced ASIC technology and secure the go-to-market strategy.

Selecting an ASIC design service tightly coupled with a Silicon Foundry, like GlobalUniChip (GUC) is with TSMC is another step to a successful product release, especially during the ramp-up to production. In fact, even if your prototype is first time right, if you are not able to quickly ship the IC to your customers to support their production needs, best case you will delay the revenue flow… worst case a competitor will win the race just on the line! If you’re a Qualcomm or an Apple, you probably build a joint team with TSMC, when the size of the company is more modest, it can be useful to benefit from a well-trained team of Product Engineers, able to manage the Test, Packaging and knowing the target process. Such a service should be offered by an ASIC design service.

This (rather long) introduction help understanding what should be the positioning of ASIC Design Service, in general, and what is effectively the way GUC is running. Designing an ASIC today is often synonym to developing a large SoC. Thus, integrating pre-existing and Silicon proven IP is an absolute requirement. Pre-existing IP to speed-up the design integration, and silicon proven to minimize the risk. The design service company could decide to externally source complexes functions like Interface IP (USB3.0/2.0/1.0, HDMI V1.4 TX and RX for example) or DDR2/3 Memory Controller and PHY, to name a very few, but integrating internally developed IP will be much faster: it will ease the vendor/customer relationship, avoiding to insert another third party, and even more important, the design team will quicker integrate an already known function. Both will positively impact the design cycle, and finally improve the Time-to-Market (TTM).

GUC’s IPs are silicon and production proven in the ASIC projects of a global customer base, and provides designers with a broad range of synthesizable implementation IP, hardened PHYs and verification IP for ASIC, FPGA, and SoC designs. The GUC in-house IP portfolio includes bus interface, mixed signal, data converter, multimedia, power management, and SERDES.

  • Bus Interface IP includes digital and mixed-signal standards-based connectivity IP such as 1G and 10G SerDes (supporting GPON/EPON applications as well as XFI and 10G BASE-KR back plane applications), PCI-e 3.0/2.0, SATA 3.0/2.0/1.0, SAS 2/1, USB3.0/2.0/1.0, HDMI V1.4 TX and RX, Interlaken/Double XAUI, XAUI, SGMII, SRIO, Fiber Channel, AHB/AXI, and Ethernet.
  • Data Converter IP includes SAR and pipelined ADCs and wide bandwidth, precision and high speed DACs.
  • Mixed-Signal IP includes LVDS, power management, DC-DC converters, clock generator IP, 3.3V/2.5V high voltage tolerant/drive I/O, etc.
  • Memory Element IP includes many offerings from TSMC including single- and dual-port memory compilers and memory types are also available.
  • Peripheral Core IP includes DDR2/3 Controller and PHY IP up to 1600Mbps silicon-proven IP (next generation targeting 2133Mbps) with both wire bond and flip chip solutions.
  • Processor IP includes MCU/MPU and hardened ARM processor cores including an ARM development platform for quick prototyping.

GUC’s IPs are silicon and production proven in the ASIC projects of a global customer base, and provides designers with a broad range of synthesizable implementation IP, hardened PHYs and verification IP for ASIC, FPGA, and SoC designs. The GUC in-house IP portfolio includes bus interface, mixed signal, data converter, multimedia, power management, and SERDES.

  • Bus Interface IP includes digital and mixed-signal standards-based connectivity IP such as 1G and 10G SerDes (supporting GPON/EPON applications as well as XFI and 10G BASE-KR back plane applications), PCI-e 3.0/2.0, SATA 3.0/2.0/1.0, SAS 2/1, USB3.0/2.0/1.0, HDMI V1.4 TX and RX, Interlaken/Double XAUI, XAUI, SGMII, SRIO, Fiber Channel, AHB/AXI, and Ethernet.
  • Data Converter IP includes SAR and pipelined ADCs and wide bandwidth, precision and high speed DACs.
  • Mixed-Signal IP includes LVDS, power management, DC-DC converters, clock generator IP, 3.3V/2.5V high voltage tolerant/drive I/O, etc.
  • Memory Element IP includes many offerings from TSMC including single- and dual-port memory compilers and memory types are also available.
  • Peripheral Core IP includes DDR2/3 Controller and PHY IP up to 1600Mbps silicon-proven IP (next generation targeting 2133Mbps) with both wire bond and flip chip solutions.
  • Processor IP includes MCU/MPU and hardened ARM processor cores including an ARM development platform for quick prototyping.

Last point: the Multi-standard SerDes (pictured above) has been successfully deployed in 20+ customer projects and the IP solution integrates MAC/PCS/PMA, another guarantee of faster TTM.

To learn more about IP port-folio from GUC, just go here.

By Eric Esteve from IPNEST



Startups: the Biggest Challenge

Startups: the Biggest Challenge
by Paul McLellan on 01-31-2013 at 9:00 pm

What is the biggest challenge facing an EDA startup today? By a startup, I mean a brand new company, not a company that already has a few customers and is either on a fast path to success or a slower path whereby the company can continue to grow slowly forever.

Obviously, one challenge is the funding environment. Since EDA acquisitions have typically been at low valuations, this has put investors off starting EDA companies. Of course there have been exceptions: Apache and Denali were acquired for healthy valuations but it took a long time to get there in both cases. But with computers so cheap, cloud computing providing almost infinite resource when you need it, and modern programming tools, the amount of money required to get “ramen profitable” is a lot less than it used to be. Another challenge for EDA funding is that it doesn’t need enough money to interest VCs, who have large funds and want to invest the fund in a manageable number (board meetings etc) of large investments.

But I think money is easier to get hold of than something else critical: test-cases.

To be successful as a startup, you have to intercept the future, create technology that isn’t essential today (or someone would already have created it) but will be when you are ready, maybe at 14nm or 10nm. If you are targeting 20nm or above it’s already too late. There are only a handful of groups doing anything at all at 14nm, so how do you get them to work with you?

Answer: you can’t, at least initially. So you have to create your own test-cases to get the product developed. The trouble is that it isn’t clear what the characteristics of a good test-case are. Say someone gives you a 45nm design (even that might be a big ‘if’). How do you need to change it to be a good archetype for a 10nm design. Must be larger for sure. All those sub-20nm stuff like double patterning and layout-dependent-effects. Plus some stuff that probably nobody knows yet.

This was brought home to me during the time I was CEO of Envis. We had some power reduction technology that worked really well on the test-cases we had, reducing power (and occasionally area) by 30% or so. But those designs were old designs that had been designed during an era when power wasn’t an issue so there was lots of low-hanging fruit to be harvested. When we engaged with real customers on real designs, the power savings dropped to more like 7-8%. Not nothing, but not compelling enough for anyone to upend their design methodology.

Another challenge in EDA today is that I think many of the problems are becoming too big for a startup to handle. TSVs require changes to the entire tool flow of the big guys, not just adding a new point tool into the mix. Double patterning, ditto. FinFETs, not a point tool. I’m sure there are niches but that is a problem. Niches are small. To be successful as an EDA startup you need to have something that everyone is going to require eventually, and preferably need lots of licenses. The big guys will eventually have one but maybe you can be first. And best. And if you are, one of the big guys will probably get theirs by buying you.

But you have to get to the point of having something compelling enough to get leading edge groups to engage with you before you get your hands on a real leading edge test-case. Chickens and eggs come to mind.


Seeing inside SoC designs, from the beginning

Seeing inside SoC designs, from the beginning
by Don Dingee on 01-31-2013 at 8:10 pm

Engineers have this fascination with how things work. They are thrilled to tear stuff apart, and sometimes to even be able to put it back together afterwords. So I can keep my recovering engineer card, I thought I’d take a few moments and look inside a technology Daniel Payne and I have been covering here, exploring where the idea started and how the approach is different.

Continue reading “Seeing inside SoC designs, from the beginning”


Dynamic/Leakage Power Reduction in Memories

Dynamic/Leakage Power Reduction in Memories
by Daniel Nenni on 01-31-2013 at 8:05 pm

Embedded memories have an important impact on power. SoCs that integrate multiple functions on a single silicon die are at the heart of many electronic devices. As process geometries have scaled, design teams have used more and more of the additional silicon real estate available to integrate embedded memories that serve as scratch-pads, FIFOs, and caches to store data for the computational cores. As a result, most current designs have over 50 percent of their area used by embedded memories and these memories account for 50‑70 percent of total SoC power dissipation. Clearly, any attempt to reduce SoC power is incomplete if it does not attempt to reduce the power consumed by the embedded memories in a design.


Given the complexity of today’s SoCs, efficient power management requires a holistic approach where the control logic, data paths, and memories are analyzed together and optimized for both dynamic and static power. However, identifying sequential clock and memory gating opportunities is beyond the scope of RTL synthesis tools. Power conscious designers try to analyze the registers for redundant accesses and look for conditions under which such accesses can be shut off. There is no single known method of achieving this, and designers mostly develop this expertise over time. Even so, the process can get very tedious and error prone without suitable assistance.

In an earlier webinar Calypto presented the concept of deep sequential analysis (DSA) and how it can be used to reduce power at RTL. Sequential analysis involves temporal analysis of the complete design — including gates, flops, and memories — over several clock cycles and the examination of the stability, propagation, and observability of signal values. This is important for power optimization in identifying unused computations, data dependent functions, and don’t-care cycles in the original code.

Sequential analysis is equally applicable to embedded memories. Memories are used to store the results of intermediate computations in the data pipelines; serve as buffers between interacting computations; or serve as caches to store frequently read data. Even though locally the reads and writes to a memory may appear to be necessary, depending on the functional mode or complex control sequence of the design, they may not be needed. Removing such redundant memory accesses can result in significant reduction in the dynamic power consumption of memories.

Memory vendors provide several capabilities to reduce leakage power in memories that are not in use, and various flavors of sleep modes are now available in embedded memories, but using these modes requires the creation of controllers to generate the sleep and wake signals. In addition, the leakage power savings gained during sleep mode must be greater than the dynamic power dissipation associated with transitioning the memory in and out of sleep mode. The memory must be in sleep mode for a minimum number of cycles to actually save power. Finally, creating the sleep mode control signals and ensuring that sleep modes are triggered only during periods when the memory is quiet for an extended period require analysis of the design functionality over multiple cycles. DSA is very effective in analyzing and identifying optimum sleep modes for embedded memories.

In their next webinar Calypto will show how its patented deep sequential analysis (DSA) technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory.


TSMC ♥ Oasys

TSMC ♥ Oasys
by Paul McLellan on 01-31-2013 at 8:05 pm

Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling with new QoR and time to market issues.

RealTime Explorer enables RTL engineers to have a physically aware, implementation accurate synthesis tool for top-level PPA and routing analysis without requiring them to be physical design experts. Without an accurate tool like RealTime Explorer, RTL designers either ignore physical design issues and their impact on timing and physical issues such as congestion. Or else they have to go through a complete iteration of physical design which can take days, even assuming that tools and physical design engineers are available to perform the work.

One feature that makes a big productivity difference is the logical-to-physical cross-probing capability that makes it easy to get at the root cause of timing and routing issues before even handing the design off for physical design. It is simple to go straight from the violation in the physical domain and connect straight back to the line(s) of RTL that originate the problem.


Advanced Technology-Design-Manufacturing Co-optimization

Advanced Technology-Design-Manufacturing Co-optimization
by Daniel Nenni on 01-31-2013 at 7:00 pm

I spent some quality time with Subi Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES in Las Vegas during CES. Great guy, he worked at Silicon Access, Virage and TSMC before GF. One thing you should know about embedded memory guys, SRAM is the first thing that goes through a new process so they know their process technologies.

At Silicon Access Networks, Subi Directed a WW Engineering team to a first pass silicon sucess on industry’s first 10G classification processor SoC. At Virage, with responsibilities of WW design centers and advanced memory R&D, Subi took the Company to a leadership position on 90nm, 65nm and 40nm nodes. At TSMC, Subi was the Sr. Director in Design and Technology Platform and the Head of their North America Design Center. With a large engineering team in the US and Taiwan, Subi was responsible for technology enablement of advanced nodes and interfaced with strategic customers and partners.
Subi also has 30+ patents.

At GF, Subi is responsible for determining the technology feasibility, competitiveness and manufacturability of all elements of technology platform and to establish the advanced technology (14nm) roadmap. Subi is also one of the presenters at the Common Platform Technology Forum next week at the Santa Clara Convention Center:

[TABLE]
|-
| valign=”top” |
| valign=”top” | 2:50pm – 3:50pm
| valign=”top” |
| valign=”top” | Advanced Technology-Design-Manufacturing Co-optimization — A Triathlon

  • Subramani Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES
  • Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics

This session explores the challenges of bringing advanced technology into high volume manufacturing. Similar to a Triathlon, there are three legs: Technology Architecture Development, Design Enablement and Manufacturing Ramp. Careful co-optimization of the interactions among all three disciplines is required at each stage of the process node maturity cycle. This technical session delves into critical requirements, challenges and solutions to enable SoC level product value and accelerated Time-to-Volume at current and future nodes, and touches on new approaches such as multi-patterning, FinFETs and IC reliability checking.
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Subi will start off with a quick overview of broad requirements that drive Foundry Technology which calls for deep collaboration with market drivers. Some areas of system design and technology collaboration will be discussed. Extending Mike Noonen’s point on changing landscape in the Mobile industry, Subi will touch upon the impact to foundry business and technology requirements before discussing details of two major challenges ahead: Device Architecture and Lithography.

Next he will go into details of critical technology considerations for mobile applications with focus on power density and EM issues. He will explain the technology architecture options for reducing active and standby power in SoCs. This will lead into a discussion on why FinFET architecture requires very careful focus of parasitic modeling, EM-aware standard cell design and metrology to ensure optimization of critical SoC metrics and volume ramp. With first generation FinFET architected for time-to-volume, he will discuss how GF is leveraging their HKMG Production ramp. Further, all the SoC level optimizations done on 20nm planar, which gave it ~15% competitive area advantage, are being carried over to 14XM. He will show a comparison of critical metrics between 28nm, 20nm and 14XM that will highlight the key values of GLOBALFOUNDRIES offerings.

In the third section, Subi will go over 14XM development status and all the technology risk mitigation approaches we are using to bring up first generation FinFET into high volume quickly. Also, Subi will summarize ecosystem readiness for advanced technologies and then provide a view of the 10nm and 7nm technology roadmap. The talk will end with the importance of packaging technologies and show the GF roadmap for the next few generations.

I hope to see you there! Join me for lunch!


Building Energy-Efficient ICs from the Ground Up

Building Energy-Efficient ICs from the Ground Up
by Daniel Payne on 01-31-2013 at 6:02 pm

My oldest son just upgraded Smart Phones from a 3″ display to a 4.5″ display and was shocked to discover that his battery barely lasted 8 hours, so I welcomed him to the reality of limited battery life in modern SoC-based mobile devices. There is some hope in increasing battery life for our consumer-oriented devices and the engineers at Cadence make a case for this in a White Paper: Building Energy-Efficient ICs from the Ground Up.

Continue reading “Building Energy-Efficient ICs from the Ground Up”