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April 17-19: Overbooked!

April 17-19: Overbooked!
by Paul McLellan on 04-01-2013 at 4:23 pm
Categories: Events, Global Semiconductor Alliance, IP, Semiconductor Services

For three days in a couple of weeks time there is a crash of conferences, spread out all over the extended Bay Area.

Firstly, from 17-19th April at the Santa Clara Hyatt is the Linley Mobile Conference. This covers all things microprocessor in the mobile industry. Details of the conference including the full agenda are here. The conference is free for qualified attendees (which doesn’t include EDA company employees but does include your humble blogger). 9am on 17th Linley gives the keynote, a one hour Mobile Market Overview. Registration is here.

From 18th-19th down in Monterey is the 20th Electronic Design Process Symposium, EDPS. Ivo Bolsens, the CTO of Xilinx, gives the keynote 18th on The All Programmable SoC. Gary Smith gives the after-dinner keynote on Silicon Platforms + Virtual Platforms. On 19th, Dan Nenni (yes, new levels of SemiWiki fame or something) gives the keynote on The FinFET Value Proposition. The rest of the day is all FinFET all the time too. Once Dan’s worked out what he is going to say I’m sure he’ll be blogging about it here.

On the first day there are also sessions on ESL & Platforms, Design Collaboration, and 3D IC (the TSV type not the FinFET type). One the second day the two sessions are on FinFET Design Challanges and FinFET Design Enablement Challenges.

The full program is here. Registration is here.

On Thursday 18th at the Computer History Museum in Mountain View is the GSA Silicon Summit. Registration is free for GSA members, otherwise $50. The day is split into 3 panel sessions:

  • Disruptive Innovation: Enabling Technology for the Connected World of Tomorrow
  • How More Than Moore Impacts the Internet of Things
  • Integration Challenges and Opportunities

The full program is here. Registration is here.

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Clock Gating: Sequential Is Better

Clock Gating: Sequential Is Better
by Paul McLellan on 04-01-2013 at 3:46 pm
Categories: EDA

Sequential clock gating offers more power savings that can be obtained just with combinational clock gating. However, sequential clock gating is very complex as it involves temporal analysis over multiple clock cycles and examination of the stability, propagation, and observability of signal values.

Trying to do sequential clock gating manually is extremely difficult if at all possible, as it requires keeping track of data values over multiple cycles. But it is very attractive, especially in wide datapaths where saving unnecessary clocking can produce power savings as large as 30%. The basic idea is simple. If a register wasn’t clocked on this clock cycle, and it feeds another register on the next clock cycle then that following register does not need to be clocked on the next cycle since it already must contain the correct value. But although the basic idea is simple, getting all the details right in real world designs is not simple at all.

However, in addition to the challenge of correctly inferring which cycles to which registers can be gated, there is an equivalent problem which is how to verify that the inserted sequential clock-gating logic has been inserted correctly. Almost by definition, sequential clock gating changes the behavior of registers and memories and so introduces new verification challenges. Simulation is too time-consuming and is not exhaustive and ordinary formal verification often comes up short either in capability or in ease-of-use. What is required is sequential formal verification.

Next week, Rob Eccles of Calypto will present a webinar Impact of Sequential Clock Gating on Design Flow and Verification. This will cover the latest in sequential clock gating methodologies and its impact on the overall design flow,. He will also describe the latest sequential formal analysis, automated sequential clock gating, ECO and verification. Today, Rob is an AE at Calypto primarily supporting PowerPro. Prior to joining Calypto he was a design engineer and CAD engineer at AMD, Vitesse and Xilinx.

The webinar is April 9th at 10am Pacific. More details, including a link to register, are here.

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Power integrity: ground, and other fairy tales

Power integrity: ground, and other fairy tales
by Don Dingee on 03-31-2013 at 8:30 pm
Categories: EDA, Siemens EDA

Ground. It’s that little downward-pointing triangle that somehow works miracles on every schematic. It looks very simple until one has to tackle modern power distribution network (PDN) design on a board with high speed and high power draw components, and you soon discover ground is a complicated fairy tale with a lot of influences.

No amount of signal integrity analysis will save a design if the power integrity is lacking. We’ve been looking around at various tools for power and signal integrity, and I wanted a closer look at the Mentor Graphics offering. HyperLynx 9.0 is making its debut with new features for DDR memory analysis and more, but the baseline of features for power integrity analysis is intact from the prior version.

I grabbed an oldie-but-goodie Mentor webinar on “Design for Signal & Power Integrity with HyperLynx 8.0”, featuring independent consultant Dr. Eric Bogatin and Chuck Ferry of Mentor talking through the subtleties of PDN analysis. Eric proposed three basic goals for any design: providing stable voltages to the chip pads across the spectrum from DC to more than the bandwidth of signals; providing a low impedance return path (the correct name for “ground”) for signals; and mitigating EMI.

He then injected the first dose of reality: what does 100A look like, anyway? We think of high amperages involved in something like the circuit breaker panel on the side of our building, or in gigantic chunks of copper. On boards with multiple processors, power supply current on primary voltages can add up quickly, including spikes from simultaneous switching of signals. He sets a goal of 1mOhm impedance, from DC to GHz ranges, for a PDN.

In a simple fairy tale, there are 3 “habits” to minimize PDN impedance. The first is to place power and ground planes on adjacent layers separated by a thin dielectric, close to the surface if possible. The second is to use short surface traces for decoupling capacitors. The third is to choose the number and values of decoupling caps to fine-tune the impedance profile where needed.

In the full-length book of short stories, the darker characters in the PDN show up. There are lots of voltage rails on a board, each with characteristics of loading and decoupling. There are not enough planes as a result, and even good planes are non-optimally shaped or look more like Swiss cheese underneath difficult components (often the highest current draws). Space is always at a premium, so locating the decoupling caps may be a struggle.

Coping and hoping used to be the strategy: do what worked on prior designs, go to the “guru” and ask for his layout advice, or dump a lot of margin in with more layers to accommodate planes and more decoupling. In a better strategy, design rules and virtual prototyping enter the story to help create a “correct by design” environment with the minimum margin needed for performance goals, which helps minimize cost.

Chuck then showed some of the capability of HyperLynx in analyzing power integrity. The first is pictured above: being able to look at current density and IR drop across the layout, with the red and yellow areas where things are happen. At a more detailed level, HyperLynx can drill down and look at simulated current at each via, quickly revealing possible problem areas that may need rerouting or additional traces (usually not enough ground vias) to deliver current.

This type of post-layout visualization of power integrity can head off problems before they ruin a design. There is nothing more evil than trying to debug an elusive voltage drop on a critical area of a physical prototype, burning braincells on power instead of signaling performance. Mentor is even offering a cloud-based version of HyperLynx PI for designers to try it out.

In your experience, is the empirical wisdom of the guru still enough to succeed in power distribution on boards, or is something more analytical needed to navigate the fairy tale? Have you tried HyperLynx PI and have some thoughts? Where are you still running into problems where new tools might help? Thoughts welcome.

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Tackling Circuit Level EM Analysis for RF, MMW and High Speed Analog Designs

Tackling Circuit Level EM Analysis for RF, MMW and High Speed Analog Designs
by Daniel Nenni on 03-31-2013 at 8:07 pm
Categories: EDA, General

Accuracy, ease of use and performance have always been paramount for electromagnetic analysis software. Historically, it has been hard to find all three of these qualities in one tool. The result is that many high speed analog and RF designers resort to using multiple, often overlapping, tools to get the job done.

Lorentz Solution set out years ago to solve this problem. Their success to date shows that this is working. ThePeakView electromagnetic design platform is used by the largest FPGA, RF and foundry companies. PeakView has a finely tuned field solver, flexible passive device synthesis and automatically generates physics based RCLK models for time domain analysis.

With higher frequency designs and more advanced process nodes, the challenge has moved on to a new frontier – multiple device electromagnetics. Designers increasingly care about coupling between passive devices or interconnect, and also the effects of shielding and DFM structures like metal fills. The best example of this trend is the elevated need to model critical interconnect for inductance – not just R and C anymore. Circuit designers are learning that extraction tools are not accurate enough for the job.

Lorentz has implemented a set of new technologies that make it easy and efficient to look at coupling among devices and interconnect while considering DFM structures too. The 3.1.1 release of PeakView brings these features together.

Hierarchical EM (HEM) gives designers the flexibility to rapidly model large and complicated EM structures. A powerful direct solver handles each ‘partition’ then the coupling between partitions is factored in, producing a single EM model. Customers are using this to model caps, inductors, transmission lines and interconnect together all in one run. It is ideal for ensuring that mutual inductance is not going to interfere with circuit operation.

Incremental EM adds the ability to change and move devices around for coupling analysis and get fast results. It works by only re-simulating has what changed in the design. After the first run, all changes in subsequent design iterations will run at lightening speed – giving the designer true EM results for all devices and device coupling.

High Frequency Designer takes circuit analysis beyond simple RC extraction and adds true EM field solver capability to the LVS->LPE->Simulation flow. High port count critical interconnect is electromagnetically analyzed and back-annotated into an updated simulation view in the designer’s library.

Physics Based Interconnect Modeling ensures that designers have RLCK subcircuits suitable for SPICE simulators running time domain analysis. The problem with field solvers is that that they only output s-parameters. Lorentz had previously solved this problem for devices, but now boasts the ability to give physics based RLCK models for arbitrary interconnect.

This new suite of capabilities, running in a millimeter-wave silicon tested solver, means that designers can easily and confidently build circuits where verification includes factoring in electromagnetic effects at the circuit level, something that has never been done so easily before. Moving well integrated EM analysis and design to an earlier point in the flow means fewer iterations, more productivity and increased first time silicon success.

By Tom Simon
Director of sales and Business Development
Lorentz Solution, Inc.

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See Hogan’s Heroes at DAC 2013: The EDA Hunger Games!

See Hogan’s Heroes at DAC 2013: The EDA Hunger Games!
by Holly Stump on 03-31-2013 at 8:05 pm
Categories: EDA, Events

Risks and Rewards of Engaging with EDA Startups:The Hunger Games!

Doing business with EDA startups comes with both risks and rewards. The Hogan’s Heroes panel at DAC 2013 features key decision makers from fabless, startup and vc firms sharing candid opinions on this risk/reward equation, and the financial and technical issues of engaging with EDA startups.
·How often do companies “burn out” and users “get burned?”
·How can you protect yourself?
·And, how do customers sometimes contribute to the rise and fall?

Jim believes that startups are the innovation engine of EDA.“If you do not invest in small companies, you will get roadmaps from the EDA “gorillas” but not much new technology. Certainly there is risk, but without startups, we don’t see a lot of innovation.”

Hear what the panelists have to say!

Moderator: Jim Hogan, Private Investor

Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 35 years gaining experience as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies. Mr. Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A., all from San Jose State University.

Panelist: Atul Sharan, Artiman Ventures

Atul is currently Entrepreneur in Residence, Artiman Ventures. Previously, Investment Advisor at Darwin Venture Management; President & CEO AutoESL (acquired by Xilinx); Corporate Consultant at Cadence Design Systems; Founder, President & CEO at Clear Shape Technologies (acquired by Cadence); Resident at Mohr Davidow Ventures; Vice President – Marketing, Business Development & Applications at Synopsys; Senior VP – Worldwide Sales & Marketing at Numerical Technologies Inc. (IPO; acquired by Synopsys); Business Development & Marketing at Ambit Design Systems (acquired by Cadence); GM – India Operations at VLSI Technology Inc., Compass; Engineering Manager at Altera; and at IDT. Atul’s education spans the University of California, Berkeley – Walter A. Haas School of Business, MBA, Finance & Management; University of Houston MS, Engineering; and IIT Kanpur, BS, Engineering.

Panelist: Sanjay Lall, Board of Directors, Ausdia Inc.

Sanjay Lall is currently on the Board of Directors at Ausdia, with over 20 years of experience in the electronic design automation (EDA) and semiconductor industries. Sanjay is also chairman and managing partner at Cronox Group, on the board of advisors at Verdigris Technologies, and a director at Mobi-holdings.Previously VP of worldwide sales at Extreme DA, acquired by Synopsys in2011; President and CEO at Silicon Software; President & CEO at NION Interactive; and accelerated sales growth for EDA companies such as Sente (acquired by Frequency Technology), Triquest (acquired by Summit Design), Ultima Interconnect (acquired by Cadence), Frontline Design Automation (acquired by Avanti), CadMOS (acquired by Cadence), Plato Design (acquired by Cadence), Q Design (acquired by Cadence), Brion Technology (acquired by ASML) and Epic Design (acquired by Synopsys).He holds a B.S.in electrical engineering and computer science from Santa Clara University.

Panelist: Dave Crohn, Senior Director, Engineering, Broadcom….and DAC Party Singing Idol!

Dave currently manages all of EDA for Broadcom Corporation, a leader in the industry providing broadband communications. Dave had done design work for 24 years starting with Sperry (later Unisys) back in the ECL days; ETA Systems designing a 10 GFLOP supercomputer in liquid nitrogen; Siemens including 1 year working in Munich; ADC Telecommunications; then Motorola; and finally on to Broadcom where he’s been for the last 14 years. At Broadcom he originally managed the standard cell team and later moved into the managing EDA role at Broadcom for the last 9 years. Working for thedifferent companies gave Dave the opportunity to work with many different EDA tools as well as different technologies throughout his career. This now lends itself to working with engineering at Broadcom to determine best in class technology to pursue corporate-wide. Dave also negotiates the contracts and manages EDA supplier relationships. Dave holds a BSEE from the University of Minnesota.

Let the EDA Hunger Games Begin…

Join us Tuesday, June 4, at DAC 2013 in Austin Texas. For more information, please see www.dac.com

And, to EDA startups and their customers:

“May the odds be ever in your favor!
Ever in your favor…..”

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Samsung 28nm Still Does Not Yield?

Samsung 28nm Still Does Not Yield?
by Daniel Nenni on 03-31-2013 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC

As if Samsung didn’t have enough to worry about with their new neighbor to the North (Korea) declaring war, Samsung 28nm is still NOT yielding. In my previous blog “Can Samsung Deliver as Promised?” I wondered what will power the new Galaxy S4 phones that Samsung has been aggressively marketing. You would think it would be a 28nm version of the Exynos 5 Octa SoC that was launched at CES in January with former President Bill Clinton. As it turns out that is not the the case. I like honesty, I like transparency, I don’t like how Samsung is communicating with us on this one.


The first launch of the Galaxy S4 will be powered by 28nm silicon all right, TSMC 28nm silicon in the form of a QCOM Snapdragon 600. That must really hurt the Samsung foundry folks since they are negative selling TSMC and others at the top fabless semiconductor companies in an effort to win 14nm business. At first it was rumored that it was an LTE issue with Exynos but Samsung denied that recently on Twitter of all places. The people I asked here in Silicon Valley, one of which is a Samsung customer, said it was in fact a 28nm manufacturing problem.

Remember, Samsung went Gate-First HKMG instead of Gate-Last like TSMC:

Gate-first HKMG is easier to implement as a transition from a traditional poly/SION structure, she explained. The construction of the gate and transistor remain the same, though the materials are different (i.e., a high-k gate oxide instead of oxynitride); a metal gate is inserted, and then poly on top of that—and the rest of the flow is “basically the same as previous generation structures.” Gate-first also is “much simpler” to implement from a process migration standpoint in terms of IP implementation, and fewer restrictive design rules (gate-last requires CMP around the gate structure). “We can maintain 50% shrink from 45nm to 32nm because there’s not as many restrictive design rules,”Ana Hunter (VP foundry at Samsung Semiconductors)said. This makes the process particularly good for mobile applications, as it’s cost-effective and “very good on gate leakage—a >100× improvement from 45nm to 32nm.”


During one of my Taiwan trips in 2010 I asked Dr. Shang-yi Chiang why TSMC decided on Gate-last versus Gate-first. Shang-yi is TSMC’s Executive Vice President and Co-Chief Operating Officer, he joined TSMC in July 1997 as Vice President of Research and Development (R&D) and has successfully delivered many new process technologies including 28nm. Shang-yi told me quite honestly that TSMC had both Gate-first and Gate-last 28nm HKMG architectures under consideration but concluded that yes Gate-first is simpler (less manufacturing steps) and would be easier to design to (less restrictive) but it was much harder to yield, especially for complex SoCs. The rest is history, TSMC successfully implemented Gate-last 28nm and they have 100% market share as a result.

This all goes to credibility which is the cornerstone of collaboration and the fabless semiconductor ecosystem. Let’s not forget how all this fabless stuff got started. The traditional semiconductor companies (IDMs) were not doing their jobs. They rented out their excess capacity allowing former employees to innovate and bring us companies such as QCOM, BCOM, NVDA, XLNX, and the resulting fabless semiconductor ecosystem.

Now, Intel and Samsung (both IDMs) are trying to get back control of the semiconductor industry and will spend whatever it takes to do so. According to IC Insights, their combined capital expenditures now represent more than 40% of the total semiconductor capital spending. To me this is a great cause for concern for the fabless semiconductor ecosystem. Just my opinion of course.

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Circuit Analysis & Debugging

Circuit Analysis & Debugging
by Daniel Payne on 03-30-2013 at 3:18 pm
Categories: Concept Engineering, EDA

Spice Debugger

In EDA we often talk about how fast a SPICE circuit simulator is, or about capacity and accuracy compared to silicon measurements. Yes, speed, capacity and accuracy are important, however when talking to actual transistor-level circuit designers you discover something quite different, most of their time is spent doing debugging, looking at waveforms, reading tables of text results, and trying to understand why the circuit is acting differently than intended. In order to really understand what is happening with your newest IP block or re-used IP, you need some automation help in looking at the netlist or interconnect in a visual way.

Fortunately there is help and it comes in the form of an EDA tool that lets you visualize any SPICE netlist so that you can quickly traverse it. Talking about it doesn’t do much justice, so instead I invite you to attend an online webinarhosted by Concept Engineering and EDA Direct, scheduled for Tuesday, April 9th from 10AM to 11AM, PDT.

Webinar
Here’s what will be covered during the webinar:

  • Understand the topology and function of the circuit without having schematics
  • Automatic Schematic generation from Spice, DSPF, LVS Spice, Spectre
  • Traverse hierarchy, search nets/instances very fast
  • Cross probing with GDS for highlighting nets
  • Verify connectivity especially for multi fanin and fanout nets
  • ERC Checking: Floating input and output nets, heavy connected nets, etc.
  • Generate design statistic & reports: Instance & primitive counts
  • Turn on/off Parasitics from extracted netlist to debug designs quickly
  • Debug power/ground connectivity issues
  • Analyze results of LVS runs and use the automatically generated schematics from the extracted SPICE netlists with RC network
  • Full chip netlist tracing (top level integration and block level)

EDA Tools
The German-based engineers from Concept Engineering have a range of tools to help you analyze and debug your IC designs:

  • Transistor-level debugging
  • Gate-level debugging
  • RTL-level debugging
  • Mixed-signal debugging (Transistor, Gate and RTL)

Further Reading

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Dan Niles Economic Review: Q1 is the Bottom

Dan Niles Economic Review: Q1 is the Bottom
by Paul McLellan on 03-29-2013 at 7:38 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

Every quarter GSA runs a webinar with Dan Niles of Alpha One Capital Partners on what the semiconductor outlook is. He doesn’t actually focus on the semiconductor industry itself, demand for chips is really driven by economic conditions in the major markets around the world. People who are unemployed, or in Cyprus, don’t buy so many chips as people in booming economies.

I actually think that some micro-techy things are important too. Windows 8 is not receiving rave acceptance either in the home or business markets. But iPad (and similar tablets) are exploding. I admit that when I heard about the iPad announcement I was “meh” and figured I’d never want one. After all I have a smartphone and a laptop already. But I was completely wrong (along with most of the punditry). I did do better than many on predicting that x86 compatibility in the sub-notebook market would not be an issue and whatever-they-were would turn out to be more like an overgrown phone than a shrunk PC. Here is what I wrote in 2009, back when MID stood for “Mobile Internet Device” because we weren’t sure what they were yet:”My gut feel is that a MID will be more like a souped up smartphone than a dumbed down PC, and so Atom will lose to ARM. In fact I think the smartphone and MID markets will converge. Microsoft will lose unless they port to ARM. There will be no overall operating system winner (like with smartphones).”


So one of the big worries is that BRIC (Brazil, Russia, India, China) growth has slowed and Europe is in a recession with unemployment (especially among the young) ridiculously high in several countries including some large ones like Spain.


European debt levels are high, and due to problems with the Euro we hear about them a lot. But two other big markets, Japan and the US, actually have higher debt levels. The United States at 103% of GDP is not just higher than Europe, it is almost the same as the PIIGS, the sick countries (Portugal, Italy, Ireland, Greece and Spain) who are only at 104%. Japan at 230% is in a league of its own, and with fertility not that much above 1 child per female and essentially no immigration, they are on a “going out of business” trajectory.


Dan’s view is that in 2013 the semiconductor market will bottom out in Q1 and grow more strongly in the second half of the year. The biggest issue is probably deleveraging, reducing the amount of debt. There are two problems with this. Individuals in most countries are aggressively deleveraging and this means they are paying down debt rather than buying electronic goodies, new cars, new TVs etc. But government is still not delveraging, in general, they are going the opposite way.

But IT spend should outpace GDP growth, which is obviously good. And future customer interest looks good:

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Design Automation Conference: Go For It!

Design Automation Conference: Go For It!
by Paul McLellan on 03-29-2013 at 5:35 pm
Categories: EDA, Events

The conference program for DAC is now live here including the conference itself, keynotes, some other special tracks, the pavilion panels and more. And the must-see panel is on emulation at 4pm on Tuesday afternoon moderated by…well, that would be me so I’m a bit biased.

Registration is now open here for both attendees and exhibitors.

Hotel reservations are here (they have been live for some time).

As I’m sure you already know, DAC is in Austin for the first time this year. It is also the 50th DAC. There are many special events at DAC both looking back over the past 50 years and looking at the contribution of the Austin area to electronics. I’ll have a more detailed review nearer the time but for now, go and register.

And there is great Texas barbecue and more live music than you can imagine.

Bringing DAC to Austin
Major Employers of Design Engineers in Austin
 [TABLE] style=”width: 600px”
|-
| align=”left” valign=”top” |

  • 3M Co. (1000)
  • Advanced Micro Devices (2933)
  • Agere,Inc.
  • Alereon
  • Altera (50)
  • Analog Devices
  • Aperian
  • Apple (3000)
  • Applied Materials (2250)
  • Applied Micro
  • Applied Science Fiction
  • ARM (100)
  • ASI (Advanced System Integration)
  • BAE Systems (675)
  • Centaur (40)
  • Cirrus Logic
  • Cisco Systems (800)
  • Cypress
  • Dell (10,000)
  • DuPont Photomasks Inc.
  • Flextronics (1875)
  • Freescale Semiconductor (5000)
  • Hewlett-Packard (550)
  • IBM Corp. (6239)
  • Image Microsystems (500)

| align=”left” valign=”top” |

  • Intel Corp. (1000)
  • InterSil (40)
  • LSI (30)
  • Microsemi (40)
  • Motorola
  • National Instruments (2200)
  • Oracle (515)
  • Photronics
  • PulsewaveRF
  • Qualcomm
  • Rocket Chips
  • Samsung (1100)
  • SGI
  • Silicon Group Inc., The
  • Silicon Hills Design Inc.
  • Silicon Laboratories (500)
  • SMSC
  • Spansion (900)
  • Stellar Micro Devices
  • TI (100)
  • Tokyo Electron America Inc.
  • Vitesse Semiconductor
  • WindRiver Systems

|-

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA). Members of a diverse worldwide community from more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.