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Denali+Tensilica+Cosmic = Cadence

Denali+Tensilica+Cosmic = Cadence
by Paul McLellan on 04-17-2013 at 1:00 am
Categories: Cadence, IP

I won’t be able to attend Chris Rowen’s presentation here at the GlobalPress Electronic Summit since I’m going to the first day of the Linley Mobile Microprocessor conference. In fact I wonder if Chris himself will make it since he was running in the Boston marathon on Monday. He finished about 10 minutes before the explosions but was close enough to hear them and see the smoke.

Anyway, I have a advance copy of his presentation which looks at a couple of things. One is Tensilica’s recently announced video processor that I already covered here. So I’m not going to cover that again.

Of course, Tensilica is in the process of being acquired by Cadence and so the other topic is how Tensilica fits in, or technically will fit since I don’t believe the acquisition has closed. Cadence are also in the process of acquiring Cosmic Circuits which may take some time to close since they are an Indian company.


Along with other IP Cadence already has, in particular resulting from acquiring the Denali product line and its expertise, Cadence has a much more rounded out IP offering than was the case as early as the beginning of this year. Martin Lund seems to have a fat wallet and likes going shopping.

The combination of the earlier Denali memory interfaces along with additional interfaces from Cosmic Circuits gives a rich portfolio of connectivity. Then the Tensilica offering, along with other partners such as ARM, gives a range of different specialized processors for particularly attractive markets. ARM and Tensilica are complementary, in the sense that the ARM processor is the control processor for a design and then one or more Tensilica processors can be used to offload, for example, video compression or hi-fi audio.


Having talked to Martin recently, Cadence has a sort of factory view of IP. If you just go out and acquire random IP based on price, there are basically limited quality standards and low expectation that everything will work well together. If IP is basically completely pre-characterized with no opportunity to make incremental change, it is hard to differentiate and the IP is not well matched to the design (for example, there may be a lot of silicon used up that implements features that are not used in the design). By adding a service component, the IP is customized to what is required without compromising quality or performance.

Where Tensilica fits in is to accelerate time-to-market with silicon-proven customizable design IP, optimized for various high-volume applications such as audio, video, cell-phone LTE modems. It is very complementary to Cadence’s other IP in connectivity, AMS design, VIP and so on. For the key market segments where Tensilica has customizable application specific dataplane processors, the Tensilica acquisition will really strengthen the Cadence IP offering, and make it much easier to go seamlessly from architectural definition to tapeout.

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FPGAS – The New Single Board Computers?

FPGAS – The New Single Board Computers?
by Luke Miller on 04-16-2013 at 10:00 pm
Categories: FPGA, Xilinx

I have always felt that FPGAs have been the red haired step child of Silicon Valley. Software weenies have hated them, they are mysterious and take too long to route. Even though they can be massively parallel and the most deterministic piece of silicon you can buy besides a million dollar ASIC, the GPU steals their glory, for now. Until the System Architect realizes once again, they just have to use the FPGA, sigh. But if they could design them out they would. Evil laugh… Muhahahahah

You are probably thinking what a horrible picture of FPGAs. I know but it is true but that is going to change and in the future really change! The game changer is of course the Zynq SOC from Xilinx. Let’s face it, and you know it, you only used that big honking Intel or Free Scale CPU to do BIT, Status, Control or some out of band math when it is tied to an FPGA. Then for some reason the software team always quote a $1,000,000 NRE for a change for one line of code. I found it a bit amusing when the FPGAs were called the off load engine, yeah right. Any time an FPGA meets a CPU, the CPU is the offload and the FPGA is doing the real work. Please no emails or comments just agree please.

This Zynq is really a Rack on a Chip, ROC. It is also an almost self-contained single board computer. Take some Elmer’s all glue and put some Flash and DDR3 and there you go, maybe a few pieces of macaroni like my kids do for art. My point is that the software guys are going to be programming FPGAs very soon. This will open the FPGAs up to these nerds like the GPUs are via CUDA and the likes. The next step is learning Vivado HLS. The communities that once disliked FPGAs are now the ones that will really fall in love with them. As for the board vendors, they have much to think about and perhaps relations with CPU vendors may become a bit stressed, as well with the RTOS as well, maybe.

If I could talk with the Xilinx CEO I would have one suggestion for him. The Zynq is indeed in the right direction and keeps Xilinx as the FPGA player for this node. They need to do more to address the GPU threat, and it is real. The advantage of the GPU is that the GPUs are virtually in every PC. No one has to buy an evaluation board for $2000. Ever hear of a college hacker with 2k? A whole underground world of nerdom supports the GPUs for free. If Xilinx could weedle its way onto motherboards or into a smart phone offering, Xilinx would gain a whole community that will develop apps, IP and more for free provided that Xilinx opens the tools up for free. I know that sounds self-serving and I used the word weedle but I can think of many areas where the Zynq will fit into smart phone or mother board realm. Sounds fun does it not? FPGAs are changing for the better and more probably coming soon, embrace it or probably lose your job to some new hire.

lang: en_US

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Atrenta, Forte and Jasper LOVE DAC

Atrenta, Forte and Jasper LOVE DAC
by Paul McLellan on 04-16-2013 at 8:20 pm
Categories: EDA, Events

I LOVE DAC is back. This year the sponsors are Atrenta, Jasper and Forte (hey, all semiwiki subscribers). The way it works is that you register on the DAC website here and you get a free three-day exhibit pass. In addition to everything going on in the exhibit hall, including the pavilion panels held there, the pass also gives access to:

  • Five keynotes from National Instruments, TI, Qualcomm, Freescale and Samsung
  • “Designed in Texas” sessions on the designer track
  • Sunday night welcome reception, Monday night Kickin’ it up in Austin party, Tuesday reception and Wednesday reception and poster session

But there is more. Go to the booths for Forte #1547, Jasper #2346 or Atrenta #1847 and get an “I LOVE DAC” badge. Or if you have one from previous years wear that. People spotted wearing one of these badges will randomly be given tickets to a drawing at 3.15 on Wednesday at the DAC pavilion panel. The winner gets a MacBook Pro with retina display.

Full details and a link to register are all on the DAC website here. You must register by May 17th.

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Wally Rhines: Embedded Software the Next Revolution?

Wally Rhines: Embedded Software the Next Revolution?
by Paul McLellan on 04-16-2013 at 8:10 pm
Categories: EDA, Siemens EDA

As seems to be traditional, Wally Rhines gave a keynote here at the GlobalPress Electronics Summit here in sunny Santa Cruz. It was entitled Embedded Software, the Next Revolution in EDA. Unlike Cadence and Synopsys, Mentor has a strong position in embedded software. It has been build up over a long time through a series of acquisitions (plus lots of internal development, of course).

First they acquired Microtec in 1998 and got the XRAY debugger and VRTX RTOS. Next, in 2002 they acquired Accelerated Technology (ATI) along with the Nucleus operating system (the volume leader if not the $ leader at the time, since it was royalty free). A couple of years later they acquired Embedded Alley with expertise in Android and Linux. In 2010 they acquired CodeSourcery, a major player in open source tools and services. And just recently they acquired MontaVista automotive from Cavium (who acquired all of MontaVista back in 2010).


The growth in software, both in the number of lines of code in a typical SoC or embedded system (think a car or a smartphone) and in the number of engineers involved is incredible. And it is only going to get worse, so if the secret can be cracked it is a huge opportunity.


Of course the holy grail in EDA is to get the hardware people and the software people onto some sort of common infrastructure, since the chip and the software and the IP are now so intertwined. Mentor tried this early on with their Seamless product. But despite having designed the product for the software developer, only hardware developers bought it. So instead of being used for software development, designers were using it to stimulate their design using software. Software people didn’t use it for a couple of reasons. Firstly, it cost $50,000. To an design group, that is a reasonable cost for an EDA tool. For a software group, even $1,000 is too much. But also it didn’t give the software people what they needed, namely to live in the environment that they were used to and do things the way they were used to.


So gradually it dawned on everyone that the grand unified field theory of EDA wasn’t going to work. What was actually required was to let software developers live in their favorite environment and deliver them what limited information they needed in terms they can understand (which means not talking about SystemC TLMs or Verilog), and correspondingly give the hardware designers whatever software information they needed in terms they could understand.


CodeSourcery is widely used. It is the preferred toolchain for leading edge semiconductor companies. It is downloaded 15,000 times…every month. Last year it was downloaded 150,000 times and there were 300 releases. The scale of a large open source project is incredible when you are used to EDA volumes (but correspondingly the price point is disappointing when you are used to EDA prices, namely free).

I asked Wally if they actually made money on the software part of the business. He emphasized that the embedded division is profitable, it is the fastest growing part of Mentor. Their CodeSourcery service business that tailors the open source code for specific companies is the most profitable service business in the company with margins above emulators and nearly as high as pure software. Wow, that’s pretty impressive for software that anyone can “just” download and alter themselves.

I believe that this is a rough preview of Wally’s keynote at U2U next week. The detailed agenda for U2U is here. Details about attending, including a link to register are here. The conference is free and includes a free lunch (so there is such a thing).

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Cavendish Kinetics

Cavendish Kinetics
by Paul McLellan on 04-16-2013 at 8:05 pm
Categories: Events, IP

I have spent the last couple of days at the GlobalPress Electronics Summit at the Chaminade Resort in Santa Cruz. Hey, it’s tough, but someone has to do it. One interesting presentation was from Cavendish Kinetics. It is especially interesting because many years ago Cavendish was founded by Mike Beunder, who I know well since I hired him to work for me in France and then moved him to the US to work for me over there. Cavendish was founded when he returned to Netherlands where he is from. The original mission was to use MEMS technology to make non-volatile or one-time programmable memories. The technology worked by bending metal up or down using electric fields at the micro level to make or not make a contact. To my surprise, at that scale, if you bend the metal it basically stays where you put it and so that is where the programmability came from. This business wasn’t successful since the market for non-volatile memory has a lot of entrants with different technologies (SiDense, Kilopass to name but two) and the market for one-time programmable memory is small and the market for non-volatile memory is dominated by flash.


Mike moved on and Dennis Yost the CEO presented what Cavendish is currently doing. It turns out building a good cell-phone radio given the crappy antenna that you can fit inside the phone is hard. But you knew that. One thing that makes it especially hard is that the radio has to operate across a very wide frequency spectrum to cover the entire cellular band. If it were possible to build a radio that only worked in a narrow band but easily retune it so the optimal band could be moved around, then that would be great. As it is, the difference in performance between what is theoretically possible and what is delivered is large and growing larger. This is called antenna frequency tuning.


The key problem is that if you have active circuitry in there, the resistance kills you and you still can’t build an optimal radio. But wait, if you happened to have, say, a technology that made or opened metal circuits using an electric field then maybe you’d have the perfect switch technology with very low resistance that would be a perfect solution to this problem. It was unclear to me in the presentation if they were using the MEMS technology directly to vary a capacitor by moving the metal, or whether they were using the MEMS as switches to switch capacitors in and out. It is a third-generation of something at least similar to the original technology they started out with.

They have build antenna tuning chips. They are tiny and seem to be very reliable, working for billions of cycles with no drift. The gains are greater than 1.3dB which is a 35% increase in efficiency. Like basically every successful MEMS company (ADI, ST etc) they control their own design, their own technology and do their own volume manufacture. It will probably be years before MEMS can be done in a fabless/foundry model.

lang: en_US

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FinFETs: Ask the Experts II!

FinFETs: Ask the Experts II!
by Daniel Nenni on 04-16-2013 at 7:45 pm
Categories: EDA, Events

As I have mentioned 28 times already, on Friday (April 19[SUP]th[/SUP]) I will be keynoting FinFET day at the EDPS conference in Monterey. This is an excellent opportunity to ask the experts about the challenges of FinFET design and manufacturing in an intimate setting (60 people). If you are interested register today and use the promo codeSemiWiki-EDPS-JFR and save $50.

I wrote about the morning session here: FinFETs: Ask the Experts!I just reviewed the final slides and WOW! The presentations from Raymond Leong and Tom Dillinger are the best FinFET content slides I have seen yet! Don’t miss this event! Seriously, WOW!

In the afternoon there will be a panel discussion with Betty Pokerwinskiof Qualcomm, John Heinleinof Arm, Luigi Capodieciand Srinivasa Bannaof GLOBALFOUNDRIES. I will be moderating and I would like to thank everyone that helped with the questions. They are still coming in but this is what I have so far:

[LIST=1]

  • What can we do to improve early engagements with customers?
  • What challenges your team the most going from a previous process node to FinFET?
  • Which IPs libraries will have the highest impacted going to FinFET?
  • Can you expand on IOs, ESD structures, and analog components (diodes, resistors, capacitors)?
  • What are the trade-offs for the standard cell track heights between planar and FinFET?
  • How is FinFET technology giving you more opportunity to broaden your market, low power to server core performance? (ARM)
  • How are you working with the foundries to reduce VDD_min for very low power applications?
  • Is ARM adding to core designs additional error detection and recovery circuits for FinFETs?
  • What does GF see as trade-offs for FinFET fabrication for bulk versus SOI?
  • How does GF develop a process to address the range from very low power to high performance server and communications market?
  • What do you see for FinFET layout dependent effects compared to planar?

  • Do you see any new or more severe reliability failure mechanisms or transistor drift with FinFETs?

  • FinFET offers higher drive current and higher gate capacitance. So is there a netbenefit in performance at Iso Power or reduction in power at Iso frequency?
  • Do FinFETs bring any benefits to SoC area scaling? Is so what are some thoughts on area scaling?
  • What else can we do in EDA for you in regards to FinFET Parasitic extraction, Electro migration (EM), Thermal Modeling?
  • What other challenges are you experiencing that may not have been touched on here?

    I need four more so we can play 20 questions.Post them in the comment section or email them to me directly.The panel starts right after lunch and alcohol will be served so expect the unexpected!

    lang: en_US

    • Posted on

    Xilinx: Hide the RTL

    Xilinx: Hide the RTL
    by Paul McLellan on 04-16-2013 at 7:30 pm
    Categories: FPGA, Xilinx

    Tom Feist of Xilinx presented here at the GlobalPress Electronics Summit about their strategy to take design abstraction up another level. In the SoC world, we are still pretty much stuck at the RTL level and have moved to higher abstractions by using an IP strategy. But at least all IC designers are RTL-literate.


    Xilinx, in the Vivado suite, also has an IP strategy supported by tools that help pull everything together and make sure that you can’t make stupid mistakes by mis-connecting the wrong inputs and outputs. But they also have another problem: increasingly, the people that they want to target to use FPGAs don’t know RTL. They are working at the C level or the C++ level. Or they are using Mathworks. Or labview. Or openCL, a standard for parallel programming (and GPU programming).

    The grand vision is to enable these people to go directly from whatever environment they are in, directly to the bitstream that programs the FPGA and the software that runs on the processor embedded in the FPGA. Of course, under the hood, there will be RTL generated and then the normal synthesis and P&R will be run. But this will be hidden from the user in much the same way that a C programmer doesn’t need to understand x86 assembly code or even ever see it.


    From C, C++ and SystemC the route is using Vivado HLS (which is the next generation of the AutoESL technology that Xilinx acquired a couple of years ago). Mathworks already has the capability to generate C and Verilog. Labview (from National Instruments) are working to embed Xilinx’s Vivado under the hood so that designers can go straight from their labview environment to FPGA without ever leaving the environment. The idea is to push design up to the system level and regard RTL as a sort of “intermediate code” that most users will never see.

    In addition, they are adding libraries starting with OpenCV (computer vision) and some other video libraries. This is a library of algorithms for (surprise) computer vision. But they will be available both as callable software procedures or as FPGA subsystems. Depending on the performance required the algorithms will run either as software or as designs optimized into the FPGA fabric for much higher performance. I’m not sure if the plan is to pre-create these or whether the C-code is simply run through HLS on the fly.

    It is a bold strategy to push design up to the system level. C-based HLS has a reputation for being a bit tricky to use, not all C just runs cleanly through and produces a good implementation. But Xilinx have 350 customers using it and another 1000 evaluating it, so that’s a pretty sizable installed base. I’m not sure if 350 customers means 350 different companies or 350 copies installed.


    Ivo Bolens, CTO of Xilinx, will also cover some of the same ground at the EDPS in Monterey on Thursday morning. You can read my preview of his keynote here.

    EDPS Thursday and Friday, April 18th and 19th. The full program is here. Registration is hereand use the promo code SemiWiki-EDPS-JFR to save $50. Call the hotel directly for room reservations.

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    Altera, Intel, TSMC, ARM: the Plot Thickens

    Altera, Intel, TSMC, ARM: the Plot Thickens
    by Paul McLellan on 04-16-2013 at 7:15 pm
    Categories: Arm, FPGA, Intel Foundry, TSMC

    Vince Hu of Altera presented us her at the GlobalPress Electronics Summit on their process roadmap. Since just a month or two ago they announced that Intel would be their foundry at 14nm, everyone wanted to get a better idea of what was really going on.

    At 28nm, Altera use 2 processes, TSMC 28HP (for high end Stratix-5 devices) and TSMC 28LP for mid-range, low-cost devices.


    The next generation will use 3 processes. At 20nm their partner remains TSMC. TSMC’s 20nm is a planar process (FinFET starts at 14nm). At 14nm their foundry is Intel, with their TriGate process (their name for FinFET) which they will use for the highest performance devices. And they will also use TSMC’s 55nm process with embedded flash to make hybrid devices that are a bit like a PLD and a bit like and FPGA.

    One interesting thing Vince said, just as an aside, was that 20nm will be lower power, higher performance and lower cost. Since there have been a lot of rumors that TSMC 20nm may not be cheaper than 28nm, that was an interesting datapoint. Altera will be announcing products here later this year.

    So we started to ask questions.

    Microprocessors? ARM is a great partner, at 20nm we are committed to ARM. What about 14nm? Is Intel going to manufacture ARM? Is Altera going to put Atoms on FPGAs? Too soon to comment but there may be an announcement soon. So my guess would be that Intel isn’t going to be building ARMs into Altera arrays and some sort of Altera/Intel processor deai will be announced in the future.

    What about TSMC’s 14nm FinFET process? When that is available is Altera going to use it? Not discussing at this point.

    How about 3D? TSV? Not ready to talk about it yet.

    Vince, master of the cryptic remark, did say they are looking at what comes after, especially in the cost-sensitive space. They may even look at process technologies that are already out today. My guess would be that they might design lower cost arrays into 28nm once 28nm is no longer leading edge and wafer costs drop.

    So FinFET is focused on Intel but they remain committed to TSMC. ARM is a strong partner but it remains to be seen what that means at 14nm. The future is a bit murky out there.

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    Webinar: Making a Simple, Structured and Efficient VHDL Testbench

    Webinar: Making a Simple, Structured and Efficient VHDL Testbench
    by Daniel Nenni on 04-16-2013 at 1:47 am
    Categories: Aldec, EDA

    logo bitvis

    Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement and provide close to no support when debugging potential problems. This webinar will demonstrate how to build a far better testbench with respect to all these issues – in significantly less time. The webinar will also explain how this verification approach results in reduced design and debug time with the help of an open-source testbench infrastructure library.

    Guest Presenter: Espen Tallaksen, Bitvis CEO and Principal FPGA/ASIC Developer
    [TABLE] cellpadding=”2″ cellspacing=”2″ style=”width: 90%”
    |-
    |
    | Bitvis is a vendor independent Design Centre with competent designers, experienced in Embedded Software and FPGA/ASIC development and verification.
    |-

    Agenda

    • Making a verification specification
    • Defining your testbench architecture and concept
    • General testbench infrastructure library and methods
    • Implementing the testbench architecture
    • Implementing testcases

    For more information, please visit http://www.aldec.com/events

    Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
    www.aldec.com

    lang: en_US

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    Variation-aware IC Design

    Variation-aware IC Design
    by Daniel Payne on 04-15-2013 at 4:18 pm
    Categories: Cadence, EDA

    We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, created in December 2012, so I spent an hour today viewing it. Steven Lewis started out the webinar and then Alan Whittaker did a product demo showing how he uses Virtuoso to find and fix LDE issues.


    Steve Lewis, Cadence
     Continue reading “Variation-aware IC Design”