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Tempus: Cadence Takes On PrimeTime

Tempus: Cadence Takes On PrimeTime
by Paul McLellan on 05-20-2013 at 7:00 am
Categories: Cadence, EDA

Today Cadence announced Tempus, their new timing signoff solution. This has been in development for at least a couple of years and has been built from the ground up to be massively parallelized. Not just that different corners can be run in parallel (which is basically straightforward) but that large designs can be partitioned across multiple servers too. So Tempus is scalable to 100s of cores/servers. This scalability also means that it can handle essentially any size of design, and has already been used to analyze 100s of millions of cells (placeable instances) flat.

Of course timing closure is getting more difficult. Designs are getting larger and increased margins (e.g non-self-aligned double patterning at 20nm) make timing closure harder. Plus the number of views that need to be analyzed is also increasing exponentially leading to extremely long run times (days, not hours).

Timing closure at 20nm is growing to up to 40% of the design cycle. I’m assuming that design cycle here means the synthesis, place and route, signoff cycle and doesn’t include the RTL development and verification. As you know, modern SoC design teams are largely assembling blocks of IP that have either been purchased or developed internally in special IP development groups. In fact one o the problems with timing closure is that problems with the IP with regards to routability (which shows up often as timing violations) only comes to light suring SoC assembly.

The order of magnitude increase in performance means that it is possible to do large amounts of path-based analysis (PBA). PBA traces timing through the actual input/output pins and propagates the correct slew values. Traditionally this has been too expensive to do extensively and a more pessimistic approach is used, taking the worst (slowest) input pin and using that as a proxy for all input pins. The difference is around 2-3% in reduced pessimism. This has two effects. Firstly, some paths that violate timing without PBA will be OK with PBA and so do not need to be addressed during timing closure. And paths that still do not make timing will miss with smaller negative slack and so will not require such aggressive changes to fix. The added margin can also be taken in the form of slower/smaller/lower-power cells.

Another interesting feature is the ability to do hierarchical/incremental analysis. This makes it possible to look at just a single block (if that is all that your team is focused on) but have the timing numbers match precisely as if the entire chip was being timed. So a hierarchical design can be handled within an accurate global context.

Tempus has a tight iteration cycle with place and route, producing physically aware optimization (legalized, DRC-clean placement directives) so that typically 2-3 iterations are enough to achieve timing closure, as opposed to the all-too-common case where each set of changes fixed causes another set of paths that were previously OK to suddenly need addressing, the dreaded whack-a-mole situation where timing doesn’t really close.

Cadence have been working with Texas Instruments as a lead customer. One design (which I assume is a TI design but may not be):

  • 28nm, 44M instances, 12 views
  • Existing flow: 10 days to fix hold violations, could only work on 7 views due to capacity limitations
  • Tempus: 99.5% hold violations fixed in one ECO iteration with no degradation in setup timing. Before using Tempus there were 11,085 timing violations and after there were just 54

Cadence are working with the foundries to get Tempus signed off as signoff. For smaller fabless companies that cannot afford to do their own correlation this is essential, of course, to even be considered.

The big challenge for Cadence that I see is that it is very hard to replace “standard” trusted tools that are good enough. That’s great if you are Cadence with Virtuoso, or Mentor with Calibre. And of course Synopsys with PrimeTime. It is what I call predictable pain. PrimeTime may not be the fastest or highest capacity but it does work. Cadence is betting that if they really can deliver a 10X improvement in design closure productivity then that will be enough to get people to switch. To find out we will just have to…well…give it time.

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Design Data Management – Key Winning Strategy!

Design Data Management – Key Winning Strategy!
by Pawan Fangaria on 05-19-2013 at 9:30 pm
Categories: Dassault Systemes, EDA

In a complex semiconductor market today, characterized by ever increasing design size and complexity, long design cycle, rapid technological advancement, intense competition, pricing pressure, small window of opportunity, development and cross-functional teams spread across the globe and multiple design partners including several IP vendors for a single SoC, it’s essential for a corporate to identify key strategies for its sustainable competitive advantage. Among so much divergence in the ecosystem, there need to be some key elements of convergence to unify the system and provide direction to achieve goals at the right time of opportunity and in cost effective manner. Unified design data management is one such activity which is immensely important for the success of any semiconductor organization because such an organization handles large design data from various sources which gets revised or modified by multiple teams and is reused frequently.

Dassault Systemes group offers ENOVIA Synchronicity DesignSync Data Manager which brings compelling value to any semiconductor organization from technical, commercial and economical perspectives. It manages design data throughout the product life cycle; from specification, development, test and release, and follow on releases thereafter. Although I knew about DesignSync, didn’t realise that it silently works behind the scene and keeps the companies ahead in time-to-market until I read a paper on its ROI impact analysis done by Gantry Group by interviewing a group of ENOVIA’s 18 top customers. I would not go into the details of that study, however a summary of what customers liked about ENOVIA’s DesignSync is in the following table –

These inputs indicate that DesignSync is a critical enabling technology infrastructure for semiconductor and electronics companies to sustain their competitive advantage. As I realised after going through the paper, some of the key advantages of using DesignSync are –

Design Flow Efficiency – By embedding DesignSync into design flows, companies are able to automate the whole process of data management and version control to bring consistency in the design without bothering designers for this mundane but essential work. The design engineering time saved as a result of DesignSync was estimated as –

Design Engineer Productivity – No wonder, design engineer productivity is improved in several ways such as designers’ time spent in producing higher number of gates, increased product throughput, reduced team size, seamless handling of larger number of design configurations and shorter integration cycle. Quantitative figures for these are mentioned in the paper.

Getting back to tape-out configuration – When silicon comes back from the fab, DesignSync enables engineers, spread across multiple sites, to quickly pick up from where they left off in the design, hence saving enormous time-to-market for the company.

Data Set Compares – It’s extremely helpful for an enterprise wide team, distributed across geography to quickly and automatically figure out the design changes between different versions of a design within seconds.

Saving in Disk Space – It provides great relief for designers not to bother keeping multiple local copies of their design work. DesignSync instils confidence among designers for safe handling and retrieving of their design data in a unified manner without any duplication thus consuming only the required disc space. This is a boon for today’s semiconductor business where design data size itself can be in terabytes.

IP Re-use – As DesignSync supports modular design structure, it becomes easy to maintain and re-use IP modules in the designs. Use of IP is a significant strategy for semiconductor organizations.

There are other advantages; notably, ease of collaboration among teams spread across multiple sites, reduced product cost, predictable and optimized project schedules and reduced probability of failures. A reduction in re-spin of mask set (a 65 nm mask set could cost up to $2M) can save millions of dollars.

The paper also records some of very impressive quotes from Dassault’s customers who rightly saw the advantage of using DesignSync; managing consistency in data, handling seamless collaboration in enterprise wide teams, enabling to achieve project deadlines, Hierarchical Configuration Management and so on. Interested audience can take a look at the complete paper at –
ROI Impact Analysis of ENOVIA Synchronicity DesignSync® Data Manager, even try using DesignSync, if not used earlier.

To gain more info – visit Dassault’s booth #1625 at DAC 2013, Austin, TX – June 2 – 6

As a concluding remark, I would like to mention that semiconductor industry is one which continued investment in R&D even at a time of economic slowdown to gain edge in technology innovation. As a result, we are talking about 14nm and 10nm process nodes today. In such a fierce competition and $$ at stake, it’s wise to have a companion like DesignSync which helps eliminating every wastage of time, money and energy to keep the design teams and companies ahead on their goals.

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CEO Interview: Jens Andersen of Invarian

CEO Interview: Jens Andersen of Invarian
by Daniel Nenni on 05-19-2013 at 9:10 pm
Categories: CEO Interviews, EDA

Invarian is an interesting EDA company that sees a niche market opening in the physical verification space. There are a number of converging factors driving this opportunity. Electromigration and voltage-drop for full-chip analysis demands SPICE level accuracy with fast runtimes. Invarian solves that problem with macro modeling and a parallel architecture. Not only are runtimes greatly reduced, but accuracy is improved by incorporating thermal effects within the overall concurrent analysis flow. It seems like everything is going 3D these days, from FinFETs to heterogeneous stacked-die packaging. In a 3D world thermal effects have a major impact on power, performance and reliability. I got a chance to sit down with Invarian’s CEO, Jens Andersen, and delve into this interesting little company. We have been friends for years so I really enjoyed catching up.

What are some specific customer IC design issues your customers are facing?

  • Our industry is facing the proverbial horns of a dilemma, exponential growth in complexity in one hand and shrinking margins of error in the other. The growth in gate-count is not the problem (Moore’s Law has been with us for some time) but rather the constraints on power consumption, electromigration issues, instantaneous voltage-drop analysis and thermal effects. Sign-off has become so burdened with Band-Aid patches over the years. The cumulative effect has been to create a cumbersome and disjointed process. It has created what I call a time dilation effect. There is simply not enough time for getting simulation runs through the pipe. This is the road to ruin, leading one down a path of unpleasant trade-offs, between incomplete analyses or missing the veritable market window.
  • Our customers are demanding new tools, and for a variety of reasons these tools must be built from the ground up, to handle the complexities of cutting edge processes and large design files, but they must also be easy to setup, use and maintain.
  • Current tools sets are inadequate, in the sense that they do not account for the interaction between thermal, power, timing and voltage. A scenario where each leg of the flow works properly, yet the chip fails catastrophically is entirely within the realm of the possible. In fact, it is a very likely result. The Law of Large Numbers has a nasty habit of punishing gamblers, whether in a casino or at a workstation. It would be folly to expect customers to risk $millions on processes that use blindly set constraints for sign-off.
  • Our customers are now able to model with very accurate results due to our concurrent methodology. Not only do we provide the accuracy necessary to ensure proper chip behavior, we do so with advanced techniques that vastly improve runtime. Without incurring risk or impacting the schedule, our overall goal is to tape-out optimum designs. We aim for just enough margins but not more than enough.
  • There is a Catch-22 when it comes to designs at advanced process nodes. It has always been the case that a process is in flux at an early stage of development. This variation keeps growing as a percentage. That is not the problem. The deviation of the actual versus the predicted has major consequences for other reasons. What has changed and why it is a major issue now, when in the past it could be handled, is that chip evolution has reached the stage where interrelated forces can no longer be neglected. Electromigration and leakage current rely on current density values and thermal effects. Power budgets are set early in the design flow with appropriate clock speeds for meeting performance specs. Transient effects and ground bounce are a constant source of potential error. It’s getting harder to tell the signals from the noise.
  • We developed easy-to-use software and leverage the proven strength of industry standard file formats. There is no need to pre-characterize data with predefined corners. That approach leads to average values that are not accurate for transient analysis. Our concurrent engines allow users the ability to know exactly the condition of their design.
  • Fragmented solutions on the market tend to confound the designer and do not model the physically correct design state. With a muddled mess of average estimations there is no choice but to fall back to worst-case scenarios. There is a penalty with this overkill approach to design. Knowledge is power.
  • We have developed algorithms that keep our concurrent analysis engines in sync to provide extremely accurate data. Our results have been correlated with true physical measurements with amazing accuracy.What does Invarian do?
    We have a dual focus:
  • Our primary focus is our InVar Pioneer Platform consisting of multiple simultaneous engines for analyzing Power, EM/IR-drop and Thermal. Our holistic approach achieves the necessary accuracy and our Macro Modeling hierarchy enables our tool to run the largest designs with lightening fast runtimes.
  • Our secondary platform is our InVar Frontier 3D Platform for true 3D thermal analysis. We scale from sub-transistor level to complex stacked-die package environments. Using physical parameters we bring a whole new level of capability for 3D thermal analysis.Invarian is the only provider of physical sign-off tools that offers concurrent analysis of various power integrity parameters as a whole. First time silicon success with the optimum design for performance and accuracy requires tools that accurately model real behavior.Why did Invarian start?
    Our founders have been working in the areas of power, voltage and thermal analysis for many years. They experienced first-hand many cases where designers got faulty silicon solely because of misleading or incomplete sign-off results. From this sprang the idea of delivering a perfectly accurate and physically correct analysis tool. The idea itself is very simple – analysis should reproduce/model physical conditions of real ICs as close as possible. Designers must have a tool that exactly models the behavior of real silicon before manufacturing. Our tool removes uncertainty, and the resulting expensive re-spin cycle, from the design process. The passion that began with our quest of building an analysis solution that reflects physical reality itself continues to resonate and drive us today.

    What is Invarian’s Roadmap?
    We are constantly updating our engines to stay ahead of the competition. One of the great things about being a new entrant in an established industry is being unbound from outmoded legacy. We have been able to build our solution from the ground up to take advantage of the latest methodologies, such as parallel processing. This has allowed us to analyze huge designs (over 150,000,000 cells) in one pass, which has historically been impossible, so our customers are very excited to finally have such powerful capability. We integrate seamlessly with the major implementation flows and SPICE engines. Enabling our customers to perform highly accurate analysis within their existing flow with a powerful GUI and ‘what-if’ capability gives them the peace of mind of knowing precisely their chip’s design behavior. Looking ahead we shall continue to listen to our customers and that is what drives our technology development and roadmap. We have some exciting announcements to make in the near future and look forward to sharing those with you.

    Will you be at Design Automation Conference this year?
    Yes, we will be in the center of the show in booth #1332 and will have suites available for private showing of our new releases; these are very exciting and will benefit any new and older generation process node designs. Please visit www.invarian.com/events.html to sign up for a demo of our solution…

Also Read:

CEO Interview: Jason Xing of ICScape Inc.

Atrenta CEO on RTL Signoff

Sanjiv Kaul is New CEO of Calypto

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Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)

Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)
by Daniel Nenni on 05-19-2013 at 9:01 pm
Categories: EDA, Synopsys

Funny story, @ #49DAC I saw Aart with a very relaxed look on his face looking at the exhibit hall and in my mind he was thinking, “Mine, all mine!” But I digress……. Synopsys is the #1 EDA company for a reason and here is the supporting data for that hypothesis:

Synopsys is committed to accelerating Innovation for its customers—it’s been at the core of the company’s DNA for more than 25 years. The world’s leading semiconductor and electronics companies have relied on Synopsys’ comprehensive portfolio of integrated, system-level implementation, verification, IP, manufacturing and FPGA solutions to design their products. Meet with members of the Synopsys team at DAC to learn more about the newest solutions available to help accelerate innovation.

Visit booth #947 to see Synopsys’ technology exhibits including the HAPS family of FPGA-based prototyping solutions, and the company’s comprehensive functional verification solutions. If you are interested in a specific topic, Synopsys experts will be available for one-on-one meetings during the show.

[TABLE] align=”center” border=”1″ style=”width: 500px”
|-
| colspan=”4″ style=”width: 684px; height: 33px” | SUNDAY, JUNE 2
|-
| style=”width: 223px; height: 19px” | Event
| style=”width: 156px; height: 19px” | Time
| style=”width: 132px; height: 19px” | Location
| style=”width: 174px; height: 19px” | Additional Information
|-
| style=”width: 223px; height: 19px” | Workshop 4
Low-Power Design with the New IEEE 1801-2013 Standard
| style=”width: 156px; height: 19px” | 1:00 p.m. – 5:00 p.m.
| style=”width: 132px; height: 19px” | Austin Convention Center, Room 18C
| style=”width: 174px; height: 19px” | Speaker: Jeffrey Lee, Synopsys
|-
| style=”width: 223px; height: 33px” | MONDAY, JUNE 3
| style=”width: 156px; height: 33px” |
| style=”width: 132px; height: 33px” |
| style=”width: 174px; height: 33px” |
|-
| style=”width: 223px; height: 19px” | Event
| style=”width: 156px; height: 19px” | Time
| style=”width: 132px; height: 19px” | Location
| style=”width: 174px; height: 19px” | Additional Information
|-
| style=”width: 223px; height: 58px” | ARM-TSMC-Synopsys Breakfast
Optimizing Implementation of Performance- and Power-Balanced Processor Cores
| style=”width: 156px; height: 58px” | 7:15 a.m. – 8:45 a.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6th Floor, Grand Ballroom H
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 58px” | AMS Verification Luncheon
Advance Your Mixed-signal Verification Techniques to the Next Level
| style=”width: 156px; height: 58px” | 11:30 a.m. – 1:30 p.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6th Floor, Grand Ballroom G
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 58px” | IC Compiler Luncheon
The Many Faces of Advanced Technology
| style=”width: 156px; height: 58px” | 11:30 a.m. – 1:30 p.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6th Floor, Grand Ballroom H
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 58px” | Pavilion Panel
Affiliation Avenue: The Road to Success
| style=”width: 156px; height: 58px” | 1:30 p.m. – 2:30 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 509
| style=”width: 174px; height: 58px” | Moderator: Sashi Oblisetty, Synopsys
|-
| style=”width: 223px; height: 58px” | GlobalFoundries Theater
Foundry Reference Flow Ecosystem Empowers Designers to Achieve Aggressive Time-to-Market Challenges
| style=”width: 156px; height: 58px” | 1:45 p.m. – 2:00 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 1314 Theater
| style=”width: 174px; height: 58px” |
|-
| style=”width: 223px; height: 58px” | Customer Insight Sessions
Success with Synopsys’ Galaxy Implementation Platform
| style=”width: 156px; height: 58px” | 2:00 p.m. & 3:00 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Level 3, Room 10B
| style=”width: 174px; height: 58px” | Speakers:
2:00 p.m. – Yongjoo Jeon, Samsung
3:00 p.m. – Michael V. Leuzze, LSI
RSVP Required
|-
| style=”width: 223px; height: 58px” | GlobalFoundries Theater
Xceptional IP for GlobalFoundries 14nm-XM Technology
| style=”width: 156px; height: 58px” | 2:00 p.m. – 3:00 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 1314 Theater
| style=”width: 174px; height: 58px” |
|-
| style=”width: 223px; height: 58px” | Samsung Theater
Galaxy Innovations and Collaboration with Samsung for 14-nm FinFET Success
| style=”width: 156px; height: 58px” | 4:30 p.m. – 4:45 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 915 Theater
| style=”width: 174px; height: 58px” |
|-
| style=”width: 223px; height: 55px” | PrimeTime SIG Dinner
Technology Panel – Advanced ECO Methodology
| style=”width: 156px; height: 55px” | 6:00 p.m. – 9:30 p.m.
| style=”width: 132px; height: 55px” | Brazos Hall 204 E 4th St
| style=”width: 174px; height: 55px” | RSVP Required
|-
| colspan=”4″ style=”width: 684px; height: 33px” | TUESDAY, JUNE 4
|-
| style=”width: 223px; height: 19px” | Event
| style=”width: 156px; height: 19px” | Time
| style=”width: 132px; height: 19px” | Location
| style=”width: 174px; height: 19px” | Additional Information
|-
| style=”width: 223px; height: 58px” | Partner Breakfast with GlobalFoundries and Synopsys
Deploying 14XM FinFETs in Your Next Mobile SoC Design
| style=”width: 156px; height: 58px” | 7:15a.m. – 8:45 a.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6th Floor, Grand Ballroom G
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 58px” | Keynote Visionary Talk
Massive Innovation and Collaboration in the
“GigaScale” Age!
| style=”width: 156px; height: 58px” | 9:15 a.m. – 9:30 a.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Ballroom ABC
| style=”width: 174px; height: 58px” | Speaker: Aart de Geus, Synopsys Chairman and co-CEO
|-
| style=”width: 223px; height: 58px” | Customer Insight Sessions
Success with Synopsys’ Galaxy Implementation Platform
| style=”width: 156px; height: 58px” | 10:00 a.m. & 2:00 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Level 3, Room 10B
| style=”width: 174px; height: 58px” | Speakers:
10:00 a.m. – Martin Foltin, HP
2:00 p.m. – Tim Whitfield, ARM
RSVP Required
|-
| style=”width: 223px; height: 55px” | Paper Session 4.1
Double-Patterning Lithography-Aware Analog Placement
| style=”width: 156px; height: 55px” | 10:30 a.m. – 12:00 p.m.
| style=”width: 132px; height: 55px” | Austin Convention Center, Room 13AB
| style=”width: 174px; height: 55px” | Speakers: Tung-Chieh Chen, and
Ta-Yu Kuan, Synopsys
|-
| style=”width: 223px; height: 55px” | DAC Management Day 2013
| style=”width: 156px; height: 55px” | 10:30 a.m. – 6:00 p.m.
| style=”width: 132px; height: 55px” | Austin Convention Center, Room 17AB
| style=”width: 174px; height: 55px” | Organizer: Yervant Zorian, Synopsys
|-
| style=”width: 223px; height: 58px” | Custom Design Luncheon
Addressing Custom Design Challenges with Laker
| style=”width: 156px; height: 58px” | 11:30 a.m. – 1:30 p.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6th Floor, Grand Ballroom G
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 58px” | Verification Luncheon
SoC Leaders Verify with Synopsys
| style=”width: 156px; height: 58px” | 11:45 a.m. – 1:45 p.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6th Floor, Grand Ballroom H
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 58px” | Samsung Theater
Accelerating SoC Designs with Synopsys DesignWare® IP for Samsung Processes
| style=”width: 156px; height: 58px” | 1:30 p.m. – 1:45 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 915 Theater
| style=”width: 174px; height: 58px” |
|-
| style=”width: 223px; height: 78px” | Paper Session 11.3
Automatic Design Rule Correction in the Presence of Multiple Grids and Track Patterns
| style=”width: 156px; height: 78px” | 1:30 p.m. – 3:00 p.m.
| style=”width: 132px; height: 78px” | Austin Convention Center, Room 14
| style=”width: 174px; height: 78px” | Speaker: Nitin D. Salodkar, Synopsys
Authors: Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
|-
| style=”width: 223px; height: 78px” | Paper Session 12.4
An ATE-Assisted DFD Technique for Volume Diagnosis of Scan Chains (Best paper candidate)
| style=”width: 156px; height: 78px” | 1:30 p.m. – 3:00 p.m.
| style=”width: 132px; height: 78px” | Austin Convention Center, Room 15
| style=”width: 174px; height: 78px” | Speaker: Rohit Kapur, Synopsys
|-
| style=”width: 223px; height: 77px” | GlobalFoundries Theater:
Synopsys/GlobalFoundries Collaboration on Interoperable PDK Enablement
| style=”width: 156px; height: 77px” | 4:45 p.m. – 5:00 p.m.
| style=”width: 132px; height: 77px” | Austin Convention Center, Booth 1314 Theater
| style=”width: 174px; height: 77px” |
|-
| style=”width: 223px; height: 58px” | IPL Alliance Dinner
iPDKs: A Thriving PDK Standard
| style=”width: 156px; height: 58px” | 6:00 p.m. – 7:30 p.m.
| style=”width: 132px; height: 58px” | Hilton Hotel, 6[SUP]th[/SUP] Floor, Grand Ballroom G
| style=”width: 174px; height: 58px” | RSVP Required
|-
| style=”width: 223px; height: 65px” | Media/Analyst/Blogger Dinner
| style=”width: 156px; height: 65px” | 6:30 p.m. – 9:30 p.m.
| style=”width: 132px; height: 65px” | Malverde—located above La Condesa, 400 W 2nd Street, Austin, TX
| style=”width: 174px; height: 65px” | NOTE: As space is limited, RSVPs are required by Tuesday, May 28, and are taken on a first-come, first-served basis.
|-
| colspan=”4″ style=”width: 684px; height: 31px” | WEDNESDAY, JUNE 5
|-
| style=”width: 223px; height: 19px” | Event
| style=”width: 156px; height: 19px” | Time
| style=”width: 132px; height: 19px” | Location
| style=”width: 174px; height: 19px” | Additional Information
|-
| style=”width: 223px; height: 58px” | Paper Session 25.1
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
| style=”width: 156px; height: 58px” | 9:00 a.m. – 10:30 a.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Room 14
| style=”width: 174px; height: 58px” | Author: Charles Chiang, Synopsys
|-
| style=”width: 223px; height: 58px” | Samsung Theater
Galaxy Innovations and Collaboration with Samsung for 14-nm FinFET Success
| style=”width: 156px; height: 58px” | 10:30 a.m. – 10:45 a.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 915 Theater
| style=”width: 174px; height: 58px” |
|-
| style=”width: 223px; height: 58px” | Pavilion Panel
IP Pitfalls: Avoid the Wild Ride
| style=”width: 156px; height: 58px” | 10:30 a.m. – 11:15 a.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 509
| style=”width: 174px; height: 58px” | Moderator: Warren Savage, IPextreme
Panelists: John Swanson, Synopsys; Keith Odom, National Instruments; Hans Bouwmeester, Open-Silicon
|-
| style=”width: 223px; height: 58px” | GlobalFoundries Theater
Synopsys/GlobalFoundries Collaboration on Interoperable PDK Enablement
| style=”width: 156px; height: 58px” | 10:45 a.m. – 11:00 a.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Booth 1314 Theater
| style=”width: 174px; height: 58px” |
|-
| style=”width: 223px; height: 58px” | Paper Session 32.4
Spacer-Is-Dielectric-Compliant Detailed Routing for Self-Aligned Double Patterning Lithography (Best paper candidate)
| style=”width: 156px; height: 58px” | 1:30 p.m. – 3:00 p.m.
| style=”width: 132px; height: 58px” | Austin Convention Center, Room 15
| style=”width: 174px; height: 58px” | Moderator: Mehmet Yildiz
Authors: Qiang Ma, Hua Song, James Shiely, Gerard Luk-Pat, Alexander Miloslavsky, Synopsys
|-
| style=”width: 223px; height: 44px” | Technical Panel 34
EDA: Meet Analytics; Analytics: Meet EDA
| style=”width: 156px; height: 44px” | 4:00 p.m. – 5:30 p.m.
| style=”width: 132px; height: 44px” | Austin Convention Center, Room 16AB
| style=”width: 174px; height: 44px” | Moderator: Janick Bergeron, Synopsys
|-
| colspan=”4″ style=”width: 684px; height: 31px” | THURSDAY, JUNE 6
|-
| style=”width: 223px; height: 19px” | Event
| style=”width: 156px; height: 19px” | Time
| style=”width: 132px; height: 19px” | Location
| style=”width: 174px; height: 19px” | Additional Information
|-
| style=”width: 223px; height: 44px” | Technical Panel 47
Analog Design with FinFETs: “The Gods Must be Crazy!”
| style=”width: 156px; height: 44px” | 1:30 p.m. – 2:30 p.m.
| style=”width: 132px; height: 44px” | Austin Convention Center, Room 16AB
| style=”width: 174px; height: 44px” | Panelist: Navraj Nandra, Synopsys
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| style=”width: 223px; height: 44px” | Technical Panel 52.1
Routability-Driven Placement for Hierarchical Mixed-Size Circuit Designs
| style=”width: 156px; height: 44px” | 1:30 p.m. – 3:00 p.m.
| style=”width: 132px; height: 44px” | Austin Convention Center, Room 14
| style=”width: 174px; height: 44px” | Author: Tung-Chieh Chen, Synopsys
|-

Additional Information

Synopsys Main Booth #947
Conversation Central, Synopsys’ online radio show, is back again at DAC 2013 with an exciting line up of guests. Synopsys will host two discussions a day from the main booth—come join us! Each show will also be recorded for later viewing and listening on Synopsys’ YouTube channel, iTunes, and the Conversation Central show notes page.
We invite you to sit and listen to a selection of our past shows while visiting the Synopsys booth at DAC. For more information, visit the show notes page at http://blogs.synopsys.com/conversationcentral/
or follow on Twitter: #snps and #50DAC

Other Booths that Include Synopsys

ARM Connected Village Booth #921
Visit Synopsys to see how our collaboration with ARM® helps address leading-edge challenges for system-on-chip design and software development.

GlobalFoundries Booth #1314
Visit Synopsys at the GlobalFoundries booth to find out more about our collaboration and support for advanced process technology. Synopsys will participate in presentations at the GlobalFoundries Theater on Monday, Tuesday and Wednesday.

Samsung Booth #915 Theater
See how Synopsys and Samsung have accelerated SoC designs and collaborated on 14-nm FinFET technology in the Samsung Theater on Monday and Tuesday.

Si2 Booth #1427
As Si2 celebrates its 25[SUP]th[/SUP] anniversary, Synopsys and other members will showcase how they are applying in their products and solutions the spectrum of standards that have been developed at Si2.

TSMC Booth #1746
Synopsys will present on “Enabling Advanced SoC Designs for TSMC Processes with Synopsys DesignWare® IP” in TSMC’s Open Innovation Platform Theater.

lang: en_US

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BDA Introduces High-Productivity Analog Characterization Environment (ACE)

BDA Introduces High-Productivity Analog Characterization Environment (ACE)
by Daniel Nenni on 05-19-2013 at 7:45 pm
Categories: EDA

Last week Berkeley Design Automation introduced a new Analog Characterization Environment (ACE) – a high-productivity system to ensure analog circuits meet all specifications under all expected operational, environmental, and process conditions prior to tapeout.

While standard cell characterization and memory characterization are well defined application areas with standard flows, dedicated tooling, and rigorous metrics to ensure high quality results, analog circuit characterization is still largely ad hoc and highly dependent on individual designers’ experience. As a result analog circuit results in silicon are predictably unpredictable. Berkeley Design Automation has set out to change that with ACE.

Two Analog Worlds
Understanding the need for ACE requires first understanding the current environment analog designers work within. For leading-edge analog circuit design and verification, there are two separate and distinct worlds today:

Analog World 1 – The High-Performance Analog/Mixed-Signal World: In this world ICs are dominated by precision analog/RF circuitry including: sensors, ADCs, DACs, PLLs, RF, filters, power management, etc., and integrated digital is important and growing. Cadence dominates World 1, and Synopsys is rarely seen. Cadence simulators (Spectre, Spectre Turbo, Spectre RF, APS, APS RF, UltraSim, etc.) have historically dominated World 1, but BDA Analog FastSPICE (AFS) has made significant inroads handling the toughest problems in the last few years. All World 1 simulators use Spectre syntax and models. World 1 lives within Cadence ADE 5.1 or ADE-L/ADE-XL 6.1. World 1 designers wouldn’t dream of manually editing a netlist or doing anything from the command line.

Analog World 2 – The Big-Digital SoC World: With all due respect to digital design teams, SoC performance bottlenecks are all analog: i) high-speed I/O (getting data on and off the chip), ii) PLL/clocking (any slop in the clock is a tax on every digital path), and iii) memory (half the silicon area). Synopsys dominates World 2, and Cadence is rarely seen. Synopsys simulators (HSPICE, HSIM, NanoSim, XA, FineSim) have historically dominated World 2, but again BDA AFS has made significant inroads handling the toughest problems in the last few years. All World 2 simulators use HSPICE syntax and models. World 2 lives at the command-line—manually editing netlists, scripting, and issuing command-line runs. World 2 designers wouldn’t dream of doing anything through Cadence ADE.

BDA uniquely competes very effectively in both of these worlds, giving it a unique viewpoint on the market. Moreover, increasingly World 1 is meeting World 2 on the same project, making analog characterization an even bigger challenge.

The Growing Need for Analog Characterization
Analog designers’ simulation tasks may be classified as performance verification (hereafter simply “verification”) followed by characterization. As used here, verification is what designers do to make sure their circuit meets specifications under nominal conditions and under a few conditions that the designer expects may break it – perhaps a few PVT corners, a few extreme operating conditions, and maybe a bit of Monte Carlo for mismatch. Everything looks good. Verification is done. The circuit is probably good to go, and the designer would like to move on to the next interesting problem.

Not so fast. There are many possible process, voltage, and temperature corners in nanometer silicon technologies. There are many possible operating conditions (e.g., signal levels, calibration setups, operating modes, and noise sources). There is also a lot of global and local process variation. The process corners in the PDK do not correspond to any analog circuit’s 3-sigma points. In fact, often they are not even close. Global process variation affects every circuit and every measurement (e.g., frequency, gain, duty cycle, jitter, SNDR, etc.) in every circuit differently. Key design components (e.g., inductors, varactors, etc) also have critical variation. What combination of these different environmental, operational, and process conditions (a.k.a., “variants”) result in a blown spec in silicon is anyone’s guess—especially since today’s circuits are almost all highly nonlinear. This is a combinatorial problem with typically 100s or 1000s of known important variants. The objective of analog characterization is to ensure an analog/mixed-signal/RF circuit meets all specs under all these variants.

Characterization is not fun. It’s tedious, it’s boring, it’s error-prone, it takes a long time…and there haven’t been any good tools to help. As a result, analog designers cut corners—a lot of corners (and sweeps and Monte Carlo runs). Although designers know they should do a lot more characterization, it is too painful and takes too long. So they don’t. Instead they make sure their circuits have plenty of margin (no one’s measuring over-design anyway) and hope that they don’t miss a scenario that causes a silicon problem.

Characterization in the Two Analog Worlds
In World 1 designers live within ADE. By all accounts ADE is pretty good for verification setup and analysis, but it is not so good for characterization. All Cadence customers are migrating to ADE 6.1, in which most characterization capabilities are in ADE-XL. Many designers find ADE-XL so cumbersome that they are actually performing less characterization than before. For example, setting up a corner is completely different than setting up a sweep and both are completely different than setting up a Monte Carlo. Non-trivial combinations of corners, sweeps, and Monte Carlo require OCEAN scripting for setup and post-processing. After a characterization run, designers find it impractical to effectively mine their own data, let alone look at results across a project.

In World 2 designers hand-edit netlists and write scripts. Many of the simulators, including HSPICE, have very limited support for combinations of corners, sweeps, and Monte Carlo making it very difficult to setup some of the most obvious combinations (e.g., a temperature sweep under a voltage sweep). In this world every designer does things differently, so it’s impractical to mine characterization data in any consistent way.

ACE and Beyond
Analog characterization is not rocket science. It requires straightforward tool design and engineering—analytics for analog. It didn’t exist, so BDA developed the Analog Characterization Environment. ACE is an environment where basic units like tests, measurements, and variants (i.e., corners, sweeps, and Monte Carlo runs) are characterization building blocks that are easy to create, easy to combine, and easy to reuse. ACE makes it easy to specify the experiments you want to run. ACE makes it easy to view the results and analyze the data. ACE makes it easy to create regressions. ACE makes it easy for designers, CAD engineers, and third parties to access, use, and add to the characterization data.

ACE makes systematic analog characterization practical, but it is only the first step. BDA created ACE with true openness in mind. ACE stores all characterization data in an Open Verification Database (OVD) that is quite literally open to all. All OVD data is in standard formats wherever applicable and where standard formats don’t exist, the data is in XML if intended for tools or text if intended for designers. OVD provides a foundation for CAD engineers, designers, and third-parties to integrate analog characterization into the rest of their IC design process from top-down specification and digital verification to configuration management, variation analysis, and circuit optimization tools (e.g., Cadence, MunEDA, and Solido). BDA is already working on a number of extensions and encourages customers and third-parties to do likewise.

Visit BDA at #50DAC and see Analog Characterization Environment!

lang: en_US

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Oasys Announces Floorplan Compiler

Oasys Announces Floorplan Compiler
by Paul McLellan on 05-19-2013 at 5:58 pm
Categories: EDA

Today Oasys announced the availability of Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. This is actually a repackaging of a capability that has always been in RealTime Designer, and in fact has been an important aspect of how well RealTime Designer has performed in benchmarks over the last four years. Until now, though, it has not been available as a separate tool.

However, now the design team can create a floorplan directly from the RTL that is aware of the design’s dataflow and also meets all the constraints for timing, power, area and routing congestion. The resulting floorplan can then be fed forward as initial guidance to the physical design teams.

Floorplan Compiler takes into account regions, fences, blockages and other physical guidance. The advanced editing tools make it easy to take an initially created floorplan from Oasys, make changes and then iterate getting better versions multiple times per day. One of the most time consuming tasks in SoC/ASIC design is getting a good quality floorplan. Oasys floorplan compiler reduces the time required for this task from a typical 4-6 weeks down to a few days.

The underlying approach of the RealTime synthesis engine is that it optimizes at the RTL level using a placement first methodology. No timing is undertaken without the cells being placed, since in a modern process most of the timing is related to placement and routing and not just the basic cell timing. When timing constraints are not met, then instead of just running gate-level optimizations, the algorithms return to the RTL level and re-sythesize a local area of the design using the improved knowledge. A sort of rip-up and re-synthesize. This approach results in huge capacity (the whole gate-level netlist does not need to be processed at once) and incredibly short run-times (gate level optimization is very expensive and avoiding it saves most of the time taken by traditional synthesis). For floorplanning, this infrastructure makes it straightforward to optimize RTL partitions (and change them iteratively) and automatically place macros, pins and pads to create a high quality floorplan driven by the constraints provided.

The input to Oasys RealTime Floorplan Compiler are the standard synthesis inputs (RTL, constraints, libraries) and the output is a standard floorplan DEF file which can either be fed into traditional synthesis tools or into place & route tools as an initial floorplan. So Floorplan Compiler drops seamlessly into existing flows.

More details on Floorplan Compiler are available here.

Oasys will be demonstrating Floorplan Compiler at DAC at booth 1231.

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Dassault DAC Assault

Dassault DAC Assault
by Paul McLellan on 05-19-2013 at 3:25 pm
Categories: Dassault Systemes, EDA

Dassault Systèmes is not a company entirely new to DAC, but with the acquisition of Matrix One (which had already acquired DesignSync) a few years ago and Tuscany Design Automation’s PinPoint last year they now have a richer portfolio to support various aspects of electronic design. By the way, Dassault is a French company so if you want to be correct you should pronounce it the French way, meaning the “lt” at the end is silent. So it is Dass-o not Dass-oat. Systèmes is pronounced slightly differently in French (that accent does mean something and the “es” at the end is silent) but I’ll let you off on that one. Even DS themselves drop the accent most of the time. Spot tests will be taking place on the DAC exhibit floor 😉

DS’s solutions do not directly perform design, rather they keep track of all the various views, ensure that requirements are captured and track if they are met, keep views synchronized, keep track of timing closure progress and so on. In some segments this is known as Product Lifecycle Management or PLM although in the IC design world I’ve never heard anyone use that term.

But DS remains a little bit of a well-kept secret in the industry. So come and visit booth #1625 to find out about innovative solutions to these growing challenges:

  • The latest in design collaboration with DesignSync for semiconductor design data management and Pinpoint for design intelligence
  • How simulation lifecycle management can ensure that product requirements are met throughout the entire design and development chain
  • An innovative development environment that ties together product, design, and manufacturing engineering and allows visibility from new product introduction through product delivery
  • A comprehensive IP Management solution, providing a single source of truth and targeting all aspects of IP governance

DS’s Pinpoint technology (the Tuscany product) provides a level of design intelligence that has been missing from semiconductor design flows:

  • Instant access to latest design data, including timing, power, layout, log files, reports, and more, without having to invoke physical design tools
  • An intuitive web enabled common platform for collaboration across sites and between RTL and physical designers
  • Full chip simultaneous visualizations of relevant timing, power, congestion, cell views, and physical layout

ENOVIA DesignSync and IP Management solutions provide a scalable and comprehensive IP management environment with role based use models and protection:

  • Single solution to manage internal and external IP
  • Links to design, process, industry schema, shared processes
  • Covers portfolio, part, document, supplier and knowledge management
  • Single source of truth for all IP parametric, license, warranty, compliance, technology and application information

Finally, DS’s Simulation Lifecycle Management solution drives product quality and performance for new products designed for market leadership:

  • Bridges the gap between product requirements, design and product verification and validation processes and disciplines
  • Improves team visibility, communication, and collaboration using a central repository and tool to manage product requirements
  • Provides a platform and infrastructure for a comprehensive V&V flow that allows for clear and accurate measurement and metrics reporting

Dassault Systèmes are at booth 1625 at DAC in Austin, first week of June.

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Supporting the Customer Is Everyone’s Job

Supporting the Customer Is Everyone’s Job
by Amit Varde on 05-19-2013 at 10:40 am
Categories: Cliosoft, EDA

EDA software is quite different from off-the-shelf software. In most cases, customer requirements are unique and depend on the proprietary and complex design process, environments and standards developed and/or evolved by semiconductor design teams over a number of years. EDA software ends up being heavily customized to conform to the customer’s standards and design flow.

With each customer design flow presenting unique challenges, EDA vendors must not only provide the software tools but also back them up with high quality and high touch support and services. This makes the Application Support Team a critical component for the success for the EDA vendor.

Support teams require extensive domain knowledge of various design environments and the skills to customize intricate requirements. They will sometimes need to pull in the development team to solve complex issues and provide solutions that users demand. One way to achieve top-level customer service is to build a culture where “supporting the customer” is a top priority in the company at all levels of management and engineering hierarchy. A side effect of this culture is that engineering managers and developers get to see how their software is actually used and deployed by the design teams, and get a much better understanding of the end user environment where tools are used. This helps the entire organization improve the quality of software and accomplish customer satisfaction.

Investing time and effort in support protocols is very consequential to the success of any EDA product.

  • A support website should be a one-stop-shop to answer a user’s technical questions. It should therefore be able to provide technical resources like release notes, downloads, constantly-updated FAQs, articles on customization, user discussion forums, demo videos and training in an easy-to-navigate portal. The more focused the resources, the less time that users and support teams spend on issues. Allowing users to subscribe to RSS feeds FAQs, release notes, etc. helps keep the user base active and informed of product features and developments.
  • The support portal should be integrated with a good ticketing system with active participation from customers, support engineers and development teams. Users should also be able to look at issues that their peers in the organization may have faced. This avoids unnecessary duplication and improved knowledge sharing within the organization, helping to provide faster resolution to issues and, in many cases, also helping them to optimize their design environments. Allowing tool developers to have easy access to the ticketing system and encouraging them to participate helps identify software deficiencies more quickly and to plan for new enhancements. It also allows support groups to plan tailored training session for customers.
  • “On demand collaboration” via phone and screen sharing tools is critical to resolving customer issues efficiently. Often, with critical issues, screen sharing allows support teams to be virtually onsite immediately and to quickly bring in other experts or even members of tool development team to resolve issues, if necessary.

Excellent technical support is a true win-win situation for the EDA vendor and their customers.
The simple key to becoming famous for customer service and support is a company-wide commitment to making customer needs a top priority. For ClioSoft, the result has been customer feedback such as this: http://www.cliosoft.com/support/index.php

Supporting the customer is really everyone’s job.

See Cliosoft at DAC:
http://www.cliosoft.com/dac/

Also Read

Cliosoft CEO on Design Collaboration Challenges!

Agilent ADS Integrated with ClioSoft

Data Management for Designers

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CEO Interview: Jason Xing of ICScape Inc.

CEO Interview: Jason Xing of ICScape Inc.
by Randy Smith on 05-19-2013 at 12:00 am
Categories: CEO Interviews, EDA

I recently had the opportunity to interview Jason Xing, Ph.D., CEO and President of ICScape, Inc. Below is a subset of the nearly two hour long interview.

How did you first become involved in EDA?
My EDA career started in the mid-90s when I started working on my PhD thesis at the University of Illinois in Urbana-Champaign. My thesis topic was on parallel algorithms for standard cell based placement. After graduation in 1997, I joined Sun Labs doing research on new physical design methodologies using concurrent logical and physical design. At that time, physical synthesis was becoming a critical need for high performance VLSI designs.

How did you end up at ICScape? How do you feel about the evolution of your role with ICScape?
After several years of research at Sun Labs, in 2001 I joined Sun’s internal physical design development team to lead the geometrical database design and router development, where I met Dr. Steve Yang. We talked often on the physical design issues and EDA tool limitations. We decided to start a company to develop effective tools for physical design. In 2004, I quit Sun, and started working on setting up ICScape Inc. In the early years of ICScape, I was the CTO and VP of Engineering in charge of the product architecture and development. After the products, TimingExplorer™ and ClockExplorer™ were developed and achieved good market traction, the board of directors requested me to take on the role of CEO and run ICScape. I saw this as a great opportunity and a challenge. It has opened a new chapter in my career.

What are the specific design challenges your customers are facing?
For large SoC designs, it takes too long and there are too many iteration to close timing due the fact that timing sign off and implementation tools are using different timing engines, creating a major correlation issue. Timing closure typically involves up to hundreds of corners and modes, and requires setup, hold, max. transition, and max. capacitance violations to be addressed. In today’s designs, thousands of timing violations are found by the sign off STA (static timing analysis) engine. Fixing them using STA’s timing engine or with the users’ custom scripts means that the placement and routing constraints and requirements are not taken into account at all. This is the reason for too many iterations. On the other hand, it is difficult for current P&R tools to address timing closure because they can handle only a few modes and corners at a time. In addition, their lack of timing correlation with signoff STA is a major hurdle against closure.

What are your plans for DAC this year? What is your goal for DAC?
Continue to promote our SoC design closure products, which include our flagship product TimingExplorer. This tool solves placement and routing aware timing ECOs, and is capable of handling all multi-corner, multui-mode (MCMM) scenarios together. Since the introduction of the company and its products at DAC last year, some of our products have received a high level of interest from potential customers. We have closed several high profile accounts and are in active evaluation with other companies. We want to continue the momentum and increase the customer base.

How does your company help with your customers’ design challenges?
Timing closure is a major issue for customers. TimingExplorer fully addresses the two major limitations of current tools and methods: 1) lack of timing correlation between STA and P&R tools and 2) an inability to simultaneously handle all MCMM timing scenarios. This is done by directly mapping timing graphs from the sign-off STA engine on to the built-in timing engine and leveraging a built-in P&R engine, capable of simultaneously handling all MCMM timing scenarios to generate ECO directives for the sign-off STA as well as the user’s P&R engine.
The results are better and faster timing closure using typically 2-4 iterations and cutting ECO time by 50%.

What are the tool flows your customers are using?
Major P&R and timing signoff flow. P&R flow include ICC and SoC Encounter EDI. Timing signoff flow tools include PrimeTime and ETS.

ICScape is currently aiding customers in timing closure and in the creation of clock tree synthesisconstraints, what adjacent areas do you think might make sense for ICScape to enter in the future?
We could and would like to do more in chip finishing and low power physical design solutions including low power clock trees, and dynamic and leakage power reduction.

To visit with ICScape at DAC, click here.

Also Read:

Atrenta CEO on RTL Signoff

Sanjiv Kaul is New CEO of Calypto

CEO Interview: Jens Andersen of Invarian

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#50DAC: Winning in Monte Carlo!

#50DAC: Winning in Monte Carlo!
by Daniel Nenni on 05-18-2013 at 4:00 pm
Categories: EDA, Solido

One of the places you will be able to find me at the Design Automation Conference (DAC) is on the speaker panel for a Monday Tutorial – Winning in Monte Carlo: Managing Simulations Under Variability and Reliability. Having worked closely with TSMC, GLOBALFOUNDRIES, Solido Design Automation, and some of the top fabless semiconductor companies, I have first hand experience with the increased variation at advanced process nodes and the increased SPICE simulation burden that results. Variation analysis and design software is absolutely being used by semiconductor companies and foundries to cut down on these SPICE simulations by intelligently figuring out what to simulate. This tutorial will give practical insight into causes of and solutions for variability and reliability. I highly recommend it.

Thanks to FinFETs and other process innovations, we are still shrinking devices. But it comes at a steep price: variability and reliability have become far worse, so effective design and verification is causing an explosion in simulations. First, Dan Nenni will do the introductions and present process variation content and analytics from SemiWiki.com. Presenter Prof. Georges Gielen from KU Leuven University will describe CAD and circuit techniques for variability and reliability. Next Yu Cao from Arizona State University will describe how at 20nm and new features from FinFETs, double patterning, interconnects, and other process innovations will require deep knowledge of variability and its relation to performance. More corners and statistical spreads will come into play, so advanced IC design tools will be needed to minimize design cycle times. Then, Trent McConaghy CTO of Solido Design Automation, will describe industrial techniques for fast PVT, 3-sigma, and high-sigma verification. Finally, Ting Ku, Director of Engineering at Nvidia, will describe a signal integrity case study using variation-aware design techniques.

Here is a preview of my intro slides:

Sources of Variation @ 28nm
•Random dopant fluctuation, RDF (from device Vt adjust implant)
•Metal line thickness variation (from variations in layout density, from the CMP polishing process)
•Via resistance variation (due to variation in barrier metal thickness filling the damascene trench + via)
•Gate line edge roughness, LER (localized gate channel variation)

Additional Sources of Variation @ 20nm
•Double patterning A/B mask misalignment, resulting in extraction variation between adjacent lines
•Much stronger focus on “preferred orientation” segments — “wrong-way” segments have a much greater litho variation, due to source-mask optimization litho data correction
•Introduction of “local MEOL interconnect” for active + gate contacts introduces new source of width/thickness metal variation — the MEOL is a large contributor to the gate-to-source and gate-to-drain coupling capacitances

Additional Sources of Variation @ 16nm
•FinFET-related variations… fin height tolerances, fin thickness tolerances, fin profile variation
•Relative magnitude of gate LER is larger
Fin sidewall roughness is a new phenomenon

Additional Sources of Variation @ 10nm?
•Triple- or quad-patterning –> mask mis-registration goes up… greater extraction variation
•Very restrictive layout design rules — e.g., NO wrong-way segments on lower metal layers… as a result, some variation could be mitigated?
•Metal line and via resistance tolerances go up… narrower metals imply a greater % of the damascene volume will be the barrier layers… greater % variation?
•Metal gate “grain boundary effects” (MGG) more prevalent… the grain size of the metal gate material is approaching Lgate… higher % variation in Rgate?
•New metal gate workfunction interfaces for device Vt’s…?

You can sign-up for the DAC tutorial here: http://www.dac.com/dac+2013+registration.aspx, or sign-up for a Solido software demo here: http://www.solidodesign.com/page/dac-2013-demo-signup/

lang: en_US