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Mastering the Magic of Multi-Patterning

Mastering the Magic of Multi-Patterning
by Daniel Payne on 01-03-2014 at 7:03 pm

I’ve been quite impressed that modern ICs use a lithography process with 193nm light sources to resolve final feature sizes at 20nm and smaller dimensions. We’ve been blogging about Double Patterning Technology (DPT) some 45 times in the past few years that enable 20nm fabrication, so one big question for me is, “How does this effect my design and verification flow?”

David Abercrombie of Mentor Graphics authored a 12 page white paper, “Mastering the Magic of Multi-Patterning” and it answers that question about the impact on design and verification flows with multi-patterning.


David Abercrombie
Continue reading “Mastering the Magic of Multi-Patterning”


NoC, NoC: Your Chip May Be Under Attack

NoC, NoC: Your Chip May Be Under Attack
by Paul McLellan on 01-03-2014 at 12:37 pm

SoCs face a lot of issues related to security and the Network-on-Chip (NoC) is in a good position to facilitate system-wide services. SoCs are now so complex that one of the challenges is to make sure that the chip does what it is meant to do and doesn’t do what it isn’t meant to do. Just as in software, security used to be largely ignored when doing a chip design but with all the latest revelations about the NSA (and others) you can’t just assume your blocks have no security holes and that it impossible to run malicious code on your control processor.

Chips are vulnerable to attack in all sorts of subtle ways as well as the obvious ones of violating security policies such as writing out encryption keys to non-secure areas. Just as a website is vulnerable to DDOS attack (distributed denial of service) IP blocks on a chip are vulnerable to starvation, forced errors and unauthorized access.

Sonics has a broad set of security features in its products SSX and SGN that can be used in conjunction with error management to enable content protection, core hijacking prevention, and denial of service protection and thus ensure that an SoC cannot be compromised.

The protection mechanism allows for access restrictions to user-specified targets using flexible, user-defined protection regions. The initiator access can be additionally qualified with the use of in-band qualifiers. Incoming requests at the target are qualified using the address, the user bits, the initiator id and the type of command to decide whether to grant or refuse the request. Two tests are done: is the incoming request type (read, write, both) permitted by the permissions and are the role bits of the incoming request in the pattern allowed by the user-defined network permission bits.

The access rights are stored in a table of run-time configurable registers—these registers reside in a protected region. The request address and protection group are used to look up read, write, and role permissions from a table of protection regions.


In a little more detail, access control at the target agent is based on the following attributes of each request:

  • The address is used to determine the protection region. Because the initiator agent can do address fill-in and/or multi-channel operations, the address received by a target agent may not be the same as the address sent by the initiator.
  • Initiator ID is used to determine protection groups.
  • Command is used to determine if a read or write is requested (the ReadEx command is evaluated as both a read and a write).
  • Separate portions of user defined signals can be used to determine the protection group and the role associated with the request.


Another important aspect of security is to track issues and capture error conditions. Of course there are lots of reasons for errors on an SoC and security is not necessarily the most likely. As Hanson’s razor says, “Never attribute to malice that which can just be explained by stupidity.” Well, OK, chip designers are not stupid but the most likely reason for sending, say, an unsupported command is an error. But it might not be so capturing errors is a very important part of security.

The combination of the protection mechanism along with error management helps address many SoC security vulnerabilities such as information extraction, core hijacking (running malicious code) and DoS attacks.

More information here.


Somebody at the NSA has a sense of humor

Somebody at the NSA has a sense of humor
by Don Dingee on 01-02-2014 at 6:30 pm

We have to go way back in the annals of entertainment history to find the origin of the word “Jeep”, not just a term of endearment hung on a WWII utility vehicle. Pictured is Eugene the Jeep, a mystical creature belonging to the 4th Dimension, who first appeared to torment Popeye the Sailor in 1936.
Continue reading “Somebody at the NSA has a sense of humor”


SEMI Industry Strategy Symposium

SEMI Industry Strategy Symposium
by Daniel Nenni on 01-02-2014 at 3:00 pm

The SEMI Industry Strategy Symposium (ISS) is Jan 13th-15th at the Ritz-Carlton in Half Moon Bay. When I discussed this with my beautiful wife as a possible business trip for us and mentioned the agenda she stopped me and said, “You had me at Ritz-Carlton!” As you can see by the picture it has a beautiful ocean view and includes a world class spa.

Will the combination of the unprecedented threat to Moore’s Law coupled with pressures of consumer products pricing and short life cycles stifle the industry or will the rapidly expanding mobile markets and pervasive computing trump the challenges and provide a new growth engine for the industry? How will chipmakers, equipment companies and materials suppliers be impacted and what strategies should they be contemplating now to deal with the new realities?

The mobile SoC market sure has changed the fabless semiconductor ecosystem. With wearable computing coming at us full force more change is coming, absolutely.

From business and economic trends to new and emerging markets, you’ll hear it all at the conference that has been delivering to the semiconductor industry for more than three decades—the SEMI Industry Strategy Symposium (ISS).

Paul McLellan will also be there so this will be a fully covered SemiWiki event. Engaging with semiconductor experts from around the world is not just our job, it is our privilege.

ISS 2014 hosts a hard-hitting lineup of executives and analysts offering valuable insights for companies up and down the supply chain. You’ll benefit from an array of information channels from company presentations and executive panels to the networking opportunities before, during and after the conference. The Industry Strategy Symposium, the only forum where senior executive suppliers and device manufacturers receive a first-hand view of what the industry will look like in the year ahead, and gain strategic insights into the shifting business environment. Take a look at the rich agenda and make plans now to attend.

FULL AGENDA IS HERE

Opening Keynote:
The Road Not Taken
Rick Wallace
President and CEO
KLA-Tencor

ISS Banquet Keynote:
Young Sohn
President and Chief Strategist
Samsung Electronics

Closing Keynote:
Manish Bhatia
Senior Vice President, WW Operations
SanDisk
Sessions
Day 1: Opportunities

  • Opening Keynote
  • Session 1: Economic Trends
  • Session 2: Market Perspective

Day 2: Challenges

  • Session 3: Technology Challenges
  • Session 4: Opportunities at the Edge

Day 3: Outcome and Strategies

  • Closing Keynote
  • CEO Panel

REGISTER HERE

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. Our 1,900 member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been committed to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.

lang: en_US

More Articles by Daniel Nenni…..


SemiWiki 2013 in Review!

SemiWiki 2013 in Review!
by Daniel Nenni on 01-01-2014 at 9:30 am

This certainly was an interesting year. The fabless semiconductor ecosystem definitely got stronger and I see nothing but clear skies in 2014. Judging by the SemiWiki 2013 analytics and key search terms we all have an interesting year ahead of us with even more opportunities to grow and innovate. 2013 was also a year of growth and innovation for SemiWiki and 2014 will include more of the same, definitely.

You may have noticed the new Jobs Forum on SemiWiki. A seasoned and well respected Corporate Recruiter will be joining us to help our subscribing companies fill those job openings in a professional and efficient manner, for the greater good of the semiconductor ecosystem. More details to follow…..

I post SemiWiki analytics on a semi regular basis to keep track of our progress and illustrate the power of New Media in the fabless semiconductor ecosystem. Using the EETimes website as the gold standard here is where we are today:

EETimes
2012 Rank: 24,870
2013 Rank: 28,584

2014 Rank: 32,223

SemiWiki
2012 Rank: 431,594
2013 Rank: 249,989

2014 Rank: 187,171

As you can see EETimes had another double digit decrease on their Alexa ranking while SemiWiki had another strong growth year. From our launch on January 1[SUP]st[/SUP], 2011 to December 31[SUP]st[/SUP] 2013 829,480 people have visited SemiWiki. Next year it will be more than one million, absolutely. Hopefully we can get our Alexa rating in the 5 digits.

EETimes
Bounce Rate: 65.30%
Daily Pageviews per Visitor: 1.89
Daily Time on Site: 2:17

SemiWiki
Bounce Rate: 33.10%
Daily Pageviews per Visitor: 5.90
Daily Time on Site: 9:34

Even more troubling for EETimes: the bounce rate (people who leave the site immediately), page views per visit, and time on site. Traditional media is facing a serious challenge. In my opinion EETimes should go back to releasing a weekly paper version. I really enjoyed reading Richard Goering and Mike Santorini during my bathroom breaks at work.

Demographics:

[LIST=1]

  • United States 45.99%
  • India 11.78%
  • Taiwan 4.28%
  • Germany 4.07%
  • United Kingdom 3.66%
  • France 3.20%
  • China 2.51%
  • Canada 2.41%
  • Japan 1.98%
  • South Korea 1.75%

    Devices:

    Desktop 82%
    Mobile 18%

    • Apple 61%
    • Samsung 29%
    • Google 4%
    • Other 6%

    Sources:

    [LIST=1]

  • Direct 32%
  • Search 31%
  • Referral 27%

    Total 2013 Blogs: 835

    Top Blogger:
    Paul McLellan 279 blogs

    Top Blog:
    High-Sigma Standard Cell Optimization!

    Top Market Segment:
    Design IP

    Top Search Term:
    FinFET

    New Media is here to stay and SemiWiki is just getting started. We currently have more than 40 subscribing companies working with us covering EDA, Design IP, Semiconductor Services, FPGAs, and Semiconductor manufacturers. SemiWiki added two more bloggers this year. By bloggers I mean semiconductor professionals with firsthand knowledge of what we write about. People, like myself, who work inside the fabless semiconductor ecosystem during the day and write at night because we are passionate about what we have accomplished in this industry.

    Probably the most exciting new thing you will see on SemiWiki in 2104 is a section on books as we get into publishing. The first book of course is “Fabless: The Transformation on the Semiconductor Industry” which will be released on January 15[SUP]th[/SUP], 2014.

    If you have other analytic questions post them in the comment section. New Media is all about transparency, right?

    Happy New Year to you all and thank you for making SemiWiki the success it is today!

    lang: en_US

    More Articles by Daniel Nenni…..


  • 2013 Awards, and the Winner is…Power

    2013 Awards, and the Winner is…Power
    by Paul McLellan on 01-01-2014 at 8:00 am

    Of all the things that designers have to worry about in the power-performance-area (PPA) equation, the most challenging is power. SoCs have reached a point that we can put a lot of stuff on them, but if we are not careful we cannot light it all up at once. Dark silicon, where we put subsystems on a chip but then don’t have enough power budget to turn them on, is a real issue.

    So as a sort of year-end review, here are lots of the approaches designers take to reduce power:

    • low power processes. For planar processes, leakage power has become a real problem and foundries like TSMC and GF have specia low-power variants of their processes with less performance but less power, typically optimized for the mobile market. With FinFET processes, leakage is less of an issue (one of the big reasons for going to FinFET in the first place) and the transistor architecture is less flexible so it looks like they will come in only one flavor
    • multiple V[SUB]t[/SUB] libraries. Synthesis tools will automatically use the low power cells except one critical paths that can’t meet timing without using the higher power (and higher leakage) cells
    • clock gating. All synthesis tools can replace multiplexors for recirculating data values in a register with a clock gate cell that simply inhibits clocking the register
    • automatic sequential power reduction at RTL level. Several EDA companies have tools that will rework the RTL, especially for datapaths, to reduce power by not clocking registers where the results will not be used and so on
    • turn the clock off. the simplest way to reduce dynamic power on a functional block when it is not required is simply to stop clocking it. But care needs to be taken with the power delivery network when turning a block back on since the sudden increase in power can cause voltage droop and transients
    • power down the block. the challenge here is to make sure that all outputs are tied off properly so that there is not a lot of crowbar current by gates drifting between 0 and 1. And if there is data in the block that needs to be preserved, then special retention registers must be used. Even more so than in the clock case, a lot of care needs to be taken when powering up the block or the inrush current can cause problems all over the chip. Typically the block is powered up with relatively small transistors (so it takes time) and the big transistors are only turned on once the block is already up to normal voltage
    • dynamic voltage and frequency scaling (DVFS). vary the frequency of the clock to a subsystem (typically a microprocessor). But this needs to be done with care. First the frequency must be lowered and then the voltage can be. And when getting back up to full speed, first the voltage must be increased and then the frequency can be changed
    • race to halt. sometimes running the microprocessor as fast as possible is the way to go. once it is idle again then the rest of the system can be powered down. running the microprocessor slowly may save power in the processor itself but if it means a lot of other blocks have to be powered up for a long time that might be the wrong tradeoff
    • make sure that the embedded software turns off whatever can be turned off. It is sometimes the case that the embedded s/w engineers don’t really understand IC power issues, and the IC designers don’t understand embedded s/w and a a lot of power is wasted in the gap. Virtual platforms can play a role here.
    • Unique approaches: ARM big.LITTLE, NoCs that can wait for blocks to power up, Cyclos resonant clocks, asynchronous signalling

    More articles by Paul McLellan…


    ClioSoft at Arasan

    ClioSoft at Arasan
    by Paul McLellan on 01-01-2014 at 8:00 am

    Arasan recently adopted ClioSoft for data management (DM) for design and development of Arasan’s Silicon IP products. This morning I talked to Erik Peterson, Senior CAD and Verification Engineer AMS Design about their experiences bringing up ClioSoft.

    Data management infrastructure is critical with engineering projects shared across different continents. Arasan’s development is distributed between the headquarters in San Jose and engineering sites in India. Currently the San Jose site and the Indian sites are up on ClioSoft with plans to bring the rest of the organization over to the new DM tools soon.. Arasan uses Cadence’s Virtuoso environment which ClioSoft’s SOS data management solution is tightly integrated with, making it painless to keep track of changes and versions.

    The evaluation was done using two projects. When the decision was made to purchase the product the installation was straightforward. There is always some customization required to match a new tool to our methodology. ClioSoft was very responsive in anticipating our issues and provided exemplary customer service.

    Before ClioSoft, Arasan’s DM required a lot more manual labor. But ClioSoft just works effectively and largely invisibly. The ideal infrastructure product works in the background and does not impact your development – unless something goes wrong – then you need prompt notification. It is not news when the trains run on time.

    Another key advantage over a manual solution is the institutionalized learning that comes with a system that makes it easy to see what has been changed and inspect the reason. They can see what changes were made and what notes the engineer put in, and so this lets knowledge get reused more easily on other projects.

    I asked Erik to summarize what they like about ClioSoft and their products:

    • Close working relationship with customers
    • Ability to solve an issue and reuse for separate project
    • Database security, tracking, release control
    • User learning curve, things “just work”
    • ClioSoft’s outstanding customer service
    • ClioSoft and EDA Direct’s flexibilty during eval
    • Nimble and quick start, very short notice was not a problem

    Also Read

    Data Management in Russia

    Managing Multi-site Design at LBNL

    Analog ECOs and Design Reviews: How to Do Them Better


    Quick MEMS Development Through Virtual Fabrication

    Quick MEMS Development Through Virtual Fabrication
    by Pawan Fangaria on 01-01-2014 at 7:00 am

    The design and manufacture of MEMS is very different and in many ways more complex process than even the most advanced ICs. MEMS involve multiple degrees of freedom (i.e. the device to exhibit different characteristics under different physical state, motion or mechanics), making fabrication of MEMS extremely complex; and hence the processes are highly customized and typically linked to particular design or device. The process flow and design parameters are highly sensitive to each other, thus requiring multiple build-and-test cycles and longer MEMS process learning cycles. And these days most of electronic devices or semiconductor designs involve MEMS integrated into them, necessitating a MEMS+IC design approach. For example, gyroscopes are being used in smartphones in big way to enhance motion detection and orientation. Given the cut-throat competition in the mobile market, with increasing feature sets and shrinking windows of opportunity, it’s critical that process learning cycles for MEMS development move from time-consuming build-and-test methods to more efficient methodologies to streamline the handoff from design to manufacturing.

    The good news is that Coventor’sSEMulator3D tool (about which I had earlier talked in the context of Virtual Fabrication Platform for semiconductor design ICs) is providing an excellent platform for virtual modeling of MEMSas well. Physical data (such as capacitance) can be extracted from the model for quantitative analysis and process variation studied to quickly predict the exact model of interest before actual fabrication, thus reducing the learning cycle for MEMS technology.


    [SEMulator3D Virtual Fabrication Platform]

    SEMulator3D takes the design layout data and unit process behavioral description as input and produces the 3D model, from which physical data can be extracted for quantitative analysis.

    Coventor, in the latest in its series of informative whitepapers, has demonstrated in great detail how SEMulator3D can develop a model for a 3-axis gyroscope as used by Applein its iPhone4 (publicly available here).


    [a) SEMUlator3D final model of 3-axis gyroscope, b) Close up of a device corner]


    [Model output after a) Release oxide deposition, b) via to electrode, c) Epitaxial polysilicon growth and planarization, d) DRIE, e) Release]

    The above images show step-by-step process flow development. The epitaxial polysilicon device layer is patterned using DRIE and sacrificial release oxide layer is removed to release the device. For developing gyroscope comb fingers, different DRIE process set-points were evaluated with SEMulator3D’s Expeditor tool running an automated DOE with polymer deposition thickness ratio, silicon lateral etch ratio and polymer etch ratio as parameters. It has been observed that the top CD is more sensitive to the polymer thickness ratio when both the lateral etch ratio and the polymer thickness ratio increase. However high lateral etch and polymer etch ratio removes enough of thick polymer to keep the sidewall vertical. With thinner polymer the sidewall can become slanting.

    Interestingly, the device operating window can also be determined by estimating and computing the electrostatic parameters. The capacitance between the gyroscope’s comb drive actuators (patterned with DRIE) can be determined by meshing the 3D model and running a field solver on the mesh.


    [Capacitance extraction by meshing – a) Stator and Rotor fingers, b) Straight sidewalls, c) DRIE scalloped sidewalls. d) Computed results through field solver]

    The above images show how the capacitance of one portion of the comb drive actuator is evaluated. Initially the capacitance is estimated based on parallel plate capacitance resulting from finger overlap and then meshing was done, first with straight sidewalls and then with scalloped sidewalls due to DRIE.

    SEMUlator3D has recently added a very important state-of-the-art feature, ‘Structure Search’ that evaluates the entire 3D model to detect any structural violation, thus eliminating time-consuming destructive analysis to locate such failures. In the gyroscope model, Structure Search was used to locate the release oxide residues that could affect device performance (as the residual oxide can induce dielectric between the proof mass and the electrode, thus altering capacitance and limiting maximum out-of-place deflection of the mass) and yield.


    [Residue oxide – a) between widely spaced release holes, b) near device-to-ground vias, resulting from lithographic overlay variation due to shifted masks, c) clean without residue]

    In the above images, oxide residue locations are marked in blue color dots underneath a transparent device layer. The residues near vias can cause significant parasitic capacitance in the region and hence acceptable tolerance in mask placement must be estimated by this method.

    SEMulator3D 2013 provides an excellent platform for cost effective, fast and accurate model development of MEMS before fabrication, thus eliminating costly build-and-test cycles through the wafer production process. SEMulator3D’s advanced modeling capabilities provide accuracy of prediction in the final model for production to enable a higher yield than manual approaches. The whitepaperposted at Coventor website provides more depth of details. It’s interesting to read and enhance knowledge in these new trends and methods in MEMS and semiconductor manufacturing.

    More Articles by Pawan Fangaria…..

    lang: en_US


    2014: Keep calm, and program gates

    2014: Keep calm, and program gates
    by Don Dingee on 12-30-2013 at 4:00 pm

    I was tempted to call this piece “if you’re not using an FPGA, you’re doing it wrong,” but that didn’t quite capture the whole picture. Social memes aside, the FPGA as we know it is undergoing a serious transformation into a full blown SoC, and 2014 is the year that will usher in one of the biggest changes in the history of embedded design. Continue reading “2014: Keep calm, and program gates”


    Early Thermal and Power Simulation Using Virtual Prototyping for Pedestrian Detection Applications

    Early Thermal and Power Simulation Using Virtual Prototyping for Pedestrian Detection Applications
    by Daniel Payne on 12-30-2013 at 5:00 am

    In the 1970’s we designed ICs first and when silicon came back then we measured the power and junction temperature. At that time there were no EDA simulation tools or models for full-chip power and temperature analysis. Fast forward to 2013 and we find that temperature and power are still demanding requirements for MPSoC (multi-processor SoC) projects. Ideally you want to measure and control both power and temperature during the design phase of your project, instead of after manufacturing when it’s too late.

    Continue reading “Early Thermal and Power Simulation Using Virtual Prototyping for Pedestrian Detection Applications”