SemiWiki – Page 822 – The Open Forum for Semiconductor Professionals

July 6, 2014December 27, 2023

MIMO, Always On, 3D Imaging and Computer Vision…

MIMO, Always On, 3D Imaging and Computer Vision…
by Eric Esteve on 07-06-2014 at 12:08 pm
Categories: Ceva, IP

You can read all these articles in the latest CEVA Newsletter, if you didn’t read it first in Semiwiki! The blog describing the “Maximum Likelihood MIMO Implementation” is certainly going deep technically, as it introduce a complex Digital Signal Processing technique, Multiple Input Multiple Output (MIMO). MIMO is just like magic, as it could allow a x4 bandwidth multiplication, both for emission and reception. This DSP technique is all but trivial, but with good DSP engineer developing the right algorithm on the right piece of hardware, here a DSP core from CEVA, it’s possible to boost a base station and reach such bandwidth multiplication. The reader will discover why a linear algorithm, easy to implement, cannot fully exploit the MIMO benefits, when an optimal Maximum A Posteriori (MAP) approximation MIMO algorithm will generates high latency penalties. Finally, the non-linear MIMO receiver implementation known as Maximum Likelihood Detector (MLD), more demanding on processing than a linear receiver, will offer significantly higher bit rates for the same channel conditions. You also can find a white paper going deeper into MIMO analysis.

“Bluetooth on CEVA-TeakLite-4: it’s All about “Always-on” article will certainly enjoy the people convinced that IoT is the next big thing for the SC industry! Here is an extract from the blog written in Semiwiki about Always-on: “The Internet of Things comprises a multitude of devices, technologies and form factors, with many use cases and requirements. The CEVA-TeakLite-4 specifically targets user-centric IoT devices, where natural user interface, audio playback and voice communication represent key attributes of the device. This can include for example, voice activation, face triggering and other ‘always-on’ functionality in a smartphone, smart watch, smart home controller or wireless speakers. The ultra-low power nature of the CEVA-TeakLite-4 DSP ensures that these ‘always-on’ features consume minimal battery life. All of this functionality can run concurrently on the DSP without the need for a host CPU, reducing the die size and lowering power consumption of the overall device. Illustrating this, a real-life use case implementing Bluetooth Low Energy, always-on UI and sensor fusion on the CEVA-TeakLite-4 DSP requires less than 150K gates and consumes less than 150uW when implemented in a 28nm process.” Take a look at the CEVA Newsletter too…

Accelerating Computer Vision Applications? Thanks to CEVA’ADK for the CEVA-MM3101, image processing platform acquires new resources like gesture recognition, emotion detection and augmented reality.
Meanwhile, CEVA continues to build new resources into the libraries and examples available through the ADK. The following new kernels have recently been added to the library:

Matrix inversion
Feature detection: FAST9, HOG, SURF
New filters: bilinear, bicubic
Object detection: LBP, HAAR, SVM, ORB
Image processing: Histogram, gamma
Optical flow: FLT, block matching

In addition, new sample algorithms have been provided, demonstrating the capabilities of the CEVA-MM3101 for:

Face detection and recognition
Gesture recognition
Palm tracking
Augmented reality
Object detection and tracking
Emotion detection

You will learn in the Newsletter how the partnership between CEVA and nViso was key to develop “emotion detection”.

One of the articles part of this Newsletter was not in Semiwiki: “CEVA Targets Wearable” has been extracted from a report from the Linley Group, explaining that successful devices (to support wearable) will require processor custom designed for this application. If you go to CEVA web page, you will have the ability to download the complete report from The Linley Group, on top of reading CEVA-Newsletter.

Eric Esteve from IPNEST –

The Grand Folly of India’s Foundry Plans

The Grand Folly of India’s Foundry Plans
by Peter Gasperini on 07-06-2014 at 10:10 am
Categories: Foundries

At the beginning of the year, New Delhi’s outgoing government launched an initiative purported to drive the nation’s technology independence and reduce the current account deficit on electronics imports. The initiative describes a partnership between New Delhi and two industrial consortiums for the building of semiconductor manufacturing plants – one outside of the capital and the other in Western Gujarat.

“Every age has its peculiar folly: Some scheme, project, or fantasy into which it plunges, spurred on by the love of gain, the necessity of excitement, or the force of imitation.” – Charles Mackay, “Extraordinary Popular Delusions and the Madness of Crowds”

The plan is ambitious. The 28nm fab near New Delhi and the 22nm foundry in Western Gujarat will each support 40,000 wafer starts per month. The plan is also very expensive. Together, the facilities are projected to cost just under $11B USD. The government’s role in these two separate efforts is essentially that of a zero cost banker. Each consortium will receive an interest free loan of approximately $900M USD. Furthermore, the central government is on the hook for 25% of the total capital outlays, and is providing further incentives in the form of a bundle of tax deductions and duty exemptions. Thus, New Delhi’s expenses in this effort, not counting the tax incentive bundle, are just shy of $4B. What did the previous Cabinet expect to receive as a benefit to the nation for such an industrial policy?

Well, India’s electronics imports reached $31B in 2013, and that number is expected to explode to a whopping $400B by 2020. The contention is that laws requiring local content will translate to a drop in the net import value of electronics and help ameliorate the balance of trade. More directly, though, the Cabinet advertised the economic benefits it expected from the project – an estimated 22,000 direct jobs and another 100,000 spawned from enterprises that would sprout up to support foundry operations and employees in their immediate locations. There are other hoped-for benefits of a more strategic nature. The policy echoes sentiments that call for greater Indian participation in the Information and Technology sector of the global economy, along with all the economic clout and revenues which follow. Furthermore, as India grows in its expected role as a world power, efforts need to be made to provide local sources for the components that are used in the increasingly sophisticated navigation and communications suites, avionics and targeting systems used in the aircraft, naval vessels, ground vehicles and missiles of India’s armed forces. But will this really be of benefit to India? A very quick look at basic math provides a distinctly negative answer to this question.

Consider the following: the central government in New Delhi will be responsible for subsidies and credit to the efforts of the two industrial consortia amounting to $4B (and recall that this is not counting an additional un-quantified bundle of tax and customs subsidies.) If the estimates of consequent employment are correct (and that’s a big ‘if’, folks), each direct job will cost the Indian taxpayer over $180,000. In a country where the per capita income is $4300, the cost-benefit ratio is atrocious. Adding the ‘indirect’ job creation estimate for a total of 122,000 expected positions (also a very questionable figure), the cost is still at least $33,000/job. The gross inefficiency of such government ‘investment’ is glaring. The balance of trade benefits are even more dubious.

Let’s assume that both fabs were fully functional today and produced a complete range of semiconductor devices for 3C (communications, computing and consumer) electronics. This would, by necessity, have to include analog, RF, mixed signal, optical and TTL components, microprocessors, DRAM, SRAM, Flash, programmable logic, SoCs, discretes, MCUs and so on. The combined 80,000 wafers/month capacity of the two fabs amounts to roughly 1.5% of worldwide market share in 200mm wafer equivalents. In 2013, the semiconductor market was $315B on a global basis. Thus, one could theoretically produce $4.8B of semiconductor value to offset the 2013 electronics import tab, reducing it to roughly $26B thru regulations requiring 100% local content.

However, in 2020 the effect is more or less inconsequential, as fab capacity limitations would reduce a $400B deficit merely to $395B. India’s fab capacity would have to expand by an order of magnitude to keep pace, with a consequent explosive growth in cost.These considerations just scratch the surface of what is becoming increasingly identified as a historic debacle in India’s central government industrial development planning. There are many other factors involved in assessing the short and long term utility and efficacy of this initiative, including the role of the central government, tax policy, technology considerations, social issues, environmental aspects and broader implications to the national economy.

These issues and more are explored in greater depth at the Vigil Futuri blog and the Pune Chips website.

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July 6, 2014

Sonics and Qualcomm Make a Deal

Sonics and Qualcomm Make a Deal
by Paul McLellan on 07-06-2014 at 9:00 am
Categories: IP, Sonics

Some background. Sonics has been in the network-on-chip (NoC) business for a long time. Nearly 18 years years. When Arteris launched their products, Sonics figured Arteris were infringing Sonics’s patents and in 2011 brought a complaint against them. Details are here. Arteris looked at a couple of their own patents (if you are really that interested in the details, the patents are as follows: 7,574,629 – Method and device for switching between agents; 7,769,027 – Method and device for managing priority during the transmission of a message) and decided that Sonics was infringing them. But Arteris’ claims have been dismissed.

Qualcomm then bought a lot of Arteris. They acquired the engineering team, all the source code, the patents and so on. The old Arteris still has limited rights (to use the patents, the source code and to build a new engineering team). But Qualcomm now owns the two patents above.

That caused a problem for Sonic’s customers, especially ones that competed directly with Qualcomm. What if Qualcomm came after them for infringing the patents? In some ways, with the US legal system, it doesn’t matter too much whether you win or lose since the cost, the time and the distraction of a lawsuit means everyone loses.

So yesterday Sonics announced that they had signed a patent non-assert agreement on these two patents. Also all remaining claims in the case involving these patents have been dismissed pursuant to a joint motion by Qualcomm and Sonics. It is actually effective from March 24th.

Grant Pierce, the CEO of Sonics, emphasized that this is not the end of litigation.“As we have said before, Sonics will continue to seek protection for its broad patent portfolio, including patents that were invented and granted in the U.S., as outlined in Sonics’ complaint, Complaint for Patent Infringement (Sonics v. Arteris), of November 1, 2011. We are committed to seeing this time consuming process through to its completion.”

Talking of Grant Pierce, he was just elected to the EDAC board last month when the elections were held during #DAC51. He is the only new board member, the others continue from before.

There are a lot of moving parts in this story between Sonics, Arteris, Qualcomm and their respective customers and competitors. And of course the original Sonics complaint against Arteris is still to be decided. The Sonics press release is here.

July 6, 2014

The Great 28nm Debacle!

The Great 28nm Debacle!
by Daniel Nenni on 07-06-2014 at 9:00 am
Categories: Foundries, TSMC

40nm was a big node while I was Director of Foundries at the IP company Virage Logic which was later acquired by Synopsys. 40nm was big because the top fabless companies multi-sourced designs from one foundry to another with relative ease to get the best wafer prices. It was also the node where some of the big IDMs went fab-lite moving their leading edge IP and designs to the pure-play foundries.

I totally get the need for multi-sourcing. In my personal life I multisource my technology needs so I’m not beholden to any one company. I use FireFox for browsing, Yahoo for news, Google for search and maps, iPhones and iPads, Microsoft based laptops, it seems like human nature 2.0. In business however it’s a double edged sword, absolutely.

Since TSMC was first to 40nm, they did most of the heavy lifting only to see mass production moved to UMC, Chartered, and SMIC. I remember feeling bad for the TSMC wafer sales team doing all the work and not getting the appropriate rewards. I also remember wondering about the TSMC IP embedded in the GDS II design data (design rules etc…) moving about the world. Some fabless companies did their own design rules as a superset of the foundries to make sure designs were portable. Others just handed over TSMC GDS II and said, “Make this please.”

28nm changed things of course when TSMC was the only foundry to yield so it was the first and last full node for single source manufacturing we will ever see, my opinion. The TSMC 28nm fabs have been pretty much full since the first wafers shipped in Q4 2011. 28nm wafers were even on allocation at times which made the entire fabless semiconductor ecosystem uneasy. It also hit the fabless margins hard since TSMC did not have any pricing pressure. Considering what happened at 40nm the record high 28nm margins TSMC realized were well earned.

I remember the fabless quarterly conference calls in 2012 where the CEOs blamed 28nm wafer shortages for earnings misses which implied TSMC was not doing their job. It would have been nice if the CEOs were a bit more humble and admitted that TSMC did in fact ship the wafers under contract and it was their reliance on multi-sourcing that did them in this time. TSMC could have certainly built out enough 28nm capacity to prevent shortages had they been asked, right?

The 28nm landscape is changing again now that UMC, SMIC, GF, and Samsung are yielding enough to make a profit. Not the same profit as TSMC of course since they have the best yield and the fabs have been paid for many times over the last 2.5 years. At the same time TSMC is the only fab to ramp 20nm with production parts from Xilinx (FPGA), QCOM (modem), and Apple (SoC) hitting the market this year so the margins will keep pouring in.

“Handel Jones is WRONG about 20nm by one year. According to JK Wang, Vice President of Operations for 300mm fabs, TSMC will ship 300,000 20nm wafers in 2014 and 1,000,000 20nm wafers in 2015.“

The TSMC Q2 2014 conference call on July 17[SUP]th[/SUP] will reveal just how much 20nm revenue will be recognized so let’s talk after that.

July 6, 2014June 14, 2019

Coventor Brings More Accuracy & Performance into Design of MEMS Devices

Coventor Brings More Accuracy & Performance into Design of MEMS Devices
by Pawan Fangaria on 07-06-2014 at 9:00 am
Categories: Coventor, EDA

Although MEMS devices in various forms are now found in most electronic devices, predominantly in mobile, automotive, aerospace and many other applications, their major revolution, I believe, is yet to happen. We are seeing rapid innovation in MEMS reflected by their improvements in precision, performance, size reduction, and the continuing evolution of new devices with increasing complexities. The micro level fabrication of MEMS will enable unprecedented use of these into newer and newer semiconductor based electronic devices that will revolutionize the so called IoT arena. MEMS will be essential to IoT products’ ability to connect every aspect of our life, things and happenings around us and provide us ultimate knowledge, control, security through a wide range of devices in many form factors and environments.

The advancement in technology is accelerated when there are supporting tools to accurately model the devices, automate the procedures, quickly simulate, and analyze the designs. I like Coventor’sproducts in catalyzing this race towards reaching the ultimate in MEMS technology; MEMS+ for MEMS+IC design and analysis, CoventorWare for modeling and simulation of MEMS devices and SEMulator3D for process development and virtual fabrication of MEMS and semiconductor devices. I was delighted to look at the new release of CoventorWare 2014 suite that significantly adds into developing new generation of sophisticated MEMS devices. To know more details about the new offering in this release, I had a brief discussion with Steve Breit, VP of Engineering at Coventor. And here is what I learnt about the state-of-the-art new development that happened in CoventorWare 2014.

CoventorWare is a complete suite of tools which allows 2D layout design entry along with process and material information, automatically builds 3D model of a MEMS device, generates mesh, simulates and analyzes to optimize the MEMS device as desired. What we see in CoventorWare 2014 is much improved unique capabilities for high-performance and high-accuracy electro-mechanical and specialty MEMS physics simulations and a novel intuitive interface for fast setup and analysis. The simulators are order of magnitude faster and can handle large meshes on multi-core systems.

Above is an example of modal harmonic analysis of a specialized PZE (piezo-electric) resonator which is more than 10x faster (with 200 DoF and 88 frequencies) compared to the previous release of Coventorware; the speed-up can further increase with increasing number of DoF (Degree of Freedom) and frequencies. These fast simulations are critical for designing high-Q (Quality Factor) and low-TCF (Temperature Coefficient of Frequency) piezo-mechanical resonators. Similarly other specialized solvers such as PZR (piezo-resistance) for PZR sensors and Reynolds and Stokes solvers for gas damping are available.

CoventorWare provides FEM (Finite Element), BEM (Boundary Element) and also hybrid FEM/BEM methods of simulation for simulating various MEMS physics. The FEM simulations can be used for mechanical analysis including robust contact events whereas BEM simulations can be used for electrostatic actuation and capacitive sensing. The hybrid FEM/BEM approach is used for coupled electro-mechanics, and in CoventorWare 2014 it is 5x faster due to optimization for multi-core systems and a new convergence algorithm.

The new convergence algorithm, ‘Accelerated Coupling’, is available via an intuitive new setup dialog that reduces the number of iterations required for convergence thereby reducing the simulation time.

In order to further enhance user experience in designing increasingly complex MEMS devices, the GUI and user interface has been simplified for all kinds of coupled electro-mechanics along with solver progress reporting on the Job Queue tab. A powerful Python scripting interface has been extended to include mesh and material transforms, making it easy to automate studies of sensitivity to design and manufacturing variables.

Steve summarized by saying that a combination of improvements to simulation performance (which includes multiprocessing, specialized algorithms and optimization of field solvers), user interface enhancements and new scripting support for user convenience has increased user capabilities for efficiently designing and simulating a wide range of MEMS devices with increasing set of parameters for varied applications as per requirement. For example, Gyroscopes can have different levels of bias drift precision depending on their application. While consumer applications are fine with low precision, navigation applications will require very high precision. The Gyroscope designs can be affected with multiple parameters such as bias voltage, electrostatic drive force, and physical effects such as quadrature, thermo-elastic damping and anchor losses. Similarly a varied range of effects must be considered when designing other MEMS devices such as accelerometers, microphones, RF switches & varactors and so on.

It was a very interesting and informative interaction with Steve that enhanced my knowledge about CoventorWare in general and CoventorWare 2014 in particular. It’s worth exploring and using if you are thinking of refining an existing MEMS device or designing a sophisticated new one.

Fantasy Tech-Ball and the Intel Rumor Wire

Fantasy Tech-Ball and the Intel Rumor Wire
by Don Dingee on 07-06-2014 at 9:00 am
Categories: Foundries, FPGA, Intel Foundry

Reading Intel analysis lately has been a lot like reading fantasy baseball analysis. Intel should buy Altera. Intel should waive Atom. Intel should fab for Apple. All of those have a near-zero probability of happening IMHO, and yet pundits continue to pitch their version of alternate reality, dealing away product lines and strategies left and right. Continue reading “Fantasy Tech-Ball and the Intel Rumor Wire”

July 6, 2014

An Approach to Clock Domain Crossing for SoC Designs

An Approach to Clock Domain Crossing for SoC Designs
by Daniel Payne on 07-06-2014 at 12:20 am
Categories: EDA

Blogger Pawan Fangaria wrote about Clock Domain Crossing(CDC) a few weeks ago, and so I followed up tonight and watched a webinarabout CDC presented by Ravindra Anejaof Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:

Fast throughput and thoroughness
Ability to debug and fix the source of CDC errors
Handle billions of gates and be considered a signoff tool

Continue reading “An Approach to Clock Domain Crossing for SoC Designs”

July 5, 2014

Solar Leases, How to Not Get Gouged by PG&E

Solar Leases, How to Not Get Gouged by PG&E
by mbriggs on 07-05-2014 at 12:00 pm
Categories: General

This post will be of primary interest to California residents.

If you haven’t looked closely at your PG&E bill, this may ruin your day. If you live in a house larger than a cracker box, and actually use your lights and air conditioning, the rates you pay are exorbitant. If you live in WA you’ll be paying .06-.08 per kilowatt hour. In CA you are probably paying in excess of .30. I like to call this California’s version of hidden socialism. Check out Electricity Prices by State.

PG&E, of course hides this fact. You need to download the pdf detail for your bill, then surf to page 3.

Note that for the crackerbox Tier 1 Allowance, at .13627 per kilowatt hour, I am allowed 352 kWh. This is just about enough to power my computers and my TV. The majority of my usage is at Tier 4, which costs me .35955 per kWh.

Solar Leases

I recently signed on the dotted line for a solar lease. This means that I have committed to paying Vivint Solar, a monthly fee for the next 20 years. I mentioned this to a friend and he said “Are you nuts?. You’ll have a hard time selling your house as you’ll have to include the remainder of the solar lease as part of the deal.” This perception arises because the “solar lease competition” is doing an awesome job discrediting the program. Read about it at http://solarleasedisadvantages.com/. Fortunately Elon Musk’s company SolarCity is in the game, and adding needed credibility to the space.

The way it works is that I pay zerofor the panels, zerofor installation, and zerofor maintenance. I then pay Vivint .14 per Kilowatt hour for all the power the panels produce. They size the system so that it will accommodate approximately 75% of my power needs, so I continue to pay PG&E, but at the Tier 1,2 rates. This works from Vivint’s perspective as they pick up the federal tax credit. There is an annual increase of 2.9%, but the argument is that PG&E will increase prices at a similar or faster rate.

I could have purchased the panels outright, but would have needed to fork out somewhere between $40-75K, and been responsible for the maintenance. Best case payback is 7 years. Since Vivint owns and maintains the panels I really don’t care if the technology changes.

You may have heard from the companies that sell solar panels that you can push your unused power back on the grid, and have PG&E pay you for it. Ha, ha. PG&E in it’s infinite generosity will pay you .02 / kWh for that power.

To me this is a big win, and I’d think that for a future buyer of my house it would also be a win. I also like extending my middle finger to PG&E.

July 5, 2014

July 4th Fireworks

July 4th Fireworks
by Paul McLellan on 07-05-2014 at 9:00 am
Categories: General

It was July 4th yesterday. Fireworks. I didn’t go down to the waterfront to see them in San Francisco this year, I was in a “place” (that might possibly have served beer) having fun. But it reminded me of this a couple of years ago. On July 4th 2012 the San Diego fireworks display, one of the biggest in the world, detonated simultaneously. They fired every single thing at once, or within about 10 seconds. Luckily their protocols were such that everyone was locked down inside bunkers and nobody was hurt even in that worst case scenario (which involves 5 barges spread over nearly 15 miles).

Of course it was a PR disaster. But let’s face it, for everyone who saw it, it will be the most memorable fireworks show of their lives. The press had a field day about “massive hardware failure” but if you are in technology (and if you are not, what the hell are you doing here?) that sounded dodgy. A big hardware failure would result in no fireworks going off at all. Totally believable. But all at once? That has to be a software screwup. And so it proved. A few days later they issued the postmortem. It reads a little like the postmortem on chips that need a respin, everything was checked but somehow something got through. We used the wrong CPF file. The old version of the IP. Whatever.

The report on the fireworks is here (pdf).

Warning: heavy geek factor if you read further!

This reminds me of another screwup when a space vehicle failed to get into orbit around Mars (I think, I’m remembering all this so the details may be slightly different but the basic idea is accurate).

The code was written in Fortran which, unless you are of a certain age, you have probably never used. It was invented in the 1950s when a lot of what we know now…well, we didn’t know. It had a number of convenient features which people though were neat like:

variable names could have spaces in them (that were ignored, in fact all spaces were ignored except in quoted strings). So you could say R AND R (we didn’t have lower case back then). Or, as turned out to be significant, DO 13 I
variables didn’t have to be declared. if you used one then if it started with I-N it was integer and otherwise was floating point. DO13I is thus a floating point variable.
Loops in Fortran were known as DO loops and had a syntax like this:

[INDENT=2]DO 13 I=1,5

which meant execute all the instructions between here and the label 13 with I taking the values from 1 to 5, like a for loop in C. No we didn’t have brackets {} either. Just labels.

Loops were ended with a labelled statement. So that you could GOTO the end of the loop (equivalent to break in C) you could label a CONTINUE statement that did nothing. Whereas jumping to the last statement of a loop if you labelled it would execute that statement. But there was no problem having a CONTINUE statement not in a loop. You wouldn’t get a peep out of the compiler.

So what happened to the spacecraft? Someone put in a typo:DO 13 I = 1.12

with a period instead of a comma. It is all totally syntactically correct. It was a Newton-Raphson iteration to solve a differential equation to calculate the amount of speed required. But with the rules I told you about this was actually:DO13I = 1.12

Namely declare a floating point variable DO13I and assign it the value 1.12 (and never use it again. No we didn’t have Lint type tools back then either. Or tools period).

So instead of the loop running 12 times (to converge on a good value) it ran through once (since it wasn’t a loop, just an assignment statement) and it used the initial approximation. Newton-Raphson is so efficient that it doesn’t much matter what the initial approximation is in most circumstances, nobody makes any effort to get it close. Just use 1. And maybe a couple more iterations if necessary (and yes, I know about double roots, but that is nothing to do with this).

Result. Loss of spacecraft. One character wrong.

Back to fireworks. This video has gone viral so you have probably seen it. A guy flys a quadracopter drone through a fireworks display with an HD GoPro camera. It survives (although takes a few minor hits and lots of stuff flying by). Happy Day-After-Independence-Day

P.S. Someone a decade ago asked me what the Brits do on July 4th. “Nothing, we lost” I replied.

Mentor Graphics @ SEMICON West 2014

Mentor Graphics @ SEMICON West 2014
by Daniel Nenni on 07-04-2014 at 10:00 pm
Categories: ESD Alliance, Events, Semiconductor Services

Mentor is again the most represented EDA company at SEMICON West this year. I strongly advise Cadence and Synopsys to get more involved because EDA may be where electronics begins but semiconductor manufacturing makes all of our hard work come true, absolutely. Paul McLellan, Beth Martin, and I will be blogging live, I hope to see you there!

My good friend Steve Pateras is up first. I worked with Steve at LogicVision, which is one of Mentor’s most profitable acquisitions of all times I’m told. Steve is a great guy (very approachable) so don’t miss this one if you are even remotely involved in silicon test:

Ensuring High Defect Coverage of FinFET Based Designs

Steve Pateras
Marketing Director Silicon Test
Mentor Graphics

Abstract: The semiconductor industry is ramping deployment of FinFET transistors. These devices provide important benefits such as lower static leakage leading to lower power ICs, and high drive currents enabling faster switching at lower supply voltages. FinFETs however represent a fundamental change to the underlying structure of the transistor resulting in an impact on the IC design and manufacturing flows. In particular, FinFET critical dimensions are for the first time significantly smaller than the underlying node size, leading to a growing concern over increased defectivity levels and therefore test quality and cost.

This presentation will introduce the concept of Cell-Aware test, a transistor-level test methodology that overcomes the limits of traditional stuck-at and transition fault models and associated test patterns by targeting specific shorts and opens internal to each standard cell, resulting in significant reductions in defect (DPM) levels. This technique is used to specifically model and target leakage and drive strength related transistor defects that are likely to be common in FinFET devices. The Cell-Aware approach requires only modest increases in test time despite significant improvements in defect coverage, making it a highly efficient and thus pragmatic solution.

Using a Gallery Concept to Optimize an EUV Flow

Dr. Fan Jiang
Product Engineer, Mask Synthesis Solutions
Mentor Graphics

Abstract: While there is debate about when extreme ultraviolet lithography will be ready for production, there continues to be active research and development aimed at improving every aspect of the EUV system, including optical system modeling and correction. Unlike today’s ArF (λ=193nm) lithography, proximity effects aren’t much of a problem to EUV lithography because the wavelength (λ=13.5nm) is much closer to the size of the design features. However, because EUV systems are completely reflective (i.e., uses mirrors instead of lenses) there are new effects that did not exist or were negligible before, such as shadowing and flare, that must be addressed. Associated with these new effects are a range of models and correction techniques used to make up for limitations and inaccuracies in the EUV system, just as there are in today’s lithographic flow. Our research into a variety of these EUV resolution enhancement technologies (RET) indicates the there are many possible combinations of techniques thatmust be considered to create a flow that is optimized for target accuracy and performance (runtime) objectives. To achieve the best flow for specific product lines, lithography engineers need to start with a comprehensive gallery of models and tools that address the various issues that arise in practical EUV flows. This presentation will discuss the specific challenges of reflective EUV systems and demonstrate the variety of modeling and correction techniques that can help engineers meet both accuracy and runtime objectives for their IC manufacturing flows.

The Next Generation Scan Test Diagnosis

Geir Eide
Product Manager
Mentor Graphics

Abstract: Layout-aware diagnosis represented a dramatic advance in digital semiconductor diagnosis software technology. With up to 85% reduction in suspect area and the addition of defect classifications, it cemented the position of diagnosis in use for defect localization, and paved the way for use of diagnosis in yield learning applications. In this presentation, we will present Root Cause Deconvolution (RCD), the next generation diagnosis technology that dramatically improves the resolution in diagnosis results. RCD performs statistical enhancement of layout-aware diagnosis results to identify the underlying root causes of failures. For instance, layout-aware diagnosis may point to a net segment that spans multiple layers as the possible location of an open defect. RCD narrows this result down to a specific VIA in this net segment. This dramatically reduces the FA cycle time by increasing the FA relevance and success rate. It also enables “virtual FA”, the ability to determine accurate defect distributions for a population of failing devices before any failure analysis is performed….

SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

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