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GlobalFoundries Goes to Semicon West

GlobalFoundries Goes to Semicon West
by Paul McLellan on 07-04-2014 at 8:38 pm
Categories: ESD Alliance, Events, Foundries, GlobalFoundries, Semiconductor Services

Next week it is Semicon West, the big equipment vendor tradeshow. I love to go since EDA and semiconductor and all the stuff we are interested in here at Semiwiki are driven by equipment capabilities, especially lithography. The highest viewed blogs I write tend to be ones on technologies that are just a bit out beyond the stuff people have to worry about today. Is EUV going to happen and when? What about 450mm wafers? Is DSA (directed self assembly) really a thing or an academic toy? E-beam, can it work, are the data rates even feasible? Carbon nanotubes, where are they really? Semicon West is the place to get the best information about all this stuff. I’ll be there (as will Dan).

It is also the place to find out what the foundries are all thinking about. Most chips will be manufactured by foundries after all (outside of the memory business) so it is important. GlobalFoundries have 7 presentations during the next week.


David Duke: Secondary Equipment for Mobile & Diversified ApplicationsMobile, IoT, and other consumer-driven applications are changing behaviors throughout the semiconductor supply-chain. This trend has become noticeable not only at the leading edge, but also for n-2 nodes. Many of these applications rely on Analog, Power and other “More than Moore” devices which, in turn, rely on secondary/legacy equipment for their manufacture.

Les Marshall: Subcomponent Supply Chain for 10nm and BeyondAttendees will hear perspectives from leading edge IDMs and OEMs as well as expectations from critical subcomponent suppliers on how to create a more interactive and collaborative supply chain for greater efficiency, increased technology exchanges, and cost improvements at advanced nodes.

Rohit Pal: Variability Control – A Key Challenge and Opportunity for Driving Towards Manufacturing ExcellenceVariability is one of the biggest challenges when CMOS devices are scaled to meet the demand for portable electronics with increased functionality. The problem is that device sizes have been downscaled to the point where the electrical properties of individual devices are very sensitive to small changes in their materialproperties. A multi-faceted variability reduction approach is needed that comprehends integrates chip design, process and equipment development.

Reed Content: Sustainable Manufacturing Forum: Fabless Considerations in Manufacturing

Ganesh Subramanian: Challenges, Innovations and Drivers in MetrologyHow can we be more proactive in designing the metrology schemes around the introduction of new devices,materials, and components? Efficient yield and stable manufacturing requires good metrology during the HVM ramp, which means it would be desirable to have new metrology andcharacterizationtechniquesavailable early in the R&D process in order to improve cycle times and speedtime-to-market. Certain requirements, such as smaller critical dimensions (CD) and tighter overlay,aredriven by scaling. In some cases, these requirements can be accommodated by incrementalimprovements of existing techniques, but these approaches could be nearing the end of theirextendibility

An Che: Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and BeyondDriven by application and cost considerations, major IC manufacturers have made their transistor technology choices for 14nm (either FinFETs on bulk or SOI, or FDSOI. Beyond 14nm, even more choices will have to be made with respect to non-planar architectures, high-mobility materials, substrate materials, and process modules. Some experts are also looking at disruptive scaling technologies and alternatives to scaling (e.g., monolithic 3D). This session provides an overview of the transistor structures, materials, and process technologies that will need to be developed to get the industry down to 5nm

T.M. Mak: Test Vision 2020Test Vision 2020, formerly ATE Vision, has emerged as the premier workshop in the area of Automated Test Equipment. Attracting record attendance from a broad cross-section of the semiconductor community, the workshop features a compelling line-up of papers, keynotes and panel participation from leaders in the industry. This year, once again the workshop will be held in conjunction with SEMICON West and will examine where the test industry is heading and provide a forum for discussing the directions and solutions for emerging problems.

Full details on these sessions (and all the rest) here.


More articles by Paul McLellan…

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It’s Always Good If the Customer Is Arguing

It’s Always Good If the Customer Is Arguing
by Paul McLellan on 07-04-2014 at 2:41 am
Categories: General

I’ve never been in sales. Never “carried a bag”. But I have run sales forces and I have spent a lot of time in marketing, guiding sales forces. Well, herding cats comes to mind, but cats don’t have commission plans. Engineers say sales people are emotional, and ego-driven, but change their commission plans and sales people turn on a dime. They reschedule their meetings for the following week. Tell an engineer their baby project is killed and they will grieve for weeks. It is engineers who are emotional not sales people. I’ve managed both, more on the engineering side probably, being an engineer by background.

So one thing I have noticed is that new salespeople complain that there is a product or engineering problem when the customer is pushing back. Of course, if it is an existing customer complaining about some problem with a tool the purchased then it can be a genuine problem. EDA is such a fast churning industry that no tool is ready for release…when it has to be released. It has never seen good test data. When FinFETs came along, how much FinFET test data was available for EDA companies to test their stuff on. None, would be a pretty good answer. Not much maybe closer to the truth. CTO’s of semiconductor companies used to tell me when I worked at Cadence that we should have better software quality and I told them to use the prior release. It was pretty solid. Of course they couldn’t for the current process node, but the reality in EDA is that the software was developed, like, yesterday. It won’t be stable until a lot of designs have been run through. The choice is wait (which some people can) for other people to run all those designs through, or live with the instability that goes with being one of those early guys through. But they argue about the issues all the time with their salespeople.

So I tell members of the sales team that it is always good when the customer is arguing. After all, think of the last time some salesperson tried to sell you solar panels, or a swimming pool. If you were not interested you would shut up and try and get them to go away. If you were, then you would say that the price was too high, or the pool was the wrong size. It’s always good if the customer is arguing.

It is not restricted to leading edge stuff, but there seems to be more argument there because it gets the most visibility. But ultimately IC design is a strange ecosystem to sell into. As a friend once said to me, EDA is the “only environment that when you try and sell them a car they take the cylinder-head off and check the valve timing.” If that isn’t arguing then I don’t know what is. So when they make the effort to “check the valve timing” then it is not a criticism of the engine/tool but a sign that they care enough to check, they are interested.

But it’s always good if the customer is arguing!


More articles by Paul McLellan…

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Intel is Speaking @ SEMICON West 2014!

Intel is Speaking @ SEMICON West 2014!
by Daniel Nenni on 07-03-2014 at 8:00 am
Categories: ESD Alliance, Semiconductor Services

The SEMICON West website has a nice “speakers” option where you can search by company and see who is talking about what. I’m always interested in what Intel has to say (they are still the leading semiconductor company) so here is the line-up for next week:

Intel Sanchali Bhattacharjee Subcomponent Supply Chain for 10nm and Beyond

Intel Janice Golda Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond
Wednesday, July 9, 2014
9:00am-12:00pm
Moscone North, Hall E, Room 131
Driven by application and cost considerations, major IC manufacturers have made their transistor technology choices for 14nm (either FinFETs on bulk or SOI, or FDSOI. Beyond 14nm, even more choices will have to be made with respect to non-planar architectures, high-mobility materials, substrate materials, and process modules. Some experts are also looking at disruptive scaling technologies and alternatives to scaling (e.g., monolithic 3D). This session provides an overview of the transistor structures, materials, and process technologies that will need to be developed to get the industry down to 5n

According to LinkedIn: Janice Golda manages an organization responsible for creating strategies and working with Intel’s lithography pattering, metrology, mask, and process/product debug equipment suppliers and sub-suppliers to develop and deliver equipment and materials meeting Intel’s roadmap requirements for technology, affordability, and velocity. I will definitely attend this session. I do plan on being around for 5nm, absolutely.

Intel Tim Hendry Breakthrough High Volume Manufacturing Innovations: New Paradigms for the Road Ahead

Intel Sunit Rikhi SEMI/Gartner Market Symposium
Monday, July 7, 2014
1:00pm–5:30pm
San Francisco Marriott Marquis, Golden Gate A
The SEMI Market Symposium, co-sponsored by SEMI and Gartner, provides a midyear market update as well as a forum to discuss pertinent business issues. SEMI and Gartner will present market forecasts and analysis for the semiconductor, capital equipment and semiconductor materials industries.

We all should know Sunit. He is Vice President, Technology and Manufacturing Group; GM, Custom Foundry at Intel. In fact, Sunit has been at Intel for as long as I have been working in Silicon Valley. He started as EDA Software Manager in August 1984. Sunit and I have spoken before, he is a great guy and knows semiconductor design and manufacturing from the ground up:

  • Software Engineering Manager, EDA
  • Engineering Manager, Mask Operation
  • Business Development Manager, Mobile Computing
  • Director, Logic Technology Automation
  • Vice President, Technology & Manufacturing Group; Director, Advanced Design
  • Vice President, Technology and Manufacturing Group, GM, Custom Foundry

If you do a search on LinkedIn for “Intel Custom Foundry” you can see the rest of his team, about 500 of them. The common denominator is their long careers at Intel.

Sunit will be speaking on:

“Intel Custom Foundry as a relatively new player in today’s Fabless ecosystem offering custom manufacturing services that include wafer manufacturing and beyond. The talk will highlight the challenges and opportunities of winning in a highly competitive environment, of being inside the world’s leading IDM, and of leading the innovation in design at the leading edge of Moore’s Law.”

No way I’m missing this one! Hopefully he has read our book “Fabless: The Transformation of the Semiconductor Industry”. Remember, to know where you are going you must know where you have been. I will bring a signed copy for Sunit, absolutely.

More Articles by Daniel Nenni…..

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In Case You Missed #51DAC

In Case You Missed #51DAC
by Daniel Nenni on 07-02-2014 at 9:50 am
Categories: EDA, Events

This will probably end up being the most memorable DAC for us since Paul and I signed hundreds of copies of our book “Fabless: The Transformation of the Semiconductor Industry”. I’m not sure how we are going to top that next year but I’m confident we will think of something. If you want to catch up on the live blogs from the last three conferences check the Design Automation Conference ( DAC ) Wiki.

It is interesting to see the DAC numbers over the last three years. If you have more DAC data that you would like included feel free to edit the wiki or post it in the comments section and Daniel Payne or I will add it. Comments on how to improve DAC would also be appreciated. It is important to document past conferences to make sure we prepare for the next one. In my experience most companies that fail usually fail at the future so let’s make sure that does not happen to our beloved DAC.

It is interesting to see the conference numbers over the last three years from the wiki:

Location: San Francisco, CA 2014
Attendance:

  • Full conference passes – 2,393
  • Exhibits-only passes – 1,650
  • Exhibitors booth staff – 2,658

Location: Austin, Texas 2013
Attendance:

  • Full conference passes – 1,589
  • Exhibits-only passes – 2,364
  • Exhibitors booth staff – 1,998

Location: San Francisco, CA 2012
Attendance:

  • Conference attendees – 1901
  • Exhibits-only passes – 2783
  • Exhibitors booth staff – 2704

I had predicted a blow-out attendance this year and it did not happen!?!?!? Conference passes were up, which is great, but what happened to the exhibit only passes? Do we not love DAC anymore?

The DAC committee is also looking for your feedback. There is a new General Chair in town and she will be blogging once a week for the next 52 weeks to give you a behind the scenes look at how this conference gets ready for June 2015! This is a VERY brave thing to do! It is for the greater semiconductor good, so please support this effort.

Anne Cirkelis the General Chair for the 52nd DAC and a Senior Director for Technology Marketing at Mentor Graphics. Prior to joining Mentor Anne held marketing management positions at Analogy, Viewlogic, and Berner & Mattner. Anne holds a Master’s degree in Business Administration with an undergraduate in Metallurgy from RWTH Aachen, in Germany. She has been actively involved on the Executive Committees for DAC and DATE as well as the Program Committee for Embedded World.

Here is what Anne has thus far:

#52DAC will again be in beautiful San Francisco before returning to Austin in 2016. Let’s figure out how to make this coming DAC bigger and better. A $300B+ industry that is critical to modern life is depending on it, absolutely.
The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. Members are from a diverse worldwide community of more than 1,000 organizations that attend each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities.

More Articles by Daniel Nenni…..

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So Easy To Learn VIP Integration into UVM Environment

So Easy To Learn VIP Integration into UVM Environment
by Pawan Fangaria on 07-02-2014 at 7:30 am
Categories: Cadence, EDA, IP

It goes without saying that VIPs really play a Very Important Part in SoC verification today. It has created a significant semiconductor market segment in the fabless world of SoC and IP design & verification. In order to meet the aggressive time-to-market for IPs and SoCs, it’s imperative that readymade VIPs which are proven with latest specifications must be used to accelerate the complex task of verifying SoCs. And that can happen when there are easy methods available for integrating VIPs into the SoC testbenches and testing them.

It was a pleasant surprise to see this videofrom Cadencewhich demonstrates the integration of PCI Express VIP in UVM Environment with such clarity in just about five minutes. I didn’t think it was so easy to learn. Since Cadence acquired Denali, it has always been ahead in keeping up with the latest specs for PCIe VIP, providing the broadest range of PCIe VIPs covering most of the applications including mobile and cloud, very advanced compliance testing and superb debugging environment. No wonder Cadence is continually advancing in this area of business. The maturity of Cadence’s experience in VIP business is reflected by the kind of seamless integration environment it provides.

In the UVM environment, multiple agents are put together to stimulate the design, collect coverage and perform self-checking, thus enabling verification of multi-layer components such as PCIe VIP.

The PCIe VIP is integrated into the UVM test environment as UVM agent; multiple agents are encapsulated under the UVM environment. There are active and passive end points to stimulate and monitor the behaviour of the design.

Cadence provides PCIe UVM agent with the installation which can be used straightaway to start verification or it can be customized as per user requirement. The basic verification components such as sequencer, driver and monitor can be extended from the UVM agent. Let’s look at some glimpses of the code which is used to set properties, configure the verification components, and create and instantiate verification components and so on.

On the left side, there is code to set properties for the activeRC component. On the right, there is code for configuring the verification component by extending cdnPcieUvmConfigFunction which is extended from UVM config object. It contains all the functions and attributes of verification. The VIP checks the consistency of all these functions and attributes before starting the verification. The configuration can also be done with graphical interface which allows setting all functions and attributes and checking their consistency.

Above is the code for instantiating and creating verification components. On the left, there is code for instantiating a verification component and virtual sequencer. On the right, the verification component and the virtual sequencer has been created. And a connection between the virtual sequencer and the sequencer of the UVM agent is also created.

Above is the simulation result which can provide very detailed analysis for easy debugging.

This morning, while writing this article, there was another pleasant moment to see Eric Steve’s articleon semiwiki which says about the release of PCI Express 4.0 specifications and its complex features which are already included in Cadence PCIe VIP.

It’s a worthwhile 5 minutes video(presented in a very candid manner by Amir Attarhaof Cadence) to look at and learn how a VIP can boost the productivity of a verification engineer, simplify protocol compliance and shorten the design cycle to meet the short window of opportunity. It’s a must watch for design and verification engineers, students raring to get into semiconductor SoC and IP specialization and others in the semiconductor community.

More Articles by Pawan Fangaria…..

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Is this thing real? Symmetric authentication will tell you!

Is this thing real? Symmetric authentication will tell you!
by Bill Boldt on 07-01-2014 at 6:00 pm
Categories: Foundries

The act of authentication is very straightforward. Essentially, it is making sure that something is real.

There are two parts to authentication:

[LIST=1]

  • Identification
  • Confirmation of identity

    Authentication in the “crypto-verse” typically happens on a host and client basis where the host wants to ensure that a client is real. A typical use case occurs when a client device is inserted into a system, while the host asks (“challenges”) the client to confirm its identity. This can occur when an ink cartridge is inserted into a printer, or a water filter is put into a refrigerator. a battery is put into a phone, and numerous other applications. Firmware and software can be authenticated too, but that is a topic for another article.

    Think of the challenge as when the castle guard in an old movie asks, :Halt! Who goes there?”. The guard expects a suitable response to prove confirm the identity of the approacher.

    Getting back to the real world, authentication is accomplished using a process focused on calculations involving cryptography keys, and that is true for both of the major types of authentication; namely, symmetric and asymmetric. We will focus on the symmetric process here.

    With symmetric authentication, the host and client both have the exact same key, which is in fact how symmetric got its name. Note that is critical for both keys to be kept secret to ensure security. Keeping secret keys secret is the main touchstone of authentication and data security of any type. The best way to do that is using a secure hardware key storage device.

    The basic idea behind symmetric authentication is that if the client is real then it will have the exact same key as the host. Challenge-response is a prescribed methodology to prove it.

    The host controller sends the client a numerical challenge to be used in a calculation to create a response, which is then compared to a similar calculation that is performed on the host.

    To describe the process in more detail we can look at a typical symmetric authentication architecture using Atmel ATSHA204A devices on both the host and client and a microcontroller in the host. (Another article will explain how this is done with the crypto device on the client only, which is the fixed challenge methodology).

    Step 1: The process kicks off when the host sends a random number to the client which is generated by the host’s ATSHA204’s random number generator. This is the “Challenge” and is illustrated above.

    Step 2: The client receives the random number challenge and runs it through a hash algorithm (i.e.SHA256) using the secret key stored there. The result of the hashing function is called the“Response” and it can also be called the “Message Authentication Code” (or MAC). A MAC is technically defined as the result of a hashing function involving a key and message. The response is sent to the host.

    Step 3: The host internally uses the same challenge (i.e. the random number) that it sent to the client as an input to its internal hash algorithm. The other input to the internal hash is the secret key stored on the host side. Then the host compares the hash value (MAC) calculated on the host side with the response hash-value (MAC) sent from client. If the two hash values (MACs) match – then the keys are indeed the same and the client is proven to be real.

    Note that the secret keys are never sent outside the devices, as they always remain securely stored in protected hardware and invisible from attackers. Stated very simply:“You can’t attack what you can’t see.”

    Benefits:
    The benefits of a symmetric architecture with secure key storage crypto engine devices on both sides are:

    • Symmetric authentication with crypto devices on both sides is quite fast.
    • Secure hardware storage on both sides increases security.
    • Ensures a very low processing burden on the microcontroller.

    For more details on Atmel CryptoAuthentication™ products, please view the links above or the introduction page at CryptoAuthentication.

    Bill Boldt, Sr. Marketing Manager, Crypto Products Atmel Corporation

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    A song of optimization and reuse

    A song of optimization and reuse
    by Don Dingee on 07-01-2014 at 10:00 am
    Categories: Arteris, IP

    If you hang around engineers for any time at all, the word optimization is bound to come up. The very definition of engineer is to contrive or devise a solution. With that anointing, most engineers are beholden to the idea that their job is creating, synthesizing, and perfecting a solution specifically for the needs of a unique situation. Continue reading “A song of optimization and reuse”

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    PCI Express 4 specification just released for PCI-SIG DevCon

    PCI Express 4 specification just released for PCI-SIG DevCon
    by Eric Esteve on 07-01-2014 at 4:45 am
    Categories: Cadence, IP

    I have been alerted by a blog from Moshik Rubin from Cadence: PCI-SIG has finally released the PCIe 4.0 rev 0.3 specification for members’ review, on time for the PCI-SIG developers conference last June in Santa Clara. Since the early days of PCI Express in 2005, Denali (at that time, now Cadence) has positioned the PCIe VIP as the first to be released. This aggressive positioning was a part of Denali’s success: being the first on the market greatly helps catching the first PO from customers, large IDM or smaller IP vendors. Getting fresh cash in advance helped minimizing cash investment and boost engineering and product development effort. Sounds like a winning strategy!

    If you take a look at the PCI-SIG website, you can download the conference agenda and realize that PCIe 4.0 is more than a buzz word, as several presentations were specifically dedicated to PCIe 4.0 Electrical, Card Electromechanical Specification (CEM) or Encoding and PHY Logical. You may be surprised by the number of presentations dedicated to M-PCIe, the joint specification issued by the MIPI Alliance and PCI-SIG. In fact, PCIe 4.0 is the first specification fully integrating M-PCIe (M-PCIe was an ECN of PCIe 3.0 specification). Mobile Express attractiveness is still strong within the SC industry, and the M-PCIe dedicated presentation cover an overview, MIPI M-PHY Technical Overview, Testing and Verification of M-PCIe devices and also a Holistic Approach for M-PCIe implementation!


    The Cadence M-PCIe Subsystem IP supports up to height M-PHY lanes in each direction, and has over 100 configuration features and 1500+ input parameters, to customize the subsystem to the specific needs of the application. This very wide configurability capability is directly linked with the PCI Express specification, offering an extensive set of parameters. That is, the Cadence M-PCIe Subsystem IP uses the company’s Silicon proven PCIe Controller core, and the M-PHY Physical layer.

    The logical physical layer provides an RMMI interface to connect the M-PHY device, and the Host Adaptation Layer (HAL), or optional AXI3, provides connectivity to the client. The picture below illustrates the RMMI implementation:

    As usual, Gen-4 specification is doubling the bandwidth while keeping backward compatibility. Let’s review the main changes/additions of the new specification:

    • Speed negotiation and operation at 16.0 GT/s
    • Link equalization procedure for 16.0 GT/s
    • Inferring electrical idle conditions at 16.0 GT/s
    • Reorganization of the PCI Express electrical specification
    • Incorporation of all post Gen3 ECNs (including M-PCIe)

    Cadence PCIe 4.0 VIP was announcedin May and provides support for all of those changes. This VIP has been demonstrated during PCI-SIG DevCon 9 at the Santa Clara Convention Center. As mentioned earlier in this paper, Cadence has adopted the same aggressive Verification IP launch strategy for than Denali. More than just a successful marketing strategy, this policy makes Cadence as essential part of the PCI Express Ecosystem, as IP vendors and IDM need to benefit from a VIP available in advance, before the final PCIe 4.0 specification is frozen, to be able to launch PCIe 4.0 products with a TTM advantage! As far as I am concerned, I also expect to see the PCIe 4.0 Design IP to be released soon by Cadence, as the Design IP group should benefit from the efforts made by the Verification IP team!

    From Eric Esteve from IPNEST

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    RTL Signoff Update from #51DAC

    RTL Signoff Update from #51DAC
    by Daniel Payne on 06-30-2014 at 7:00 pm
    Categories: EDA

    In the early days of Customer Owned Tooling (COT) the signoff was done at the GDS II, or physical level. Today, however we see the trend of RTL signoff instead because of the EDA tools and methodology available. At DACearlier this month I met with Piyush Sanchetiof Atrenta to get an update on what’s new with RTL signoff.


    Continue reading “RTL Signoff Update from #51DAC”