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July 6, 2014June 14, 2019

Coventor Brings More Accuracy & Performance into Design of MEMS Devices

Although MEMS devices in various forms are now found in most electronic devices, predominantly in mobile, automotive, aerospace and many other applications, their major revolution, I believe, is yet to happen. We are seeing rapid innovation in MEMS reflected by their improvements in precision, performance, size reduction, and the continuing evolution of new devices with increasing complexities. The micro level fabrication of MEMS will enable unprecedented use of these into newer and newer semiconductor based electronic devices that will revolutionize the so called IoT arena. MEMS will be essential to IoT products’ ability to connect every aspect of our life, things and happenings around us and provide us ultimate knowledge, control, security through a wide range of devices in many form factors and environments.

The advancement in technology is accelerated when there are supporting tools to accurately model the devices, automate the procedures, quickly simulate, and analyze the designs. I like Coventor’sproducts in catalyzing this race towards reaching the ultimate in MEMS technology; MEMS+ for MEMS+IC design and analysis, CoventorWare for modeling and simulation of MEMS devices and SEMulator3D for process development and virtual fabrication of MEMS and semiconductor devices. I was delighted to look at the new release of CoventorWare 2014 suite that significantly adds into developing new generation of sophisticated MEMS devices. To know more details about the new offering in this release, I had a brief discussion with Steve Breit, VP of Engineering at Coventor. And here is what I learnt about the state-of-the-art new development that happened in CoventorWare 2014.

CoventorWare is a complete suite of tools which allows 2D layout design entry along with process and material information, automatically builds 3D model of a MEMS device, generates mesh, simulates and analyzes to optimize the MEMS device as desired. What we see in CoventorWare 2014 is much improved unique capabilities for high-performance and high-accuracy electro-mechanical and specialty MEMS physics simulations and a novel intuitive interface for fast setup and analysis. The simulators are order of magnitude faster and can handle large meshes on multi-core systems.

Above is an example of modal harmonic analysis of a specialized PZE (piezo-electric) resonator which is more than 10x faster (with 200 DoF and 88 frequencies) compared to the previous release of Coventorware; the speed-up can further increase with increasing number of DoF (Degree of Freedom) and frequencies. These fast simulations are critical for designing high-Q (Quality Factor) and low-TCF (Temperature Coefficient of Frequency) piezo-mechanical resonators. Similarly other specialized solvers such as PZR (piezo-resistance) for PZR sensors and Reynolds and Stokes solvers for gas damping are available.

CoventorWare provides FEM (Finite Element), BEM (Boundary Element) and also hybrid FEM/BEM methods of simulation for simulating various MEMS physics. The FEM simulations can be used for mechanical analysis including robust contact events whereas BEM simulations can be used for electrostatic actuation and capacitive sensing. The hybrid FEM/BEM approach is used for coupled electro-mechanics, and in CoventorWare 2014 it is 5x faster due to optimization for multi-core systems and a new convergence algorithm.

The new convergence algorithm, ‘Accelerated Coupling’, is available via an intuitive new setup dialog that reduces the number of iterations required for convergence thereby reducing the simulation time.

In order to further enhance user experience in designing increasingly complex MEMS devices, the GUI and user interface has been simplified for all kinds of coupled electro-mechanics along with solver progress reporting on the Job Queue tab. A powerful Python scripting interface has been extended to include mesh and material transforms, making it easy to automate studies of sensitivity to design and manufacturing variables.

Steve summarized by saying that a combination of improvements to simulation performance (which includes multiprocessing, specialized algorithms and optimization of field solvers), user interface enhancements and new scripting support for user convenience has increased user capabilities for efficiently designing and simulating a wide range of MEMS devices with increasing set of parameters for varied applications as per requirement. For example, Gyroscopes can have different levels of bias drift precision depending on their application. While consumer applications are fine with low precision, navigation applications will require very high precision. The Gyroscope designs can be affected with multiple parameters such as bias voltage, electrostatic drive force, and physical effects such as quadrature, thermo-elastic damping and anchor losses. Similarly a varied range of effects must be considered when designing other MEMS devices such as accelerometers, microphones, RF switches & varactors and so on.

It was a very interesting and informative interaction with Steve that enhanced my knowledge about CoventorWare in general and CoventorWare 2014 in particular. It’s worth exploring and using if you are thinking of refining an existing MEMS device or designing a sophisticated new one.

Fantasy Tech-Ball and the Intel Rumor Wire

Fantasy Tech-Ball and the Intel Rumor Wire
by Don Dingee on 07-06-2014 at 9:00 am
Categories: Foundries, FPGA, Intel Foundry

Reading Intel analysis lately has been a lot like reading fantasy baseball analysis. Intel should buy Altera. Intel should waive Atom. Intel should fab for Apple. All of those have a near-zero probability of happening IMHO, and yet pundits continue to pitch their version of alternate reality, dealing away product lines and strategies left and right. Continue reading “Fantasy Tech-Ball and the Intel Rumor Wire”

July 6, 2014

An Approach to Clock Domain Crossing for SoC Designs

An Approach to Clock Domain Crossing for SoC Designs
by Daniel Payne on 07-06-2014 at 12:20 am
Categories: EDA

Blogger Pawan Fangaria wrote about Clock Domain Crossing(CDC) a few weeks ago, and so I followed up tonight and watched a webinarabout CDC presented by Ravindra Anejaof Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:

Fast throughput and thoroughness
Ability to debug and fix the source of CDC errors
Handle billions of gates and be considered a signoff tool

Continue reading “An Approach to Clock Domain Crossing for SoC Designs”

July 5, 2014

Solar Leases, How to Not Get Gouged by PG&E

Solar Leases, How to Not Get Gouged by PG&E
by mbriggs on 07-05-2014 at 12:00 pm
Categories: General

This post will be of primary interest to California residents.

If you haven’t looked closely at your PG&E bill, this may ruin your day. If you live in a house larger than a cracker box, and actually use your lights and air conditioning, the rates you pay are exorbitant. If you live in WA you’ll be paying .06-.08 per kilowatt hour. In CA you are probably paying in excess of .30. I like to call this California’s version of hidden socialism. Check out Electricity Prices by State.

PG&E, of course hides this fact. You need to download the pdf detail for your bill, then surf to page 3.

Note that for the crackerbox Tier 1 Allowance, at .13627 per kilowatt hour, I am allowed 352 kWh. This is just about enough to power my computers and my TV. The majority of my usage is at Tier 4, which costs me .35955 per kWh.

Solar Leases

I recently signed on the dotted line for a solar lease. This means that I have committed to paying Vivint Solar, a monthly fee for the next 20 years. I mentioned this to a friend and he said “Are you nuts?. You’ll have a hard time selling your house as you’ll have to include the remainder of the solar lease as part of the deal.” This perception arises because the “solar lease competition” is doing an awesome job discrediting the program. Read about it at http://solarleasedisadvantages.com/. Fortunately Elon Musk’s company SolarCity is in the game, and adding needed credibility to the space.

The way it works is that I pay zerofor the panels, zerofor installation, and zerofor maintenance. I then pay Vivint .14 per Kilowatt hour for all the power the panels produce. They size the system so that it will accommodate approximately 75% of my power needs, so I continue to pay PG&E, but at the Tier 1,2 rates. This works from Vivint’s perspective as they pick up the federal tax credit. There is an annual increase of 2.9%, but the argument is that PG&E will increase prices at a similar or faster rate.

I could have purchased the panels outright, but would have needed to fork out somewhere between $40-75K, and been responsible for the maintenance. Best case payback is 7 years. Since Vivint owns and maintains the panels I really don’t care if the technology changes.

You may have heard from the companies that sell solar panels that you can push your unused power back on the grid, and have PG&E pay you for it. Ha, ha. PG&E in it’s infinite generosity will pay you .02 / kWh for that power.

To me this is a big win, and I’d think that for a future buyer of my house it would also be a win. I also like extending my middle finger to PG&E.

July 5, 2014

July 4th Fireworks

July 4th Fireworks
by Paul McLellan on 07-05-2014 at 9:00 am
Categories: General

It was July 4th yesterday. Fireworks. I didn’t go down to the waterfront to see them in San Francisco this year, I was in a “place” (that might possibly have served beer) having fun. But it reminded me of this a couple of years ago. On July 4th 2012 the San Diego fireworks display, one of the biggest in the world, detonated simultaneously. They fired every single thing at once, or within about 10 seconds. Luckily their protocols were such that everyone was locked down inside bunkers and nobody was hurt even in that worst case scenario (which involves 5 barges spread over nearly 15 miles).

Of course it was a PR disaster. But let’s face it, for everyone who saw it, it will be the most memorable fireworks show of their lives. The press had a field day about “massive hardware failure” but if you are in technology (and if you are not, what the hell are you doing here?) that sounded dodgy. A big hardware failure would result in no fireworks going off at all. Totally believable. But all at once? That has to be a software screwup. And so it proved. A few days later they issued the postmortem. It reads a little like the postmortem on chips that need a respin, everything was checked but somehow something got through. We used the wrong CPF file. The old version of the IP. Whatever.

The report on the fireworks is here (pdf).

Warning: heavy geek factor if you read further!

This reminds me of another screwup when a space vehicle failed to get into orbit around Mars (I think, I’m remembering all this so the details may be slightly different but the basic idea is accurate).

The code was written in Fortran which, unless you are of a certain age, you have probably never used. It was invented in the 1950s when a lot of what we know now…well, we didn’t know. It had a number of convenient features which people though were neat like:

variable names could have spaces in them (that were ignored, in fact all spaces were ignored except in quoted strings). So you could say R AND R (we didn’t have lower case back then). Or, as turned out to be significant, DO 13 I
variables didn’t have to be declared. if you used one then if it started with I-N it was integer and otherwise was floating point. DO13I is thus a floating point variable.
Loops in Fortran were known as DO loops and had a syntax like this:

[INDENT=2]DO 13 I=1,5

which meant execute all the instructions between here and the label 13 with I taking the values from 1 to 5, like a for loop in C. No we didn’t have brackets {} either. Just labels.

Loops were ended with a labelled statement. So that you could GOTO the end of the loop (equivalent to break in C) you could label a CONTINUE statement that did nothing. Whereas jumping to the last statement of a loop if you labelled it would execute that statement. But there was no problem having a CONTINUE statement not in a loop. You wouldn’t get a peep out of the compiler.

So what happened to the spacecraft? Someone put in a typo:DO 13 I = 1.12

with a period instead of a comma. It is all totally syntactically correct. It was a Newton-Raphson iteration to solve a differential equation to calculate the amount of speed required. But with the rules I told you about this was actually:DO13I = 1.12

Namely declare a floating point variable DO13I and assign it the value 1.12 (and never use it again. No we didn’t have Lint type tools back then either. Or tools period).

So instead of the loop running 12 times (to converge on a good value) it ran through once (since it wasn’t a loop, just an assignment statement) and it used the initial approximation. Newton-Raphson is so efficient that it doesn’t much matter what the initial approximation is in most circumstances, nobody makes any effort to get it close. Just use 1. And maybe a couple more iterations if necessary (and yes, I know about double roots, but that is nothing to do with this).

Result. Loss of spacecraft. One character wrong.

Back to fireworks. This video has gone viral so you have probably seen it. A guy flys a quadracopter drone through a fireworks display with an HD GoPro camera. It survives (although takes a few minor hits and lots of stuff flying by). Happy Day-After-Independence-Day

P.S. Someone a decade ago asked me what the Brits do on July 4th. “Nothing, we lost” I replied.

Mentor Graphics @ SEMICON West 2014

Mentor Graphics @ SEMICON West 2014
by Daniel Nenni on 07-04-2014 at 10:00 pm
Categories: ESD Alliance, Events, Semiconductor Services

Mentor is again the most represented EDA company at SEMICON West this year. I strongly advise Cadence and Synopsys to get more involved because EDA may be where electronics begins but semiconductor manufacturing makes all of our hard work come true, absolutely. Paul McLellan, Beth Martin, and I will be blogging live, I hope to see you there!

My good friend Steve Pateras is up first. I worked with Steve at LogicVision, which is one of Mentor’s most profitable acquisitions of all times I’m told. Steve is a great guy (very approachable) so don’t miss this one if you are even remotely involved in silicon test:

Ensuring High Defect Coverage of FinFET Based Designs

Steve Pateras
Marketing Director Silicon Test
Mentor Graphics

Abstract: The semiconductor industry is ramping deployment of FinFET transistors. These devices provide important benefits such as lower static leakage leading to lower power ICs, and high drive currents enabling faster switching at lower supply voltages. FinFETs however represent a fundamental change to the underlying structure of the transistor resulting in an impact on the IC design and manufacturing flows. In particular, FinFET critical dimensions are for the first time significantly smaller than the underlying node size, leading to a growing concern over increased defectivity levels and therefore test quality and cost.

This presentation will introduce the concept of Cell-Aware test, a transistor-level test methodology that overcomes the limits of traditional stuck-at and transition fault models and associated test patterns by targeting specific shorts and opens internal to each standard cell, resulting in significant reductions in defect (DPM) levels. This technique is used to specifically model and target leakage and drive strength related transistor defects that are likely to be common in FinFET devices. The Cell-Aware approach requires only modest increases in test time despite significant improvements in defect coverage, making it a highly efficient and thus pragmatic solution.

Using a Gallery Concept to Optimize an EUV Flow

Dr. Fan Jiang
Product Engineer, Mask Synthesis Solutions
Mentor Graphics

Abstract: While there is debate about when extreme ultraviolet lithography will be ready for production, there continues to be active research and development aimed at improving every aspect of the EUV system, including optical system modeling and correction. Unlike today’s ArF (λ=193nm) lithography, proximity effects aren’t much of a problem to EUV lithography because the wavelength (λ=13.5nm) is much closer to the size of the design features. However, because EUV systems are completely reflective (i.e., uses mirrors instead of lenses) there are new effects that did not exist or were negligible before, such as shadowing and flare, that must be addressed. Associated with these new effects are a range of models and correction techniques used to make up for limitations and inaccuracies in the EUV system, just as there are in today’s lithographic flow. Our research into a variety of these EUV resolution enhancement technologies (RET) indicates the there are many possible combinations of techniques thatmust be considered to create a flow that is optimized for target accuracy and performance (runtime) objectives. To achieve the best flow for specific product lines, lithography engineers need to start with a comprehensive gallery of models and tools that address the various issues that arise in practical EUV flows. This presentation will discuss the specific challenges of reflective EUV systems and demonstrate the variety of modeling and correction techniques that can help engineers meet both accuracy and runtime objectives for their IC manufacturing flows.

The Next Generation Scan Test Diagnosis

Geir Eide
Product Manager
Mentor Graphics

Abstract: Layout-aware diagnosis represented a dramatic advance in digital semiconductor diagnosis software technology. With up to 85% reduction in suspect area and the addition of defect classifications, it cemented the position of diagnosis in use for defect localization, and paved the way for use of diagnosis in yield learning applications. In this presentation, we will present Root Cause Deconvolution (RCD), the next generation diagnosis technology that dramatically improves the resolution in diagnosis results. RCD performs statistical enhancement of layout-aware diagnosis results to identify the underlying root causes of failures. For instance, layout-aware diagnosis may point to a net segment that spans multiple layers as the possible location of an open defect. RCD narrows this result down to a specific VIA in this net segment. This dramatically reduces the FA cycle time by increasing the FA relevance and success rate. It also enables “virtual FA”, the ability to determine accurate defect distributions for a population of failing devices before any failure analysis is performed….

SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

lang: en_US

July 4, 2014August 22, 2024

GlobalFoundries Goes to Semicon West

GlobalFoundries Goes to Semicon West
by Paul McLellan on 07-04-2014 at 8:38 pm
Categories: ESD Alliance, Events, Foundries, GlobalFoundries, Semiconductor Services

Next week it is Semicon West, the big equipment vendor tradeshow. I love to go since EDA and semiconductor and all the stuff we are interested in here at Semiwiki are driven by equipment capabilities, especially lithography. The highest viewed blogs I write tend to be ones on technologies that are just a bit out beyond the stuff people have to worry about today. Is EUV going to happen and when? What about 450mm wafers? Is DSA (directed self assembly) really a thing or an academic toy? E-beam, can it work, are the data rates even feasible? Carbon nanotubes, where are they really? Semicon West is the place to get the best information about all this stuff. I’ll be there (as will Dan).

It is also the place to find out what the foundries are all thinking about. Most chips will be manufactured by foundries after all (outside of the memory business) so it is important. GlobalFoundries have 7 presentations during the next week.

David Duke: Secondary Equipment for Mobile & Diversified ApplicationsMobile, IoT, and other consumer-driven applications are changing behaviors throughout the semiconductor supply-chain. This trend has become noticeable not only at the leading edge, but also for n-2 nodes. Many of these applications rely on Analog, Power and other “More than Moore” devices which, in turn, rely on secondary/legacy equipment for their manufacture.

Les Marshall: Subcomponent Supply Chain for 10nm and BeyondAttendees will hear perspectives from leading edge IDMs and OEMs as well as expectations from critical subcomponent suppliers on how to create a more interactive and collaborative supply chain for greater efficiency, increased technology exchanges, and cost improvements at advanced nodes.

Rohit Pal: Variability Control – A Key Challenge and Opportunity for Driving Towards Manufacturing ExcellenceVariability is one of the biggest challenges when CMOS devices are scaled to meet the demand for portable electronics with increased functionality. The problem is that device sizes have been downscaled to the point where the electrical properties of individual devices are very sensitive to small changes in their materialproperties. A multi-faceted variability reduction approach is needed that comprehends integrates chip design, process and equipment development.

Reed Content: Sustainable Manufacturing Forum: Fabless Considerations in Manufacturing

Ganesh Subramanian: Challenges, Innovations and Drivers in MetrologyHow can we be more proactive in designing the metrology schemes around the introduction of new devices,materials, and components? Efficient yield and stable manufacturing requires good metrology during the HVM ramp, which means it would be desirable to have new metrology andcharacterizationtechniquesavailable early in the R&D process in order to improve cycle times and speedtime-to-market. Certain requirements, such as smaller critical dimensions (CD) and tighter overlay,aredriven by scaling. In some cases, these requirements can be accommodated by incrementalimprovements of existing techniques, but these approaches could be nearing the end of theirextendibility

An Che: Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and BeyondDriven by application and cost considerations, major IC manufacturers have made their transistor technology choices for 14nm (either FinFETs on bulk or SOI, or FDSOI. Beyond 14nm, even more choices will have to be made with respect to non-planar architectures, high-mobility materials, substrate materials, and process modules. Some experts are also looking at disruptive scaling technologies and alternatives to scaling (e.g., monolithic 3D). This session provides an overview of the transistor structures, materials, and process technologies that will need to be developed to get the industry down to 5nm

T.M. Mak: Test Vision 2020Test Vision 2020, formerly ATE Vision, has emerged as the premier workshop in the area of Automated Test Equipment. Attracting record attendance from a broad cross-section of the semiconductor community, the workshop features a compelling line-up of papers, keynotes and panel participation from leaders in the industry. This year, once again the workshop will be held in conjunction with SEMICON West and will examine where the test industry is heading and provide a forum for discussing the directions and solutions for emerging problems.

Full details on these sessions (and all the rest) here.

It’s Always Good If the Customer Is Arguing

It’s Always Good If the Customer Is Arguing
by Paul McLellan on 07-04-2014 at 2:41 am
Categories: General

I’ve never been in sales. Never “carried a bag”. But I have run sales forces and I have spent a lot of time in marketing, guiding sales forces. Well, herding cats comes to mind, but cats don’t have commission plans. Engineers say sales people are emotional, and ego-driven, but change their commission plans and sales people turn on a dime. They reschedule their meetings for the following week. Tell an engineer their baby project is killed and they will grieve for weeks. It is engineers who are emotional not sales people. I’ve managed both, more on the engineering side probably, being an engineer by background.

So one thing I have noticed is that new salespeople complain that there is a product or engineering problem when the customer is pushing back. Of course, if it is an existing customer complaining about some problem with a tool the purchased then it can be a genuine problem. EDA is such a fast churning industry that no tool is ready for release…when it has to be released. It has never seen good test data. When FinFETs came along, how much FinFET test data was available for EDA companies to test their stuff on. None, would be a pretty good answer. Not much maybe closer to the truth. CTO’s of semiconductor companies used to tell me when I worked at Cadence that we should have better software quality and I told them to use the prior release. It was pretty solid. Of course they couldn’t for the current process node, but the reality in EDA is that the software was developed, like, yesterday. It won’t be stable until a lot of designs have been run through. The choice is wait (which some people can) for other people to run all those designs through, or live with the instability that goes with being one of those early guys through. But they argue about the issues all the time with their salespeople.

So I tell members of the sales team that it is always good when the customer is arguing. After all, think of the last time some salesperson tried to sell you solar panels, or a swimming pool. If you were not interested you would shut up and try and get them to go away. If you were, then you would say that the price was too high, or the pool was the wrong size. It’s always good if the customer is arguing.

It is not restricted to leading edge stuff, but there seems to be more argument there because it gets the most visibility. But ultimately IC design is a strange ecosystem to sell into. As a friend once said to me, EDA is the “only environment that when you try and sell them a car they take the cylinder-head off and check the valve timing.” If that isn’t arguing then I don’t know what is. So when they make the effort to “check the valve timing” then it is not a criticism of the engine/tool but a sign that they care enough to check, they are interested.

But it’s always good if the customer is arguing!

Intel is Speaking @ SEMICON West 2014!

Intel is Speaking @ SEMICON West 2014!
by Daniel Nenni on 07-03-2014 at 8:00 am
Categories: ESD Alliance, Semiconductor Services

The SEMICON West website has a nice “speakers” option where you can search by company and see who is talking about what. I’m always interested in what Intel has to say (they are still the leading semiconductor company) so here is the line-up for next week:

Intel Sanchali Bhattacharjee Subcomponent Supply Chain for 10nm and Beyond

Intel Janice Golda Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond
Wednesday, July 9, 2014
9:00am-12:00pm
Moscone North, Hall E, Room 131
Driven by application and cost considerations, major IC manufacturers have made their transistor technology choices for 14nm (either FinFETs on bulk or SOI, or FDSOI. Beyond 14nm, even more choices will have to be made with respect to non-planar architectures, high-mobility materials, substrate materials, and process modules. Some experts are also looking at disruptive scaling technologies and alternatives to scaling (e.g., monolithic 3D). This session provides an overview of the transistor structures, materials, and process technologies that will need to be developed to get the industry down to 5n

According to LinkedIn: Janice Golda manages an organization responsible for creating strategies and working with Intel’s lithography pattering, metrology, mask, and process/product debug equipment suppliers and sub-suppliers to develop and deliver equipment and materials meeting Intel’s roadmap requirements for technology, affordability, and velocity. I will definitely attend this session. I do plan on being around for 5nm, absolutely.

Intel Tim Hendry Breakthrough High Volume Manufacturing Innovations: New Paradigms for the Road Ahead

Intel Sunit Rikhi SEMI/Gartner Market Symposium
Monday, July 7, 2014
1:00pm–5:30pm
San Francisco Marriott Marquis, Golden Gate A
The SEMI Market Symposium, co-sponsored by SEMI and Gartner, provides a midyear market update as well as a forum to discuss pertinent business issues. SEMI and Gartner will present market forecasts and analysis for the semiconductor, capital equipment and semiconductor materials industries.

We all should know Sunit. He is Vice President, Technology and Manufacturing Group; GM, Custom Foundry at Intel. In fact, Sunit has been at Intel for as long as I have been working in Silicon Valley. He started as EDA Software Manager in August 1984. Sunit and I have spoken before, he is a great guy and knows semiconductor design and manufacturing from the ground up:

Software Engineering Manager, EDA
Engineering Manager, Mask Operation
Business Development Manager, Mobile Computing
Director, Logic Technology Automation
Vice President, Technology & Manufacturing Group; Director, Advanced Design
Vice President, Technology and Manufacturing Group, GM, Custom Foundry

If you do a search on LinkedIn for “Intel Custom Foundry” you can see the rest of his team, about 500 of them. The common denominator is their long careers at Intel.

Sunit will be speaking on:

“Intel Custom Foundry as a relatively new player in today’s Fabless ecosystem offering custom manufacturing services that include wafer manufacturing and beyond. The talk will highlight the challenges and opportunities of winning in a highly competitive environment, of being inside the world’s leading IDM, and of leading the innovation in design at the leading edge of Moore’s Law.”

No way I’m missing this one! Hopefully he has read our book “Fabless: The Transformation of the Semiconductor Industry”. Remember, to know where you are going you must know where you have been. I will bring a signed copy for Sunit, absolutely.

In Case You Missed #51DAC

In Case You Missed #51DAC
by Daniel Nenni on 07-02-2014 at 9:50 am
Categories: EDA, Events

This will probably end up being the most memorable DAC for us since Paul and I signed hundreds of copies of our book “Fabless: The Transformation of the Semiconductor Industry”. I’m not sure how we are going to top that next year but I’m confident we will think of something. If you want to catch up on the live blogs from the last three conferences check the Design Automation Conference ( DAC ) Wiki.

It is interesting to see the DAC numbers over the last three years. If you have more DAC data that you would like included feel free to edit the wiki or post it in the comments section and Daniel Payne or I will add it. Comments on how to improve DAC would also be appreciated. It is important to document past conferences to make sure we prepare for the next one. In my experience most companies that fail usually fail at the future so let’s make sure that does not happen to our beloved DAC.

It is interesting to see the conference numbers over the last three years from the wiki:

Location: San Francisco, CA 2014
Attendance:

Full conference passes – 2,393
Exhibits-only passes – 1,650
Exhibitors booth staff – 2,658

Location: Austin, Texas 2013
Attendance:

Full conference passes – 1,589
Exhibits-only passes – 2,364
Exhibitors booth staff – 1,998

Location: San Francisco, CA 2012
Attendance:

Conference attendees – 1901
Exhibits-only passes – 2783
Exhibitors booth staff – 2704

I had predicted a blow-out attendance this year and it did not happen!?!?!? Conference passes were up, which is great, but what happened to the exhibit only passes? Do we not love DAC anymore?

The DAC committee is also looking for your feedback. There is a new General Chair in town and she will be blogging once a week for the next 52 weeks to give you a behind the scenes look at how this conference gets ready for June 2015! This is a VERY brave thing to do! It is for the greater semiconductor good, so please support this effort.

Anne Cirkelis the General Chair for the 52nd DAC and a Senior Director for Technology Marketing at Mentor Graphics. Prior to joining Mentor Anne held marketing management positions at Analogy, Viewlogic, and Berner & Mattner. Anne holds a Master’s degree in Business Administration with an undergraduate in Metallurgy from RWTH Aachen, in Germany. She has been actively involved on the Executive Committees for DAC and DATE as well as the Program Committee for Embedded World.

Here is what Anne has thus far:

#52DAC will again be in beautiful San Francisco before returning to Austin in 2016. Let’s figure out how to make this coming DAC bigger and better. A $300B+ industry that is critical to modern life is depending on it, absolutely.
The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. Members are from a diverse worldwide community of more than 1,000 organizations that attend each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities.