WP_Term Object
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 513
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 513
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158

Dr. Cliff Hou, TSMC VP of R&D, Keynote

Dr. Cliff Hou, TSMC VP of R&D, Keynote
by Daniel Nenni on 02-16-2014 at 9:00 am

 This will be my 30[SUP]th[/SUP] Design Automation Conference. I know this because my first DAC was the same year I got married and forgetting how many years you have been married can cost you half your stuff. I have known Cliff Hou for half of that time and he has proven to be one of the most humble and honorable men I have worked with, definitely.

Cliff started at TSMC in the PDK group and produced the first TSMC Reference Flow which really was the starting point for the fabless semiconductor ecosystem (Grand Alliance) that we have today. Cliff then took over the TSMC IP group before becoming the Senior Director at Design and Platform which included the PDK, IP, and other design enablement Groups inside TSMC. In 2011 Cliff was appointed TSMC’s Vice President of Research and Development. Clearly Dr. Cliff Hou is rising star in the semiconductor industry and it has been an honor to work with him.

Cliff was our choice to write the foreword to the book, “Fabless: The Transformation of the Semiconductor Industry” as he and TSMC led this transformation. The foreword alone is worth the price of the book and I can’t wait to get Cliff to sign a copy for me at #51DAC where he will be keynoting:

Industry Opportunities in the Sub-10nm Era

The human thirst for connectivity and experience, as enabled by the electronics industry and the ongoing march of Moore’s Law, has already brought, and will bring even more, profound changes in way we interact with the world and each other. This profound enhancement of the human experience enabled by constant mobile connectivity, the Cloud, and sensors, brought to an ever widening worldwide audience, will bring untold opportunity to all of us here at DAC.

All of these changes demand continued chip and wafer-based scaling to deliver the power and performance necessary to enable wondrous, new applications. In less than two years we’ll be in production at 10nm, and shortly after 7nm, all made possible by a “Grand Alliance” of design ecosystem, equipment and material suppliers. At the same time, a new paradigm is being realized: heterogeneous silicon integration combining chips from multiple process technologies with 3D packaging to deliver compelling economics for a “System in a Si Superchip.”

New design techniques will be required for those applications becoming reality, including how 10nm, and 7nm will support those requirements, new manufacturing techniques, and the benefits they will provide. The introduction of 10nm and 7nm processes will alter today’s ecosystem while opening greater EDA and IP opportunities, and present new system and chip design challenges such as near threshold design, thermal and battery limitations, and 3D IC considerations.

IC designers, ecosystem providers and foundries have been committed to open innovation and mutually beneficial teamwork for many process technology generations, but success in the sub-10nm era will require unprecedented levels of collaboration and cooperation between all of us here at DAC. Our teamwork will drive industry progress, and the more we “collaborate to innovate,” the more successful our customers and all of us will become.

More Articles by Daniel Nenni…..

lang: en_US

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.