RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)
Semiconductor Expert Forum

Posted on

Kilimanjaro

Kilimanjaro
by Paul McLellan on 09-05-2014 at 7:01 am
Categories: General

For several weeks I have been trying to put out one blog per day rather than being like London buses where there are none for ages and then three come along at once. Or SFMuni buses for that matter. This week has been more of the same. Well, OK, I skipped labor day because…labor day. All you IC types will be busy eating chips not designing chips.

But actually I’ve been in Africa all week with three friends. My first time here unless you could Tunisia and Morocco which are technically Africa but not really. I am in Tanzania. It is easier to get here than you might expect. Fly direct to Amsterdam and there is a direct flight from Amsterdam to Mount Kilimanjaro airport and Dar-Es Salaam.

The connection was riskily tight so we spent a day in Amsterdam. The new Rijksmuseum is incredible if you find yourself there. I haven’t been since I was about 20 going around Europe on Interail. It was closed for a ten-year refurbishment and re-opened last year. Also, if you find yourself in the Netherlands, make sure to go to an Indonesian restaurant that serves rijstaffel (rice table). Indonesia was a Dutch colony so in the same way that Britain has incredible Indian food, and France has great Moroccan food, the Netherlands has great Indonesian food. Rijstaffel consists of many small dishes and some rice. It is best with a lot of people. In the Cadence days I often had to visit Philips in Eindhoven since I was their executive partner and the local sales team would always take me out for it.

We arrived in Mount Kilimanjaro airport last night late. I don’t think I’ve ever been on a 9 hour flight before where you end up pretty much in the same time zone as you started (one hour difference). I’m more used to flying to Europe or Asia from San Francisco with 8 or 9 hour time differences. The plan is to go on a safari for a couple of days and then on Friday we start our assault on Kilimanjaro. It starts in the heat at about 6000′ and ends up in sub-zero temperatures and snow on the summit which is nearly 20,000′ (19,341′ if you want the exact number). The lack of oxygen on the final day is apparently a challenge. I hope we all manage to make it. It is a lot higher than Mount Whitney, my previous highest ascent.

More news and photos later.


More articles by Paul McLellan…

Posted on

SmartScan Addresses Test Challenges of SoCs

SmartScan Addresses Test Challenges of SoCs
by Pawan Fangaria on 09-04-2014 at 4:00 pm
Categories: Cadence, EDA

With advancement of semiconductor technologies, ever increasing sizes of SoCs bank on higher densities of design rather than giving any leeway towards increasing chip area and package sizes; a phenomenon often overlooked. The result is – larger designs with lesser number of pins bonded out of ever shrinking package sizes; the design size per pin count keeps increasing. This is a challenge, test engineers take silently, but how to keep the test cost down without diluting the test reliability? The test vectors to test the increased functionality on chip will increase and not decrease. So, smart techniques are needed in test engineering too to test larger designs with same or lesser number of pins at the same or lesser cost of testing.

Reducing ATPG patterns test time and test data volume, which can be achieved by scan test compression specific DFT (Design for Testability) architecture, can significantly contain the overall test cost. The compression structure which uses a broadcast/XOR network of scan-input pins, XOR/MISR (Multi Input Shift Register) logic on the scan-output pins and a number of scan channels (stumps) connected to compression logic. When the scan chains are properly balanced then they can provide test time and test data volume reduction close to the target compression ratio (i.e. the ratio of number of scan channels to the external full-scan chains). A compression efficiency of 100-200X has been observed provided the scan data pin pairs remain high. The moment scan data pin pairs are reduced to five or lesser, the compression efficiency and fault coverage go down drastically; at the scan input data correlation increases and at the scan output data aliasing increases, resulting into failures being masked out, thus affecting the reliability of test. So, what’s the alternative given that LPCT (Low Pin Count Test) designs are the way of life in the SoC world of testing?

I was pleased to know about Cadence’sEncounter Test SmartScan technology that offers a robust, highly efficient and reliable scan compression solution for LPCT designs.

It utilizes two N-Bit shift registers for de-serializing and serializing the compressed data, thus requiring a single pair of scan-in and scan-out pins. After fully loading the input shift register with the compressed data (which takes N cycles for a single bit-slice of the scan channels), the scan clocks are fired and data is transferred into the internal scan channels. The output shift register captures the response data in parallel from the internal scan channels and shifts it out serially.

The test patterns are generated using N-bit parallel scan interface by bypassing the de/serializer registers. These patterns are re-targeted to the Encounter Test SmartScan serial interface by translating each scan cycle of the parallel interface pattern into loading and unloading the de/serializer registers. The parallel interface pattern can also be directly applied at the automated test equipment (ATE) provided the chip package has those pins for test purposes. The test control signals required to switch between parallel and serial interfaces can be internally decoded from on-chip test logic.

This arrangement reduces scan data correlation to large extent which is not possible with only a few pins driving the compression logic directly. The pattern quality is consistent requiring a single-pass ATPG run, because the internal scan configuration is identical between the serial and parallel interfaces. Debugging and diagnosis is easy to isolate tester failures.

The Encounter Test SmartScan logic is verified in the context of post-ATPG pattern retargeting which avoids any re-iteration of DFT verification and ATPG flows (due to any error in its implementation) which could be expensive.

Above are the results of fault coverage and test time on an automotive design. It can be clearly seen that SmartScan methodology provides quality close to full-scan (i.e. with single scan chain) at a much lower test time compared to full-scan. The quality of conventional XOR compression is drastically lower and unreliable.

The Encounter RC cockpit provides a seamless environment for insertion of SmartScan logic into the front-end design netlist. A single logic-synthesis and DFT-insertion run script is used to achieve the best area, power, timing, and test coverage. The RTL Compiler also generates all downstream run scripts to verify design equivalence with Cadence Conformal LEC, generate parallel interface patterns and retarget them for Encounter Test SmartScan interface, and provide fault coverage metrics with Encounter Test True-Time ATPG.

The Encounter Test SmartScan methodology provides the much needed solution for LPCT designs in automotive, MCU and mixed-signal applications at significantly reduced test cost and high quality of test and fault coverage. A further detailed description can be obtained from a whitepaperwritten by Pradeep Nagaraj at Cadence.

More Articles by Pawan Fangaria…..

Posted on

Synopsys VC VIP for Memory

Synopsys VC VIP for Memory
by Paul McLellan on 09-04-2014 at 7:01 am
Categories: EDA, Synopsys

Synopsys have been gradually broadening their portfolio of verification IP (VIP). It is 100% native SystemVerilog with native debug using Verdi (that was acquired from SpringSoft last year, now fully integrated into Verification Compiler). It has native performance with VCS. Going forward there are source code test suites.

Most of Synopsys IP has been focused on buses and interfaces such as AMBA, PCI, ethernet and so on. See the table below. In a major change they have a growing portfolio of VIP for memories. This is a market that has historically been dominated by another company (famous for parties at DAC in case you need a hint).


As Synopsys pulls all their verification together in a much more seamless environment under the name Verification Compiler, making everything run seamlessly together has become increasingly important. The initial focus has been on DDR3/4 and LPDDR2/3/4. They are not making any more announcements at the moment but for sure they are working on continuing to broaden the portfolio to cover things like flash.


The picture above shows how all the moving parts go together. The primary differentiators of the Synopsys approach are:

  • Based on proven SystemVerilog VIP technology and base class library

    • Simplified use-model and ease-of-use for UVM testbenches
    • Strong foundation of proven base classes
    • Integrated with Protocol Analyzer
  • Configures to Specific Components

    • Vendor memories
    • Includes DIMM, RDIMM, LRDIMM, UDIMM
    • DIMM logic + buffers
  • Validated against internal SNPS memory controllers and customer designs

The memory VIP has the features you would expect such as being able to bypass memory initialization to reduce simulation time, direct access to the memory to examine or alter contents, error injection and exception testing, skew injection, protocol and timing check. The functional coverage is fully integrated into the VIP and protocol verification plan.

As an example, here are the DDR3/4 VIP features. Not being a in-depth memory expert there are one or two things that I am not sure what they are, such as fly by delay. It think it is the tuning needed at these high speeds but it also sounds like being 8th in line for takeoff at SFO.

More details on all Synopsys VIP is here, including datasheets for the memory VIP.


More articles by Paul McLellan…

Posted on

A couple of misconceptions about FD-SOI

A couple of misconceptions about FD-SOI
by Eric Esteve on 09-03-2014 at 9:59 am
Categories: FD-SOI, Foundries, STMicroelectronics

We have extensively discussed in Semiwiki about FD-SOI technology, explaining the main advantages (Faster, Cooler, Simpler), sometimes leading to very deep technical discussions, thanks to Semiwiki readers and their posts. I have recently found an article “Samsung & ST Team Up on 28nm FD-SOI”. This article includes many quotes from so-called “analysts” or experts, that I will share and comment with you in a minute. Why taking the time to do so? Because some of these quotes are just simply wrong!

First Quote (in theory)
Also part of the enticement to designers wanting to dive into FD-SOI is that staying with 28nm mode means, in theory, no new non-recurring engineering costs. In other words, the 28nm masked set transfers to the 28nm FD-SOI and no $50-million-plus redesign needs to happen as you would see with a jump to new process node.

If you read and trust this assertion, you may jump to one of the ASIC supplier, ST or Samsung, supporting FD-SOI technology, bring your existing SoC mask set in 28nm bulk and be quite frustrated. At first, the design rules may not be compatible at all: FD-SOI is derived from 28nm HKMG gate-first process, when most of the 28nm bulk ASIC technologies are based on gate last (TSMC for example). Even if the existing design targets 28nm HKMG gate-first process, a new layout would be required to be adapted to some FD-SOI specificities like wells configuration and polarization. Porting an existing design from 28nm Bulk to FD-SOI with no layout modification is not realistic, furthermore it would be a mistake! If you want to take full benefit of the various FD-SOI advantages, you certainly don’t want to miss the capability of using the Forward Body Bias (FBB) effect. With no layout modification, you could not implement the polarization scheme and not benefit from FBB.

Just take a look at the above table. Applying FBB allow reducing maximum power consumption (dynamic + leakage), up to 31% for the same technology node (14FD-SOI) and slow conditions… and up to more than twice power consumption for the device in 28HPM with ASV. This power consumption reduction is almost magic, but it is unrealistic to think you can blind port a bulk design to FD-SOI, you will need a new mask set.

The latest point about porting an existing design: ASIC supplier like ST has automated the porting, creating scripts which translate schematics and automatically modify layouts. Thus the automated migration path allows porting an existing IP in ½ (half) to 1/3 (one third) of the time it would have required to port the IP in a new technology. Finally, the design must be tuned-up in order to have correct electrical behavior.

To summarize: for an existing design on bulk, if you want to benefit from the better power consumption (or better performance) linked to Forward Body Bias capability on FD-SOI, you will have to modify the existing layout, thus create a new mask set. The porting can be automated and the result must be tuned-up to have correct electrical behavior.

Second quote (you don’t get the strength)
Kevin Krewell of Tirias Research told EE Times. “FD-SOI offers power benefits but you don’t get the strength.” He explained that the process does work well for wearables where the idle power is most important. FD-SOI gives just enough performance to handle a wearable’s work and small display but it reduces the power to extend the battery life (…)

I love the second quote: it’s a mix of true fact (FD-SOI offers power benefits) and completely wrong interpretation (FD-SOI gives just enough performance to handle a wearable’s work and small display) of this fact. We have written a blog to address such interpretation, If you think that FD-SOI is for low performance only, but it could be wise to address this point again. At first, we have mentioned in Semiwiki some ASIC designed on 28nm FD-SOI targeting performance hungry networking application and you can check in this recent blog for the mention of ST design-win of a communication infrastructure ASIC in 14nm FD-SOI… not really a wearable device!

Yes, you can get the strength with FD-SOI technology. Moreover, you can compensate the slow process corners and avoid doing binning (binning from Wikipedia: “by reducing the clock frequency or disabling non-critical parts that are defective, the parts can be sold at a lower price, fulfilling the needs of lower-end market segments”), improving the SoC profitability. Eliminating “Slow” process corner device is possible, but extremely costly as a chip maker pays for the complete wafer. Using adaptive supply voltage (ASV) is a way to keep high performance at the same level for any chips, even coming from a slow process corner. Using forward body bias (FBB) can be a way to reduce the SoC power consumption, or to increase performance, at your choice.

In fact, using FD-SOI technology to design for wearable devices, or for smartphone is certainly a good option, thanks to the performance efficiency offered by the technology. But that doesn’t mean that an ASIC built in FD-SOI technology “don’t get the strength” and is limited to low power/low performance system. Speaking about an existing ASIC in bulk technology, you will benefit from FD-SOI advantages without doing a full redesign, by doing a simple porting. The effort is comparable to this done in the past to shrink a SoC, requiring a new mask set, like for a shrink…This effort will be largely paid by the power AND performances benefits given by FBB, unique to FD-SOI.

The quoted article can be found here

From Eric Esteve from IPNEST

Posted on

Quicklogic Delivers First Wearable Sensor Hub with Under 150uW Standby

Quicklogic Delivers First Wearable Sensor Hub with Under 150uW Standby
by Paul McLellan on 09-03-2014 at 9:00 am
Categories: FPGA, QuickLogic

I have talked before about how the Internet of Things (IoT) doesn’t require enormous power-hungry SoCs. We all accept, or at least put up with, having to recharge our phones daily. But smart pedometers (or whatever a good name for Fitbit-like products are) had better last for a week or two between charges.

Today, Quicklogic announced the ArcticLink 3 S2 platform, which is the second customer-specific standard product (CSSP) on its sensor hub roadmap. Of course as you would expect it is better. It has four times the computational performance, four times the on-board algorithm capacity and eight times the buffer storage of the previous generation, while consuming over 1/3 less power. The standby power at 1.2V operation is a miserly 150uW. With those specs it has capacity to store 3 weeks of data. It is completely pin-compatible and software-compatible with the previous generation.

The part falls into the sweet spot between the application processor approach, using entirely software, which is much too power hungry. On the other hand, a fixed function ASSP doesn’t always have enough flexibility to adapt sensor hub algorithms for emerging applications. The new part is both adaptable by changing the hardware (it is a programmable device in the FPGA sense) or the software (it is also a programmable device in the microprocessor sense).

The ArcticLink 3 S2 is available in CSSP and Catalog CSSP variants. The CSSP variant allows OEMs the chance to develop customized versions of the S2, and choose from QuickLogic-developed, 3[SUP]rd[/SUP] party, and/or OEM-developed sensor algorithms to address specific end product requirements for best-in-class performance. The first Catalog CSSP variant, called the ArcticLink 3 S2 Gesture and Context Catalog CSSP, provides out-of-the-box support for gestures such as tap-to-wake and rotate-to-wake, along with providing enhanced context and significant motion detection, sensor calibration functions, and enhanced pedometer (including differentiation and step counts of running, jogging, and walking.)

Instead of giving you all the detailed specs (which are on the datasheet, see below), here are the algorithms that are supported out of the box:

  • Device Motion: Shake, Rotate, Translate
  • Device Carry: On Person, Not on Person, In Hand Front, In Hand Side, In Pocket
  • User Activity: Sitting, Standing, Cycling, Walking, Jogging, Running (including individual step counts)
  • Transport Contexts: In Car, In Elevator, On Stairs, On Bike
  • Gestures: Tap-to-Wake, Rotate-to-Wake, Lift-to-Wake, Optical Gesture
  • 9-axis Sensor Fusion: On device or shared with AP/MCU
  • Heart Rate Monitor: Support for PPG-based sensors, including Beats Per Minute (BPM) and Interbeat Interval (IBI)

Historically Quicklogic have been working with Sensor Platforms and other partners. With the acquisition of Sensor Platforms by Audience Semiconductor, Quicklogic have decided to become more self-sufficient. In addition to continuing to work with partners, Quicklogic have built up a team to do algorithm development internally. There is a sort of cottage industry of small algorithm companies so consolidation and acquisition looks like the order of business going forward for now.

The name is not public, but Quicklogic have been working with a top ten smartphone supplier during Q1 for a wearable product. This is a particularly exciting design win. This customer has high brand recognition and all of the algorithms used in the design were developed by QuickLogic.

More details, including a datasheet, are available here.


More articles by Paul McLellan…

Posted on

Momentum Builds For 64-bit ARMv8-A

Momentum Builds For 64-bit ARMv8-A
by Eric Esteve on 09-03-2014 at 2:55 am
Categories: Arm, IP

No doubt about it, the summer break has ended, it’s time for releasing big announcement, like this one from ARM “Momentum Builds For the Next Generation of ARM Processors”. In fact, the key information is about ARMv8-A market adoption. A total of 27 companies have signed agreements for the company’s ARMv8-A technology as industry momentum builds for greater compute capability across a wide range of applications. The ARMv8-A silicon partners include:

  • All of the top 10 companies who sell application processors for smartphones
  • 9 of the top 10 application processor companies for tablets
  • 4 of the top 5 companies that provide chips for consumer electronics (including DTV and STB)
  • 4 of the top 5 companies that provide chips for enterprise networking and servers
  • 8 silicon vendors from Greater China

If ARMv8-A architecture is still compatible with 32-bit, this momentum demonstrates the continuing strength in demand for 64-bit-capable ARM Cortex®-A50 processor family and ARMv8 architecture licenses. If we look back in October 2013, one comment related to the launch of Apple 64-bit A7, from Qualcomm executive “”I know there’s a lot of noise because Apple did [64-bit]on their A7. I think they are doing a marketing gimmick. There’s zero benefit a consumer gets from that,” has shacked the mobile semiconductor market for some time… until Qualcomm put out a statement in which it walked back Chandrasekher’s comment and called it “inaccurate.” Moreover Qualcomm has quickly announced in 2014 the launch of 64-bit Snapdragon application processor. According with Anandtech, “Like the previous 64-bit announcements (Snapdragon 410, 610 and 615), the 808 and 810 leverage ARM’s own CPU IP in lieu of a Qualcomm designed microarchitecture. We’ll finally hear about Qualcomm’s own custom 64-bit architecture later this year, but it’s clear that all 64-bit Snapdragon SoCs shipping in 2014 (and early 2015) will use ARM CPU IP”.

Two facts here: Qualcomm is using ARM CPU IP and a 64-bit architecture! In fact, we don’t really know if the smartphones sold today, build around a 64-bit application processor, will take full advantage of the 64-bit architecture. As all the existing software has been designed for 32-bit, it may take some time to develop for 64-bit architecture. But it would certainly be a strong marketing mistake to develop an application processor based on a 32-bit architecture only to target smartphone or tablet…

ARM’s market share in mobile is incredibly high with 95%, and this is a well-known fact. More surprising is ARM penetration of the consumer electronic and enterprise networking market segments. From the top picture, we see that ARM has licensed the 64-bit ARMv8-A to 4 out of 5 market leaders, in both segments. Historically, ARM was not so strong in the consumer electronic application like Digital TV and Set-Top-Box (STB). The green and orange circles (above picture) illustrate the growing penetration in DTV and STB applications. When a customer makes the decision to buy an ARM license is just the starting point of a rather long process: SoC design, prototyping, S/W development, system validation, production ramp-up… The overall process can take anytime between 18 months to several years, and the royalty part of the revenue is linked to SoC devices shipment. In the market segments where ARM is growing penetration, like DTV, STB or enterprise networking, the license design-win show that there is room for market share growth for royalties linked to production shipment.

Another specific information should be highlighted: 8 silicon vendors from Greater China are ARMv8 partners. At first, this is one of the various illustrations showing that silicon vendors from Greater China are quickly closing the gap with their competitor from the rest of the world. As of today, the application processor chip maker from Greater China ship production IC in 40nm node, being one technology node late compared with their competition. But they are moving to 28nm for the new developments. They represent a large growth potential for production volume based royalties for ARM. And the adoption of 64-bit ARMv8 architecture will allow these silicon vendors to target various computing intensive market segment on top of the mobile phone only, like mobile computers, DTV, STB, servers or networking.

Eric Esteve from IPNEST –

More Articles by Eric Esteve…..

Posted on

Google Glass with purpose, not just another smart wear

Google Glass with purpose, not just another smart wear
by Pawan Fangaria on 09-02-2014 at 4:00 pm
Categories: Mobile

Last year or earlier (when it was in the making), when I first heard of Google Glass, I was of the opinion that it’s yet another device with a screen in front of your eyes, with wearable glasses through which you can see the virtual extension of reality you are interacting with (here is a demo); a technology called Augmented Reality (AR) which also allows to see through any object and collect more information about it; for example features of a car you liked, information about a book or food in a restaurant, it can also provide you the meaning of difficult words scanned (through an in-built scanner) from a newspaper or magazine, or you might have an intension of spying on something. I guess most of us have seen the popular Sixth Sense videoon technology developed at MIT Media Labbased on AR, it’s amazing. So, well, my perception was that it’s better and more exciting than other wearable devices.

But when I looked at this technology from Googlemore closely, I realized it’s not just a smart wear, it’s with some real, real, valuable purposes in human life. Again by connecting the dots in Google technologies, the way they are organized and may be added further in future, one can easily make out that Google Glass has been conceived with real good purposes with a long term view.

Before getting into how best it can be used, let me quickly recap about what’s there inside it. Of course sensor enabled touchpad on the side of the Google Glass which controls its activation and screening of the events, Wi-Fi or Bluetooth, a camera, speakers, microphone, an advanced LED illuminated display, a voice synthesizer and controller which enables the device to operate on voice commands and a transducer near the ear to receive voice response from other sources. The device can also be activated by tilting your head 30[SUP]0[/SUP] upward (detected by a gyroscope inside) and say “O.K. Glass”. Then there are interesting apps with Google Glass such as Google+, Gmail, Google Maps and Google Now which provide it ultimate power of navigation and information exchange. Also, there are many 3[SUP]rd[/SUP] party apps which are active on Google Glass. Google with its Mirror API and Glass Development Kit has left the ground open for developers to innovate and build apps for different purposes such as exercise, cooking, sharing on social networks, face recognition, photo manipulation, travel, text translation etc.

Now talking about the usages of Google Glass, rather than its conventional usages (e.g. on the move hands-free voice command to take a picture, record an event, chat on video, attend a conference using Google Hangout,or even compose an e-mail by dictating the content, adding attachments and send automatically through the smartphone in your pocket) I would like to talk about the real value added services it can provide to our society. Imagine how prudent Google was to come up with the ergonomics of this hands-free device to be put on your temple like a spectacle. Your face with vital sense organs is the most powerful part of your body to make intelligent moves to operate a device like Google Glass hands-free. Now think of the operations or situations in which your hands are tied-up elsewhere and you need this device to work intelligently on your voice commands and your head movement. Here are some of those which are already being practiced and some which we can anticipate –

A surgeon while doing surgery can just ask for vital information from patient’s data stored in a computer, CT scan, cardiograph or ultrasound images, displayed on her screen. The live surgery procedure can be relayed to other specialist doctors at their desk for on-line review and quick suggestions. Of course live video recording and photographs of internal parts of organs (which is otherwise not possible) can be taken and specific information embedded with them for record purposes and further teaching to medical students.

It can provide much needed independence to disabled. The Google Glass can provide direction, guidance, information to a person on wheelchair without needing another person’s help. She can just put on her Google Glass and be on the move to explore the world at her own will and commands and not depend on anyone. It’s her world with Google Glass as a lifetime companion. Google Now has predictive software that can provide live information to her about the traffic and weather conditions of the place she wants to visit. If it’s a baseball game somewhere and traffic is bad, Google Now can provide the latest updates and scores about that to her at home.

A recent app added on Google Glass is SMARTSign which helps parents communicate with their hearing impaired children in great way through sign language. Of course, this technology can also be used to teach sign language to normal children.

Further, I guess, the Google Glass can also be of great help to blinds in guiding their way. She can just provide voice command for her destination and the Google Glass can keep guiding her through the way by conveying the messages into her ears through the transducers.

Although there has been criticism about the possibility of privacy invasion by Google Glass, for which I guess some solution should emerge, it’s a greatly convenient device for security, police and secret services personnel. A security officer can scan through a large crowd and pin point suspected culprits or terrorists at particular functions with such gatherings. A detective agent can investigate a crime spot which may be inside a building, a metro rail station, a hotel or hospital, from a distance. She can spot unusual activities at important places, such as airports, embassies etc.

Business personnel or state representatives while visiting different countries using different languages (spoken and written) can make great use of Google Glass. It can record the speech in different language, translate it into English within moments and flash on the screen for its wearer to understand the message and respond appropriately. The same process can repeat in the Google Glass of the other party, thus making communication easy and fast. Similarly the Google Glass can help in scanning and translating road signs, messages displayed in common areas such as airport and hotel and deciphering any alert signal.

Although you may never get lost with a GPS chip and Google Maps in your Google Glass, the Google Glass can help you in great way when you are in distress. Imagine you fell from a height while on an adventure trip or met with an accident, and you are not able to move your arms or legs, there is high probability that your tiny Google Glass is intact (it’s made with a strong frame). You can ask your Google Glass to record your location and voice message for help and send to police and friends.

I could go on writing more, but would like to stop here and leave it for the audience to guess and comment on more usage. After all, Google during its debut introduction of the Glass, asked from consumers about how they would use it. So, there could be more surprises in store!

More Articles by Pawan Fangaria…..

Posted on

Managing Stress in 3D

Managing Stress in 3D
by Beth Martin on 09-02-2014 at 1:32 pm
Categories: EDA, Siemens EDA

A new publication on mechanical stress in integrated circuits, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D at Mentor Graphics, has just been released by AIP Publishing. “Stress-Induced Phenomena and Reliability in 3D Microelectronics” includes 14 key papers from four international workshops held in the U.S., Germany and Japan and is available at http://bit.ly/1w1svjo. The publication isn’t free, you’ll need to buy ($28) or rent ($4) it.

Development of 3D IC integration provides a potential solution to overcome the wiring limit imposing on interconnect density, performance and power consumption of integrated circuits. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-integrated circuits using through silicon vias (TSVs). The potential stress-related impact of the 3D integration process on product reliability must be understood and shared, and designers need a solution for managing stress.

The co-editors selected papers to focus on Design-for-Reliability (DFR) and together they describe a stress management simulation flow that would enable designers to model stress implications on their designs quantitatively. The papers also discuss multi-scale modelling and simulation, multi-scale materials parameters and multi-scale analysis.

This is the second work in a series on stress management. The first publication, called “Stress Management for 3D ICS Using Through Silicon Vias” is available at http://amzn.to/1o60QE4.

Posted on

Design Collaboration across Multiple Sites

Design Collaboration across Multiple Sites
by Pawan Fangaria on 09-02-2014 at 12:00 pm
Categories: Cliosoft, EDA

Any SoC or IC design project, whether implemented at the same design site or multiple sites requires some data management tools to manage things such as a central data repository, revision management of files, etc., for effective co-ordination of work among different team members. Given the challenge of meeting the shrinking time-to-market windows, semiconductor companies are creating design centers wherever it is economically viable to operate or where a substantial good talent pool is available. As a semiconductor professional myself, I have often wondered about the ramifications on design schedules and design efficiency when collaborating across globally-dispersed design centers.

I realized the impact when I met one of my old acquaintances during my regular morning walk last Sunday. On enquiring about his rather irregular morning walks, he explained that it was due to the very long hours he was compelled to work. He further elaborated that his design team was facing challenges in collaborating with different design team members in different parts of the world. Curious, I politely enquired whether it was due to communication issues. Based on my friends explanation, I understood that some groups within their company rely on an open source revision management system that uses mirrored sites, despite which file transfers into the repository as well as the ‘rsync’ between their mirrored sites was also taking a long time. Since it was open source software that they were using for data management, the support was very limited. Moreover, they had been using customized scripts to set triggers, which needed to be upgraded, and the person maintaining the scripts at his local office had left. Other groups were not using any data management systems and were using a name-based file versioning system.

Also Read: Webinar: Improving Collaboration Within Dispersed Design Teams

My poor friend was stuck with late night sync-up meetings accommodating common time for all sites twice a week and of course managing to understand accents and diffierent ways English was spoken in different regions. Even though they had local sync-ups for the analog, digital and firmware parts of an SoC, they still needed to regularly consolidate all the work together to verify that they were working with the latest versions, for example, with the latest behavioral models from analog designers. And as a result of the chaos, his tapeout schedule had slipped, something which his managers were not too happy about.

Given the disorganized nature with which data management was set up, and the constant meetings my friend needed to have to ensure everyone was in sync, it was no wonder that my friend was stressed out. I remembered my old library design days when I had experienced headaches in regular mirroring of hierarchies for proper regression runs and when we had to babysit transfer of hundreds of design files, data or executable files to/from customer sites in the USA.


Figure: Globally-dispersed design centers collaborating on a design

In my opinion, owing to the complex nature of the design flows and designs being created, having a robust data management tool is no longer a luxury but an absolute necessity, especially when multiple design centers are concerned. It helps keep the engines of the design project well oiled and allows the designers to be more productive. Most importantly, it helps reduce the un-necessary stress in designers’ lives.

So, what are the requisites a data management must have in order to enable a design team, dispersed globally across different sites, to be more productive? Should we look at using open source software for data management or should we rely on commercial software? Here are some of the considerations I would think through:

· While I am a believer in open source software, and some of them are extremely good, the support is rather limited. The last thing I would like in a high-pressure project is to be stuck with some issues and being forced to browse through online forums to find a solution. Commercial data management solutions such as ClioSoft’s SOS and Perforce score in this area in terms of the level of support being provided. Moreover, commercial data management vendors are more amenable to work with you to customize the software to meet the unique requirements of your company.

· Commercial data management solutions provide a better feature set and roadmap compared to open source software.

· Although networks have large bandwidth these days, designers still suffer latency while accessing files from their central repostiories. Having a cache management system at each of the design sites, with regular automatic sync-ups with the data in the central repository, would help eliminate the latency problem. The local cache system should be configurable to store the commonly used revisions of the data, specific to the local design site. An additional advantage of this approach is that in the event of network down time, designers could continue to work without stopping at the local design centers.

· Network disks from vendors such as Netapp are not cheap. Hence from a cost perspective, it may not be prudent for the designers to copy the entire design database into their work area as the disk space usage can very easily balloon up. Ideally, the designers should be able to check out only the files that they want to modify into their local work area, while referring to the local site cache for the rest of the files.

· For the semiconductor insustry, espcially for analog, mixed-signal and backend designers, does it make sense to use a hardware configuration system such as ClioSoft’s SOS, which is built for big data sizes and performance, or a software configuration system such as Perforce? The requirements of the semiconductor industry to some extent differ from that of the software industry.

· No matter how much preacution a design team manager takes, a common problem he continues to face at the time of a design tapeout is the number of changes which are made at the last minute. As a result there are problems such as the central repository not being up to date, or unsolicited fixes being done at the last minute, which tends to de-stabilize the release. This can be resolved by maintaining specific release tags and ensuring that all files have them before the release and after fixes of all open defects against them. One of the requirements therefore would be the ability to set as many tags and labels as one wants during a design project cycle. This helps considerably while coordinating with team members at multiple locations.

· In order to restrict further changes in the files with release tags, there should be strict access control mechanisms that set the files to read-only mode the moment they are promoted with a release tag. In fact, access control must be used to allow or restrict access to particular groups whenever required.

· Design managers should be able to leverage off existing reports or create their own reports to determine the audit trail or to determine whether the same version of the IP is being used by all the team members.

· There must be an integrated defect tracking system that can be reviewed for the required fixes so that one can ascertain that the required fixes from other parties are done.

· There should also be a mechanism to take snapshots of the design very easily. There should be an easy mechanism for maintenance of tags and labels for hand-off of specific modules. This is very useful for designers when they are running different experiments in different directories to meet the performance criteria. It is etremely easy to lose track of which directory has the correct results. Having a mechanism to tag the directories would be extremely useful.

Do you have any other insights into what a data management tool for a semiconductor company must have? Comments are welcome!

Also Read

Webinar: Collaboration Within Dispersed Design Teams

Leveraging Design Team Energy!

Webinar: Making Design Reuse Work

Posted on

MIPS 64 bit CPU Architecture

MIPS 64 bit CPU Architecture
by Eric Esteve on 09-02-2014 at 4:47 am
Categories: Imagination Technologies, IP

Imagination Technologies has just launched the 5[SUP]th[/SUP] generation of MIPS CPU core, the 64-bits Warrior, or I6400 family, offering a total compatibility with the 32-bit previous architecture. MIPS Warrior I-class processor cores offers 64-bit processing in applications including embedded, mobile, digital consumer, advanced communications, networking and storage. I6400 is designed to be an extremely flexible, low-power 64-bit processor architecture capable of scaling across a wide range of applications, from microcontrollers to 64-bit servers. This 64-bit architecture provides hardware virtualization in all cores, hardware multi-threading, multi-domain security and multicore/multi-cluster support.

If we take a look inside the I6400 family of cores, customers will benefit from:

  • Highly efficient, scalable 64-bit performance:The I6400 will enable customers to set new price/performance points across markets. The I6400 can be implemented across a very wide range of performance, power and area operating points allowing reaching high frequencies in aggressive implementations. Design architect may implement multi cores and multi clusters configurations, including a mix of heterogeneous multi cluster, highly appreciable in mobile systems.
  • Hardware multi-threading:The I6400 features hardware multi-threading technology that supports up to four hardware threads per core.

Hardware multi-threading leads to higher utilization and CPU efficiency. Moreover the simultaneous multi-threading (SMT) technology in the I6400 enables execution of multiple instructions from multiple threads every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% with less than a 10% cluster area increase.

  • Hardware virtualization:To provide increase security and reliability and enable a unified security and virtualization strategy throughout the system, the I6400 joins the entire range of MIPS Warrior cores in incorporating hardware virtualization technology (this includes support for up to 15 secure/non-secure guests).

  • Unified security strategy:The I6400 core is designed to address the privacy and security needs of evolving and emerging connected applications. The core is optimized to support multiple independent security contexts and multiple independent execution domains. The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
  • Advanced power management:PowerGearing™ offer the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
  • Efficient FPU: The proven hardware Floating Point Unit (FPU) in the I6400 supports both single and double precision capabilities relevant to general computing as well as improved control systems processing.
  • 128-bit SIMD:The I6400 features 128-bit SIMD support, delivering high performance and high throughput for a wide range of tasks that can exploit the efficiencies of SIMD execution in data-parallel applications. It is built on the MIPS SIMD architecture with instructions defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, or to leverage of existing code.

Nothing is better than a picture (see above) and some numbers to illustrate the I6400 Power/Performance/Area (PPA) optimization. Targeting TSMC 28 HPM technology, the base core configuration, including 32 KB Instruction, 32 KB Data for the level 1 cache, two threads/core, SIMD/FPU and H/W virtualization with 15 guests, occupy one mm2 and deliver 5.6 CoreMark/Mhz or 3.0 DMIPS/Mhz. This performance level assuming worst case conditions (Vnom -10% and SS corner Silicon), nevertheless, higher frequencies can be achievable with more aggressive implementation techniques. The cluster configuration in this example is a quad core with 128 virtualized global interrupts and 1 MB of level 2 cache, for an estimated area of 7 mm2.

The successful semiconductor device will have to exhibit low power consumption while offering high performance, not only for mobile application but also in enterprise or consumer systems. Power efficiency (or performance in DMIPS or CoreMark per Watt) is the keyword. Advanced power management, or PowerGearing for MIPS I6400, is based on the following techniques:

  • Fine grained, block level, and core level clock gating
  • For each core (in multi-core cluster):

    • Sleep mode
    • Dynamic Voltage and Frequency Scaling (DFVS)
    • Can be implemented at different performance/power optimization point
  • Directory-based coherency architecture optimized for low power

    • Sleeping cores only wake when needed for coherency

Imagination expects the industry to move for architecture neutrality, thus the CPU choice should be based on technical superiority. The I6400 features set addresses wide range of next generation applications, allowing customers to optimize their resource investment when targeting various applications.
Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014. Contact info@imgtec.com for more information.

From Eric Esteve from IPNEST

More Articles by Eric Esteve…..