SemiWiki – Page 793 – The Open Forum for Semiconductor Professionals

October 31, 2014June 14, 2019

Effective Bug Tracking with IP Sub-systems

Effective Bug Tracking with IP Sub-systems
by Daniel Payne on 10-31-2014 at 7:00 am
Categories: EDA, Perforce

Designing an SoC sounds way more exciting than bug tracking, but let’s face it – any bug has the potential to make your silicon fail, so we need to take a serious look at the approaches to bug tracking. When using an IP or an IP subsystem in a design, the SoC integrators require some critical knowledge about this IP. The actual design and test files are just one part of that information. It is also very useful to understand all of the outstanding bugs associated with this IP subsystem in real time so that the impact of using a specific version of the IP is clear.

Problems with traditional bug tools
The key problem with this is that most bug tools like Jiraor Bugzilla are project specific. Bugs discovered in IPs developed as part of a bigger system are associated with that system, rather than the IP itself. If that IP is now used elsewhere, there is usually no good way to track open bugs.

The other shortcoming of native bug tools is that bugs cannot be associated with multiple projects or systems. This way, even if the bugs related to an IP were carved out into a separate project, the original project would no longer have access to these bugs.

Many teams have tried to implement IP hierarchy, bug portability, etc. by using custom fields, complex logical associations and call-backs directly in the bug tools themselves. However, IP reuse and IP hierarchy is a dynamic, constantly evolving situation, which makes keeping bug hierarchy and IP reuse in-sync an almost impossibly complex task.

Connecting bugs to an IP management system
Methodics has an approach where the most scalable way to connect bugs to IP is by overlaying IP meta-data in the bug tracking system. Connecting bugs to IP means that the IP management platform itself will understand which bugs are associated with which IP by accessing this metadata. This allows multiple users to view IP bugs directly in their project hierarchy.

The actual project under which a bug is filed is no longer a limitation. Users can pick the project that they wish (the one they are currently working on) to file a bug. However, the tool allows users to also associate the bug with the IP itself. This allows the IP and IP subsystem hierarchy to be maintained separately in a scalable, fast database, removing the need for the bug tool to track the evolution of the project.

The other advantage of this method is that bugs are visible in the actual hierarchy of the project. For example, take a simple CPU project shown below. In this case, the CPU is made up of three subsystems, which also have additional IP of their own.

In order to make sense of all the bugs associated with each of these components, the user should be able to see the currently open bugs in a similar hierarchy – allowing the user to drill down into each level. A hierarchical bug display looks like:

Bug relationships – discovering predecessors and successors
As an IP develops, some bugs are fixed and others are discovered. Each released version of an IP has a set of outstanding bugs that are open against it.

Related – IP Management Update at DAC

It is quite useful to explore bugs in earlier and later releases of each IP so that the full context of the current IP’s bug profile is visible. This can be done by creating parent-child relationships between IP versions and branches, and having an easy discovery process for these bugs. A snapshot of how this is done is shown below:

Another way these parent/child relationships can be leveraged is between branches of an IP. Bugs found in child branches (variants) can be reflected upstream back to the parent branch (trunk) context and merged into the effective bug list. The same applies for bugs found in the original parent branch, new problems should be communicated to downstream child branches for analysis. Of course, not all of these upstream/downstream bugs are relevant in every context, so the ability to include or dismiss issues is important.

Identifying the context
Another problem with managing bugs in an IP context is understanding at what level to apply the bug. Often the engineer that finds the problem doesn’t have the full context of the hierarchical IP where the problem was found, and the best they can do is to file the issue at the IP hierarchy they have visibility. This leaves the subsystem owner to refile the bug at the appropriate IP further down the hierarchy and a process for managing those changes that communicates with the relevant stakeholders.

Summary
We’ve seen how important it is for bugs to be managed in an IP-centric fashion with modern SoC designs. With IP reuse the norm, bugs must be managed at the resource level rather than the project level and parent child relationships must be tracked to notify downstream/upstream stakeholders when problems occur. Integration people must also have the ability to create placeholder issues at the subsystem they have visibility to and a mechanism for moving those to the appropriate lower level IP when the issue has been properly analyzed.

With these new tools a true IP centric design methodology can be embraced by our SoC design community.

October 31, 2014April 10, 2025

Silvaco at the TSMC 2014 Open Innovation Platform

Silvaco at the TSMC 2014 Open Innovation Platform
by Daniel Payne on 10-31-2014 at 7:00 am
Categories: EDA, TSMC

The success of our semiconductor eco-system depends on collaboration, so the annual TSMC OIP Event just held on September 30 at the San Jose Convention Center was a prime example of that. I didn’t attend this year, but I did follow up with Amit Nandaof Silvaco this week to hear about what they presented. As a consultant I’ve worked with Amit before when he was at Barcelona Design Inc., an interesting analog-compiler company, now part of Synopsys.

Many engineers think of Silvaco as suppling only TCAD tools, however that’s not really true because they’ve assembled a custom IC design flow of tools that support many PDKs at TSMC:

EDA Tools for Custom IC Design

AMS designers can build their next IoT products using schematic capture, SPICE circuit simulation, waveform viewing, layout editor, DRC, LVS and parasitic extraction tools. Silvaco’s SPICE circuit simulator is called SmartSpice and it has been upgraded to:

Simulate faster by using a new parallel algorithm
Model certified at 16 nm
ETMI reliability supported
Soft Error Reliability

Improved capacity and performance

Related: Modeling and Analysis of Single Event Effects (SEE)

SmartSpice is used by circuit designers for library, memory and critical path characterization and it also has built-in optimizers.

In SPICE circuit simulation you need to have netlists with extracted parasitics to get the most accurate results, and the 3D RC extractor from Silvaco is called Clever. Memory cell design require accurate parasitics in order to tune RAM performance goals and catch all of the capacitive coupling effects caused by 3D layout structures like FinFETs.

3D structure of an SRAM cell

SPICE models are created by the Utmost IV tool, and many different device types are supported: TFT, UOTFT, BSIM-CMG for FinFETs, HSIM-HV2 for high voltage devices, BJT, SOI, JFET, Diode, FRAM.

TFT example fit plot using the RPI a-Si TFT model

Related: SiC and Si Power Devices

On the TCAD side engineers can virtually model diverse semiconductor technologies for: Displays, Power devices, Optical, FinFET, FD-SOI and even soft error reliability. Victory is the product name for this TCAD modeling and it supports 1D, 2D and 3D.

Related – TCAD to SPICE

I think that you’ll agree that Silvaco has a lot more than just TCAD tools to offer semiconductor engineers today, because circuit simulation and IC CAD tools are also included in their tool flow. Another factor that you need to know about Silvaco is that their tools are affordable compared to the big three in EDA. 2014 marks the 30th year in business for Silvaco, which is quite an accomplishment in this competitive industry.

October 30, 2014June 14, 2019

Improving Verification by Combining Emulation with ABV

Improving Verification by Combining Emulation with ABV
by Tom Simon on 10-30-2014 at 4:00 pm
Categories: EDA, Siemens EDA

Chip deadlines and the time to achieve sufficient verification coverage run continuously in a tight loop like a dog chasing its tail. Naturally it is exciting when innovative technologies can be combined so that verification can gain an advantage. Software based design simulators have been the mainstay of verification methodologies. Test benches are as old as the earliest designs. The advent of language based design created an opportunity to insert code for functional checks right into the designs themselves. But this activity was initially an informal and inconsistent practice.

In the last decade the formalization and standardization of these assertion based checks has made them easier to implement and more effective as debugging and verification tools. Accellerahas developed the Property Specification Language (PSL) for specifying assertions for a variety of HDL’s. Also, there is System Verilog Assertion (SVA) which is part of System Verilog. Both are IEEE standards.

Assertion based verification (ABV) brings with it many benefits. For one, as developers write HDL code they can add assertion checks in situ. The assertion checks added at this point can also help serve as documentation, and they will be more efficient and potentially more complete than directed and constrained random verification. Of course ABV code can be added externally as well by using the “bind” feature. In some cases that is preferable because it makes the verification code reusable, and the verification team can easily work in parallel with designers during development.

At higher levels of design abstraction ABV suites facilitate reuse. Having a set of assertion based checks for SOC building blocks makes it easier to confidently reuse blocks from internal or external sources. And this goes with knowledge that the blocks will more easily meet verification requirements. It turns out that there is now a niche market that provides Verification IP (VIP) for this very purpose. For example companies such as Mentor have large libraries of VIP for many different standard design elements. Because of their large user base and productized development, commercially available VIP can be better tested and documented than in-house developed VIP.

Performing assertion based checks with a software based simulator affords complete visibility, which is invaluable for debugging. Also it is easy to toggle on or off each level of checks: internal, block, signal, protocol, or chip level. Lastly error reporting is of a very high quality – including coverage information and data useful for debugging. Naturally this is a fully developed approach. Its main drawback is that as the verification problem moves up the hierarchy the simulation data set grows rapidly, so performance and throughput become limiting factors. Compromises on the number of clock cycles that can be run or the amount of test case data processed are necessary. Given that the verification team is always in a race with time, software based approaches alone may not suffice.

In the worst case scenario a test chip might come back with an issue that only shows up after many clock cycles or that is very data dependent. Despite high clocks rates, debugging in silicon is hindered by lack of observability. Unless critical signals or registers can be probed, tracking down problems can become an open ended task.

What if there was a solution that supports large design size, fast execution, high design visibility and full support for the assertion based verification standards? Mentorrecently put out a white paper that talks about using their Veloce emulators as the vehicle for performing ABV. Using an emulator can provide a huge speed advantage. Tests can be run on more cases over more clock cycles. By fully supporting the assertion based verification standards in the Veloce compilers, Mentor is making it easy to bring assertion checking to emulator users. Another big advantage of this approach is that visibility into the design is maintained so coverage data and debugging information is readily available.

Mentor also reports that they are offering tight integration in the Veloce GUI for reporting and controlling what assertions are exercised. This allows for focused verification as the design moves from block to system level.

It is clear that combining the acceleration and flexibility of emulation with the power of assertion based verification creates synergistic effect that can boost design debug and product verification.

October 30, 2014

Microprocessors: Will ARM Rule the World?

Microprocessors: Will ARM Rule the World?
by Paul McLellan on 10-30-2014 at 12:00 pm
Categories: Arm, Events, IP

Last week was the Linley Microprocessor Conference. Not the mobile one, which I find the most interesting since smartphones are such a bit part of what drives process technology these days, this is the one focused on networking and servers. But increasingly both markets are being driven by the same thing, namely mobile data. In fact smartphones are growing so fast that they are already the primary way that the internet is accessed and that trend is only going to accelerate. Desktop and notebook computers are a comparative niche. Jag Bolaria (of Linley) gave the opening keynote giving an overview of this part of the industry. Reading their data is a little difficult since they have a, to me, slightly weird definition of embedded, namely processors that last for a long time. I think they really mean anything other than a standard PC, which also has the slightly weird effect of showing Intel losing market share since the more that is done with standard server chips then the more it doesn’t count in the embedded market, as opposed to selling chips that go into routers, for example. Another complication is that Avago purchase LSI and then sold the Axxia part of that business to Intel. For this year, Linley continued to track LSI as a separate company.

Overall market share is lead by Intel followed by Freescale. To my surprise, AMD increased market share against Intel in this market since suppliers are looking for lower costs and an alternative to Intel. Cavium are also doing well selling their Octeon SoCs into many segments. Of course ARM don’t appear on this list since they don’t sell processors. However, when we look at share by instruction-set-architecture (ISA) they show up, but with a suprisingly low share. x86 slightly trails the Power architecture (Freescale, Applied Micro, Axxia for now, all use this).

ARM has a tiny share. But as I reported last year, that is all set to change. The 64-bit ARM v8 instruction set has opened up new markets and almost all embedded vendors are moving their future investment to ARM. However, the time to design-in, ship and ramp equipment in a conservative market means that the crossover will take 5-10 years, but:

AppliedMicro shipping X-Gene and sampling X-Gene2
Cavium plans to sample Thunder in Q4 (their current products are MIPS based)
Feescale sampling LS1 and plans to sample LS2 this quarter
LSI/Avago/Intel shipping ARM version of Axxia (although presumably this will be short lived now Intel owns that business)
AMD sampling Hierofalcon for embedded market
Broadcom shippping StrataGX and developing Vulcan CPU

Linley believes that a dual architecture strategy (such as MIPS and ARM) will not endure since qualifying two architectures is too expensive. So, provided the ARM parts are not rejected by the market, then MIPS and Power will lose market share.

As I said above, the market is driven by cellular data. Next year there will be 2 billion connected devices shipped, around half of which will use high data rate LTE (a big part driven by Chinese deployment although based on Xilinx conference calls and other information this is somewhat pushed out). A new technology like LTE forces the operators to focus on coverage (so then they can sell handsets) and then on capacity expansion as the transition happens and more handsets use more and more data. Capacity expansion means small cells which is a big growth opportunity.

In the server market, no surprises, Intel has 96% market share. Their strategy is to leave no holes. No matter which price/performance point you are interested in, Intel has a processor for you: Xeon E7, E5, E3, Atom and even customized processors. But ARM has this market in their sights along with their partners. As I said above, AppliedMicro are in production, AMD, Cavium, Broadcom and more. Calxeda were a casualty, only having 32 bit ARMv7 and not enough money to do 64-bit. Jag also said “expect more entrants” which I suspect he knows some non-public stuff that I don’t.

But there are challenges for ARM in servers. Unlike with Intel there is no common platform and each vendor has its own uniqueness. OS vendors are sitting on their hands waiting for volume before they invest. Of course they are attacking a walled-city but Intel has very high pricing (good for them) which creates market opportunity. But it is hard for ARM processors to match Xeon E5/7 performance, which matters for some markets (where single thread performance matters) but not others (where cost, power, physical size and general TCO is important, such as, say, Facebook data centers).

Linley himself talked about the Internet of Things (IoT). Industrial applications are already broadly deployed with, for example, 300M smart meters installed. For that market a discrete solution that costs $20 is OK. Large consumer goods are next with an SoC desired with a cost under $10. But the really big market is small things with an SoC at under $3. I’m personally not convinced since the market is so fragmented. Also, I’m not convinced that IoT devices have minimal compute needs since they also have very low power needs which means thay cannot be uploading huge amounts of data to the cloud continuously for processing. But it seems some vendors are developing IoT ASSPs integrating CPU, memory, analog and wireless to drive the cost down.

Finally, a little bit of process roadmap. But one message is that cost-focused processors will stay on 28nm LP indefinitely. Jag pointed out that 16nm reduces power but increases cost and the density is the same as 20nm (it has the same metal fabric). For high end servers that is an acceptable combination but for IoT and other lower end applications, 28nm will be around for a long time.

Adding a Digital Block to an Analog Design

Adding a Digital Block to an Analog Design
by Daniel Payne on 10-30-2014 at 7:00 am
Categories: EDA, Tanner EDA

My engineering background includes designing at the transistor-level, so I was drawn to attend a webinar today presented by Tanner EDAand Incentia about Adding a Digital Block to an Analog Design. Many of the 30,000 users of Tanner tools have been doing AMS designs, so adding logic synthesis and static timing analysis from Incentia makes sense to fill out the design flow.

Jeff Miller from Tanner EDA presented the overall AMS tool flow, including Incentia tools for big A, little D designs:

Steve Lin from Incentia talked about their digital design flow from RTL to gates with timing and power closure:

Logic synthesis is provided by the Incentia tool called DesignCraft, and it uses industry standard file formats like:

Verilog, VHDL
Synopsys .LIB, CCS Library
SDC for timing constraints
VCD, SAIF and FSDB files for switching activity
SDF – standard delay format
Tcl scripting

Incentia also supports a DFT methodology with their TestCraftDFT tool, then interface to ATPG tools from multiple vendors: Mentor, Synopsys and SynTest.

Following logic synthesis the next step is Place and Route using the HiPer Place and Route tool from Tanner, typically handling designs up to 50K gates. Standard file formats are supported, like:

LEF, DEF
GDS
Liberty for cell timing
Verilog gate-level netlist

Placement, clock routing, and n-layer auto routing steps were reviewed, and the finished layout has SDF for use in timing analysis.

For static timing analysis the tool from Incentia is called TimeCraft which accepts the SDF file from P&R. Signal Integrity (SI) issues are accounted for, along with IR drop. Multi mode, multi corner (MMMC) analysis is supported, allowing you to do timing analysis across a grid or LSF to reduce run times. The largest design run through TimeCraft has been a 100M instance tape-out.

At 65 nm and smaller geometries the on-chip variation (OCV) can start to produce overly-pessimistic timing analysis results. Location-based OCV (LOCV) can also be taken into account with the TimeCraft tool. With the LOCV approach you will have fewer timing violations, plus smaller worst-case negative slack, making timing closure happen quicker.

The Incentia tool called ECOCraft supports Engineering Change Orders (ECO) to fix setup or hold time violations after P&R. Leakage power values can be reduced by running the ECOCraft Power tool by optimizing the use of multi-Vt cells and cell-sizing.

A live demo was performed on a small block with an 8 bit ADC circuit including a Finite State Machine, written in Verilog. After logic synthesis was run using a script, then the layout editor was invoked and P&R setup and run (cell placement, clock buffer placement, de-coupling capacitors, filler cells, clock routing, signal routing, power routing).

An SDF file was created, then used in Static Timing Analysis (STA) with TimeCraft using another script. The results of STA look like:

Summary
I cannot remember the last time that an EDA vendor actually ran their tools live during a webinar, so kudos to Jeff at Tanner EDA for doing this today as proof of how fast this tool flow actually is. Tanner users will be pleased that they can complete their big A, little D designs using this AMS implementation flow with Incentia tools. The GUI and scripts looked easy to run and learn, so expect a quick ramp-up time.

The full 60 minute, archived webinar is available online after a short registration process.

October 29, 2014

Viva the New Industrial Revolution! What Etsy, 3D Printing, and Kickstarter Means to Semiconductor Companies?

Viva the New Industrial Revolution! What Etsy, 3D Printing, and Kickstarter Means to Semiconductor Companies?
by Charles DiLisio on 10-29-2014 at 4:00 pm
Categories: Foundries

The world is changing and IC companies need to adapt to this to stay competitive — moving to systems (hardware and software) vs. just product (hardware). Three key trends that are underway that change the way IC vendors need to think about their customer and the customer’s customer:

Markets are Fragmenting: We are moving away from the homogenous baby boomer generation to a heterogeneous world of multiple generational, multicultural wants and needs. These new consumer’s are seeking products that are uniquely crafted and of high quality — think Etsy. Design becomes as important as functionality. Young consumers want something that is unique to their interests — not volume, but high value.

Means and Barriers to Manufacturing are Declining:3D printing and cloud fabs or prototype manufacturing are changing the way things are made. Design software like Autodesk 360 is becoming virtually free. In the near future, you will be able to make parts or who products right at your home. Mass Customization will be the rule not the exception. Even electronic circuits are readily modularized for makers in things like LittleBits or Tiny Circuits.

Crowd-funding for New Products:Kickstarter and other sites provide early funding to new products of all types. Even venture capital firms are asking start-ups to first seek crowd-funding and if the product gets funding then they look to follow-on investments.

The Da Vinci 3D All-In-One Scanner/Printer

The above trends will cause IC companies to act faster with respect to IC design and manufacturing. Also, the idea behind Moore’s Law — the learning curve and reducing costs in conjunction with greater volumes doesn’t work in a world of Mass Customization and 3D Printing. Which brings me to this observation — 3D printing is changing the way we look at product development. Now the newDa Vinci All-In-One 3D Scanner/Printeris on the scene at a price point of $799 a significant price below the Stratasys Makerbot Replicator 3D printer. Now makers/designers have the capability to scan (copy) objects and then print them in one machine. This further reduces the barriers to manufacturing in a very important way.

Why Etsy, 3D Printing and Kickstarter are Important to IC Vendors?

IC vendors — don’t think volume, think systems. More integration requested by the customer seems logical, but can you get paid for it and how long will it take to develop the IC? Think programmability like microcontrollers like Arduino (Atmel) mbed (ARM), or PIC (Microchip). Programmability gives you the IC vendor ability to modify IC functionality using software and increase time to market and not be dependent solely on volume.

Second, how can you improve or enhance your offering using software? Can you make your IC offering more flexible, responsive and easy to use with software? Think of National Semiconductor’s Simple Switcher that allowed the engineer to develop a power management solution with simple inputs, but at a much, higher level. See the links to Littlebits or TinyCircuits above.

Third, IC vendors need to think look to new markets and don’t depend solely on existing markets. Leaders in one platform say PC’s (Intel/Microsoft) don’t necessarily lead in the new platform Smartphones (Qualcomm, Apple, Android). If Mass Customization though the Internet of Things (IoT) becomes a new platform, new leaders will likely emerge. Will or can you become a leader?

Therefore, IC vendors need to seek new potential product areas — I suggest that you attend some IoT Meet-up groups like PnP Thursdays or IoT Business Meetup SV. If you don’t know what a Meet-up group is you are already behind. Get Peter Thiel’s book “Zero to One”. One of Peter’s thoughts: “Figure out something that nobody else is doing and look to create a monopoly in some area that’s been underdeveloped.”

October 29, 2014June 14, 2019

Cadence Mixed Signal Technology Forum

Cadence Mixed Signal Technology Forum
by Paul McLellan on 10-29-2014 at 7:00 am
Categories: Cadence, EDA, Events

Yesterday was Cadence’s annual mixed-signal technology forum. I think that there was a definite theme running through many of the presentations, namely that wireless communication of one kind or another is on a sharp rise with more and more devices needing to connect to WiFi, Bluetooth and so on. This was most obvious during the panel session after lunch which was on the ecosystem needed for the internet of things. However, the way to design radios (and analog interfaces in general) is increasingly to design the smallest possible analog blocks and then use digital, even quite complex digital, to calibrate the analog.David Su of Qualcomm gave the opening keynote on Designing WLAN SoCs. He started with a history of wireless LANs, pointing out the huge increase of 3 orders of magnitude increase in data rates. The effect of this has been that data cost has been declining about 2X per year even though the cost of a wireless router has been roughly static. We went from 1MHz to 160MHz channels and now with future standards allowing 4 or 8 channels to be used.He is a big fan of minimizing the analog and using digital to calibrate, what he (and Cadence) calls digital assisted analog design. Of course there are still big challenges. The biggest problem, beyond simply power, is digital interference with the analog on the SoC. There are various strategies for coping with this, minimizing the aggressor (the digital logic) by techniques like clock gating and minimizing switching large registers on one clock cycle. Next, strengthen the victim (analog) by wells and robust analog design. And then try and minimize the coupling by spacing the blocks apart and even potentially some process tricks such as deep wells.Ken Kundert (who used to work at Cadence and was the principal author of Spectre) made a plea that the way that analog engineers designed needed to modernize or designing these kind of digitally trimmed analog is almost impossible. If designs are to be done in a reasonable time then the digital and analog need to be designed in parallel and the most promising way to do that is to start from a spec of the analog block and use that to produce a model and a self-checking testbench. This isn’t as hard as it seems. Digital design has huge state so verification is hard, but synthesis, place & route makes implementation fairly straighforward. Analog is the other way around, specifications are simple, there is little state, but implementation is hard. Hence the need to use models since the schematic comes too late and simulates too slowly for the digital design team.Wilbur Luo of Cadence gave an overview of the mixed signal offering. Increasingly the methodology revolves around having Virtuoso and Encounter Digital Implementation (EDI) running on a common open access database able to share the same semantics without losing things like constraints in implementation. There are even lower capacity versions of Encounter, Tempus, Voltus etc which run inside Virtuoso to enable digital design.After lunch there was a panel with Rob Consaro of Freeescale, Ron Moore of ARM, Ian Dennison from Cadence Scotland and Doug Patulio from TSMC. Rob related a tale of how the tools and methodologies now mean that power methodology is now a solved problem compared to a few years ago when he tried and failed to design a chip with lots of power domains in the days before CPF/UPF. But noise is the big challenge going forward. Ron said in some cases ARM is going back to a single power domain to keep the area down which makes it a challenge to handle leakage.Doug pointed out that TSMC has always been in the business of helping customers get to the next node. But he feels that 28nm is the last time that will happen. Some people will move to 16FF+ of course. But TSMC is putting a lot of effort into re-engineering older processes using what they have learned from the advanced processes, especially for ultra-low power aimed specifically at IoT. Ian talked about putting sensors and analog and digital all on the same die, perhaps using TSVs or other 3D technologies. There is a mismatch at present as to which process sensors and other MEMS devices need for fabrication, with which digital technologies make most sense. One question from the audience asked about software: how do we get analog models running on emulators so that we can use virtual platform technology to do early software development? There is some possibility that using real-number models will help but there was no clear answer.Oh, and I won a copy of the Mixed-signal Methodology Guide.
More articles by Paul McLellan…

October 29, 2014July 18, 2025

Who Really Needs USB 3.1?

Who Really Needs USB 3.1?
by Eric Esteve on 10-29-2014 at 4:58 am
Categories: IP, Synopsys

USB is certainly the most ubiquitous of the Interface protocols. I would bet that everybody is using USB everyday (I mean activate a USB connection, as we also use PCIe or SATA even if we don’t realize that we do it), but which application will get benefit of the 10 Gbps delivered by USB 3.1? Before precisely answering the question, let’s review some facts:

More video/images are created as video standard is moving from 4K to 8K
End user consumption per day (Video, audio, social media) is growing, estimated at 63 Gigabytes per day per person
The storage devices prices are dropping, this is true for both HDD and SSD, leading to use larger devices (for the same price).

These facts allow understanding where USB 3.1 adoption will come first, in storage and digital office segments, to support applications like Hubs, Docking stations, Host add-in cards or SSD.

As an analyst, I have tried to model SuperSpeed USB adoption, back in 2009. There is a consensus about the adoption behavior, coming from the “Innovation Theory”: it looks like a Gaussian curve (with Innovator, Early Adopter, Early Majority, Late Majority and Laggard categories). By the way, this Gaussian curve and the related categories are exactly the same than for an epidemic, Ebola or the flu virus! Let’s come back to electronic. This theory tells us that the adoption rate is low at the beginning (Innovator and early adopters), then reach the mainstream (early majority and late majority) and finally the laggards.

For an IP vendor, the $1 million question is to know about the market dynamic, how long it will take for USB 3.1 to reach the mainstream for each specific market segment. Synopsys has built the above picture, which is the addition of five Gaussian curves: Storage, Digital Office, Cloud, Mobile and Digital Home. According with John Koeter, vice president of marketing for IP and prototyping at Synopsys, the company has an “extensive knowledge in developing USB IP, more than 3,000 USB design wins”. Thus, Synopsys knows the key factor, by experience about selling USB 3.0 IP, which is the adoption rate.

USB 3.0 specification has been released at the end of 2008, starting to sale in 2009, and it took 5 years for the new standard to reach all the potential applications. If you take a look at the above picture, Synopsys has built it by duplicating for USB 3.1 what has happened with USB 3.0, and I fully agree with this approach. We can consider that the early adopters for USB 3.0 will be the early adopters for USB 3.1 (and so on for the other categories). In other words, the application currently integrating USB 3.0 will certainly move to USB 3.1. This is a “semi-empirical theory”, based on past behavior, but with only one unknown: USB 3.1 adoption rate in Intel PC chipset. If this adoption comes faster than for USB 3.0 (which was too long, by the way), we may even see quicker sales of USB 3.1 than USB 3.0 IP.

Synopsys is claiming offering the most comprehensive USB 3.1 solution, and there is no doubt about this assertion! IPnest has made the IP vendor ranking for USB 3.0 IP in 2013, and Synopsys enjoys 75% market share. In fact, USB 3.1 is just an enhancement of USB 3.0, running at twice the data rate (10 Gbps instead of 5 Gbps), and we can see that most of the architecture can be reused.

Synopsys Controller IP operates at USB 3.1/3.0/2.0 speeds

Interoperates with all USB generations
Synopsys customers can use their existing USB 3.0 drivers
Configurable by user
- Address all markets – storage to mobile phones
- AXI speeds and bus width
- More memory for higher performance or less area for cost savings

Synopsys also offers VIP:

Virtual model of DesignWare® USB 3.1 IP
Develop SW up to 9 months ahead of HW availability
USB 3.1 IP VDK configured to behave identically to real RTL for accurate driver development
Includes model of multi-core ARM® Cortex®-A57 Versatile Express board

It will be quite a challenge for Synopsys competitor to win market share on USB 3.1 IP market, as the company has enjoyed so far about 160-180 USB 3.0 design win, for a total (including the internally designed IP) of 300 to 350 design starts, since the release of the standard.

Also Read: USB 3.1: Physical, Link, and Protocol Layer Changes

From Eric Esteve from IPNEST

October 29, 2014August 22, 2024

IBM leaves semiconductors – end of an era

IBM leaves semiconductors – end of an era
by Bill Jewell on 10-29-2014 at 2:00 am
Categories: Foundries, GlobalFoundries

IBM last week agreed to transfer its semiconductor business to GlobalFoundries. GlobalFoundries will acquire wafer fabs in East Fishkill, New York and Essex Junction, Vermont; IBM’s commercial microelectronics business, which includes ASIC and foundry; over 10,000 IBM patents related to semiconductor manufacturing; and over 5000 fab and ASIC employees. GlobalFoundries will supply all IBM’s 22nm, 14nm and 10nm ICs for the next 10 years. IBM will take a $4.7 billion pre-tax charge to write down the assets of the semiconductor business and to cover paying GlobalFoundries $1.5 billion over the next three years. IBM will focus on fundamental semiconductor research for next generation computing.

IBM began semiconductor manufacturing for internal demand, which was huge when IBM was the world’s dominant computer company. Although exact numbers are not available, IBM was almost certainly the world’s largest semiconductor manufacturer for many years. As IBM became less dominant in computers, its semiconductor division had extra capacity. In 1993 IBM entered the merchant semiconductor market as a top 10 company with $2.5 billion in sales. IBM sold DRAMs (which were invented at IBM), ASICs and microprocessors. IBM withdrew from the DRAM business in 1999 but continued to sell ASICs and foundry services.

IBM leaving the semiconductor business is the end of an era. IBM was one of 34 original licensees of AT&T’s transistor patent in 1952, according to Bo Jojek in History of Semiconductor Engineering. We at Semiconductor Intelligence examined the original 34 licensees to see what became of them. The original 34 companies were from the U.S., U.K., West Germany and the Netherlands. Sony was the first Japanese company to license the AT&T patent, but was not one of the original 34.

It appears only 22 of the 34 companies developed and marketed transistor products. Of the 22 companies, most of them either went out of business or were absorbed by other companies in the 1950s and 1960s. 12 companies became meaningful suppliers in the semiconductor business. What happened to those 12 companies and to transistor inventor AT&T?

AT&T –semiconductor business was part of Lucent Technologies spinoff in 1996. Lucent spun off semiconductor businesss as Agere Systems in 2002. Agere merged with LSI Corp. in 2007. LSI was bought by Avago Technologies in 2014.
General Electric– sold its semiconductor business to Harris in 1988. Harris Semiconductor was spun off as Intersil in 1999.
IBM – divesting its semiconductor business to GlobalFoundries.
IT&T Corp. – divested semiconductor business over the years. Most of the remains of IT&T Semiconductor are now part of Vishay and Micronas.
L.M. Ericsson – sold most of its semiconductor business to Infineon in 2002. Ericsson exited the modem IC business in September 2014 (previously part of joint venture with STMicroelectronics).
Microwaves Associates –now M/A-Com, still makes microwave semiconductor devices.
Minneapolis Honeywell –now Honeywell, still makes semiconductor sensors.
N.V. Philips –spun off semiconductor business as NXP Semiconductors in 2006. NXP is still a top 20 semiconductor company.
National Cash Register Company –now NCR. Remains of semiconductor business now part of NetApp.
Raytheon Manufacturing –sold semiconductor business to Fairchild Semiconductor in 1997.
Siemens and Halske –now Siemens. Spun off its semiconductor business as Infineon Technologies in 1999. Infineon spun off its memory business in 2006 as Qimonda (now out of business).Infineon remains a top 20 semiconductor company.
Sprague Electric Company –sold semiconductor business to Sanken Electric in 1990.
Texas Instruments –divested most non-semiconductor businesses in the 1990s. Remains a top 10 semiconductor company.

Of AT&T and the original 34 patent licensees, only Texas Instruments remains as the same company and a significant player. If Siemens’s Infineon spinoff and Philips’ NXP spinoff are included, three of the original 34 licensees are still major semiconductor suppliers today. However compared to the changes in the semiconductor industry over the last 60 years, the changes in suppliers is not surprising. The semiconductor market first exceeded $1 billion in the mid-1960s and the major customers were mainframe computers makers (IBM), the U.S. military and the U.S. space program. Today the market is over $300 billion and the major applications include smartphones and tablet computers – unknown devices until about 20 years ago. The market has gone from single transistor devices in the 1950s to billions of transistors on an IC today.

October 28, 2014August 22, 2024

The GF IBM Deal Explained!

The GF IBM Deal Explained!
by Daniel Nenni on 10-28-2014 at 10:00 pm
Categories: Foundries, GlobalFoundries

I have it on pretty good authority that IBM has in fact come to terms with GlobalFoundries on the sale of their semiconductor business, or so I blogged last month. Did I mention that my grandparents and their many siblings settled in Upstate NY in the early 1900s from Italy via Ellis Island? So yes, I do qualify as an insider:

Insider says IBM and GlobalFoundries reach deal
Posted on September 17, 2014 | By Larry Rulison
A post to SemiWiki.com by industry author and blogger Dan Nenni says that IBM and GlobalFoundries have a “handshake deal” in place to take over IBM’s chip manufacturing.

The official announcement was last week and the slide deck is HERE in case you are interested. Since I was in Taiwan at the time and missed the official briefing I was afforded a quick one-on-one with Sr VP Gregg Bartlett at the beautiful new GF HQ. Rather than regurgitate what everyone else has been feeding you I will try and offer an insider’s view:

The IBM ASIC business is exactly what GF needed to get into the system houses
The IBM IP portfolio is exactly what GF needed to differentiate in the fabless semiconductor ecosystem
The IBM talent (5,000+ employees) is exactly what GF needed to create an East Coast semiconductor dynasty
The IBM patents (10,000+) is exactly what GF needed to secure their semiconductor legacy
The IBM acquisition is exactly what GF needed to secure a nice investor exit (IPO)

Growing up in Silicon Valley I have always viewed IBM as third world company. It was not just an East Coast versus West Coast thing, IBM was the status quo versus the entrepreneurs of Silicon Valley. Clearly Silicon Valley won but now IBM Semiconductor is in the hands of some very capable entrepreneurs which should turn out to be a very powerful combination.

Also Read:GlobalFoundries and IBM

Final approval on this will probably take the better part of a year but let’s talk about that for a minute. GF will be making a filing with the Committee on Foreign Investment in the United States (CFIUS) which consists of 16 departments and agencies including Homeland Security. The majority of the cases submitted proceed without investigation which is what I believe will happen here. Remember, IBM sold their PC business to Lenovo and GF bought AMD’s manufacturing business so this is not their first CFIUS rodeo. In the meantime the integration plans have already begun which will be like integrating peas and carrots at a family dinner.

The final and probably most important point is that GF will now own the IBM semiconductor process recipes moving forward. In the past, the process architecture was done in Albany and the implementation in Fishkill. At 28nm it was a “copy exact” type of deal out of Fishkill. At 14nm it is an architectural licensing deal out of Albany which is why Samsung has a different 14nm implementation than the other ex-Common Platform members. Moving forward 10nm will also be an architectural licensing arrangement. 7nm is unknown at this time.

Bottom line: This is an accretive deal for GF and puts them into the same league as Intel and TSMC, absolutely!