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Semiconductor Expert Forum

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GLOBALFOUNDRIES Acquires IBM Semiconductor Unit!

GLOBALFOUNDRIES Acquires IBM Semiconductor Unit!
by Daniel Nenni on 09-17-2014 at 9:01 am
Categories: Foundries, GlobalFoundries

I have it on pretty good authority that IBM has in fact come to terms with GLOBALFOUNDRIES on the sale of their semiconductor business. For those of you who have been following the story, especially the IBM semiconductor people, it has been a real roller coaster ride. If in fact this handshake deal goes through (expect a public announcement early October) it will be a very happy ending, absolutely. It will also be a game changer for the fabless semiconductor ecosystem and let me tell you why.


While researching the book “Fabless: The Transformation of the Semiconductor Industry” the importance of the pure-play foundry business model became crystal clear. Traditional semiconductor companies (IDMs) had become monopolistic and laxidasical. Pure-play foundries and the fabless semiconductor revolution, which started with IDM foundries, changed all that of course and through increased competition innovation came roaring back to our industry.

Unfortunately, competition in the pure-play foundry business has been mostly based on price. Having multiple manufacturing sources is critical to the fabless semiconductor ecosystem but it also puts the emphasis on cost. TSMC would innovate and UMC, Chartered, and SMIC would simply copy and do it for less margins. When AMD shed its manufacturing unit and GLOBALFOUNDRIES was formed I saw this as an opportunity to raise the innovation bar for the pure-play foundry business.

Also read: A Brief History of GLOBALFOUNDRIES

Of course it has not worked out that way thus far. GLOBALFOUNDRIES did not really raise the innovation bar and the Common Platform foundry initiative that came with it failed miserably. Combining the technical expertise of IBM with the marketing prowess of GLOBALFOUNDRIES however will bring ( I hope and pray) a second leading edge pure-play foundry to the fabless semiconductor ecosystem eliminating the need for IDM Foundries (Intel and Samsung).

Also read: IBM and GLOBALFOUNDRIES Deal!

From what I was told the negotiations initially broke off because of the price tag. IBM wanted to PAY GLOBALFOUNDRIES $1B to take the semiconductor unit and GF wanted $2B. Last year IBM’s semiconductor business shrank to less than $2B and is expected to shrink again this year to less than $1.5B so time was on GLOBALFOUNDRIES’ side. In most negotiations there is a point where you just stare at each other and the first one to blink loses. IBM definitely blinked because the final number that was mentioned to me is in excess of $2B.

My message to fabless semiconductor companies around the world is to aggressively support GLOBALFOUNDRIES in this acquisition. The same goes for the fabless semiconductor ecosystem. We desperately need two leading edge pure-play foundries to keep our industry growing. The IDM foundries do not have our collective best interests at heart, believe me. I have always been told by the top fabless semiconductor companies that if they had a choice they would chose pure-play over IDM foundries. Well, with this acquisition you will have a choice so it is time to put your wafer money where your mouth is!

Also Read: Intel says fabless model collapsing… really?

Also, when you show the IDM foundries to the door please thank them for their time and CAPEX. Both Intel and Samsung raised the innovation bar and pushed TSMC and the entire fabless semiconductor ecosystem to innovate at a much faster pace and for that we should be forever grateful.

More Articles by Daniel Nenni…..

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Optimize Your Interconnect & Design at System Level for Best Results

Optimize Your Interconnect & Design at System Level for Best Results
by Pawan Fangaria on 09-16-2014 at 7:00 am
Categories: Arm, EDA, IP

As the SoC design size, complexity and functionality keeps on increasing with multiple IPs packed together and design time and time-to-market keeps on decreasing amid critical constraints on PPA, there is no other alternative than to do the design first-time-right not to miss the window of opportunity. And that could be possible only when major decisions are taken at the system level with a working prototype optimized after couple of iterations, which can then be refined through design flow to get the actual silicon. At the system level, Interconnect IP plays a major role in optimizing the overall design and hence it has to be versatile to be used in optimum configuration taking into consideration various aspects such as traffic in the system, memory access bottlenecks, CPU latency limits, routing congestion and so on.

It was extremely inspiring attending a webinar, offered jointly by ARMand Carbon Design Systems, on “Pre-silicon Optimization of System Designs using the ARM CoreLink NIC-400 Interconnect”.

What an impressive network interconnect, it can be configured in most optimal way to achieve target performance while keeping power and area within budget. Multiple masters can be dynamically scheduled, according to priority, to access minimum costly shared resources such as DDR bandwidth with proper data traffic management without creating any routing congestion, thus receiving best QoS (Quality of Service) at least cost. The AMBA Designer provides GUI for easily configuring the interconnect that minimizes CPU latency and sets multiple clock domains to gain best performance and power saving. Fast timing closure can be achieved through registering options and configuring Thin Links between different NIC-400 switches requiring less wiring.

Often high bandwidth IPs can flood the system with traffic causing congestion that can block the requirements from Real-time masters such as LCD (in the above picture) and connections from low latency components such as CPUs, thus rendering priority masters starve from accessing memory and causing system performance degradation. This kind of congestion is controlled by dynamic QoS regulation where real-time masters and low latency connections get priority according to their QoS value. Of course, a high bandwidth IP can raise priority if starved. CoreLink QVN-400 goes a step further by providing arbitrated Virtual Networks for different kinds of traffic for their assured paths to memory controller.

That’s about the interconnect optimization, now how to make pre-silicon assessment for the optimality of the overall design and ensure that the same level of PPA remains down the design stream? That’s where Carbon’s Virtual Prototyping platform along with its excellent tools for accurate system prototyping comes into picture. After setting up the interconnect, important system components such as CPUs, GPUs, memory controllers and internal IPs are added and the system is exercised with bare metal software. The system level performance is optimized through booting the OS.

To get 100% accurate results, 100% accurate models for the entire system are needed. Carbon provides IP Exchange Web Portal where 100% accurate model of an IP can be compiled automatically from its corresponding RTL. As an example, CoreLink AMBA Designer IP-XACT file can be uploaded to the web portal, 100% accurate model created from ARM RTL and link to down the accurate model provided to the user via e-mail. Accurate virtual models from leading IP providers including ARM, Arteris, Cadence, CEVA, Imagination, Mentor, Netspeed, and others can be made available from the portal.

For driving the system, analyzing traffic and optimizing; traffic between producers and consumers are parameterized to mimic the modeled component. The system can be iterated over with different configurations, simulations and analyses with parameterized as well as Vector Playback (more realistic, obtained from components) and Programmed Traffic to target real functions. Also, any generic component can be replaced with its real model and the system re-tested for further optimization with the true model.

Carbon ModelStudio can be used to carbonize any model to link it with another model at different level of transaction, for example a CA model of ARM Mali GPU can be carbonized and put together with any other ARM Fast Model. A system can be constituted with various kinds of models; carbonized, accurate model obtained from IP Exchange portal, existing model or even model in SystemC or C++.

Carbon’s SoC Designer Plus virtual platform provides a remarkable capability, ‘Swap & Play’ where the system running in LT model can be changed to 100% CA at any point as desired, thus allowing cycle accuracy without actually booting Linux in CA model. After quickly booting Linux or Android, multiple checkpoints (CPs) can be created for firmware/driver engineers who can then ‘independently’ debug and validate their code against an accurate system. At OS level, system benchmarks can execute for many billions of cycles. Execution at multiple checkpoints can proceed in parallel to provide results in hours rather than days, thus enabling fast and accurate performance analysis.

Carbon offers a large variety of pre-built virtual prototypes which they call CPAKs (Carbon Performance Analysis Kits). They have over 100 of these today featuring advanced ARM IP, include 12 that feature ARM’s NIC-400. A CPAK provides pre-built extensible virtual prototype with reconfigurable memory and fabric, and pre-build bare-metal s/w and OS ports. Carbon provides ‘Swap & Play’ enabled CPAKs along with source code for all s/w components, downloadable any time from Carbon’s web portal.

It was a great learning session presented at length by William Orme from ARM and Bill Neifert from Carbon, followed by an interesting demo by Eric Sondhi from Carbon, which included multiple real world case studies to show how system is brought up fast and system level performance analysis with 100% accurate models done reasonably fast. There was an involved Q/A session at the end. Check out the on-line webinar including demo here to get the actual detailed insight.

Also read –

https://www.legacy.semiwiki.com/forum/content/3072-how-develop-accurate-yet-high-performance-models.html

https://www.legacy.semiwiki.com/forum/content/3000-taming-interconnect-real-world-socs.html

More Articles by Pawan Fangaria…..

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Interface IP Protocols: Status

Interface IP Protocols: Status
by Eric Esteve on 09-16-2014 at 3:52 am
Categories: IP

If your company develops Design IP to support well-known protocols like USB, PCIe, HDMI, DDRn memory controller, MIPI specification (and more), it’s crucial to know your competition, the market size by segment, and even more important the market potential by segment. The latest can be obtained by the Compound Annual Growth Rate (CAGR) calculated on actual data, or the revenue made in the past, in conjunction with a realistic forecast calculated through a clearly defined methodology.

If your company develops IC or System-on-Chip (SoC) and source Controller or PHY IP externally, it’s also critical to select the right protocol, then the best IP vendor. The right protocol will guarantee that your product is well positioned in the targeted segment and will interoperate properly with the other IC, ASSP, ASIC or FPGA. The right protocol will also have to be supported by a standardization organization, working to support an aggressive enough roadmap: if you use the Release 2.0, you want to make sure that Release 3.0 will exist, so your investment (design resource, marketing) will be made for the long term. The right vendor will be this able to guarantee the best (features, performances and quality) to price ratio, but not only! We will come back later to the various parameters weighting in the buying decision process…

The above picture, extracted from the “Interface IP Survey” last version (Release 6), is published for the first time and it’s for Semiwiki readers. The key information is the CAGR value for 2008-2013 IP revenues generated by all vendors involved into USB, PCIe, DDRn, MIPI and HDMI (license only). A 19% CAGR clearly indicates that the adoption for interface protocols is strong, not limited to few high end applications, but industry wide. This CAGR value also confirms that chip makers tend to source externally IP functions that they may had designed five years ago. The next question immediately arises: will IP revenue continue to grow, if yes, at which rate?

Answering this simple question will require a complete, comprehensive analysis by protocol. In fact, to be in the position to build a (credible) forecast, an analyst like IPNEST has to work hard on the market understanding, segment by segment, protocol by protocol. A high level view of the global IP market may be enough for Wall Street analyst, but not for building strategy planning! That’s why the Interface IP Survey answers to the following questions:

  • IP vendor ranking by 2013 IP License revenue, by protocol, for USB, PCI Express, HDMI, SATA, MIPI, DisplayPort, Ethernet and DDRn Memory Controller,
  • IP vendor ranking, protocol by protocol, for the last 5 years
  • 5 years cumulated revenue by protocol for the leaders (such information can be linked with the IP robustness and quality)
  • Competitive analysis by protocol: an exhaustive review of all the vendors, not only the leaders, will provide a complete picture, as well as information for potential acquisition (Evatronix or Transwitch acquisition by Cadence)
  • Pricing Information: Controller and PHY IP license price (by technology node for PHY)

The picture below (once againbuilt specifically for Semiwiki readers, never published before!) help understanding that the growth behavior is not similar for all standard related IP. The survey also integrates an analysis, by standard, explaining the reasons for such behavior…


At this stage, you may think that you real concern, and the most crucial question is related to the future. You expect to see a forecast, and you want it by protocol, like me!
Building a forecast is probably the most complicated piece of work, as many different parameters are interlinked, so you need to extract the various parameters, rank it by respective impact and models it. You need to define the right methodology. In the 2014 version of the Interface IP survey, our methodology is:

  • Extract the number of design start including a specific standard (say, PCI Express), from the revenues made by the IP vendors last year. At this stage, you need to know who sell Controller IP only, or PHY IP only or an integrated solution, the above mentioned comprehensive analysis will help you to answer.
  • Evaluate the “IP sourcing” penetration rate for this specific protocol, in respect with the TOTAL design starts. An IP sourcing rate of 50% tells you that the total number of design starts is twice the above calculated number.
  • Calculate this TOTAL design starts number, by protocol.
  • Evaluate this TOTAL number evolution for the 5 next years. In fact, if the industry agrees about the fact that ASIC and ASSP design start tend to decrease in the future, this TOTAL number may increase, due to the standard pervasion within the industry.
  • Once this evaluation has been made for the next 5 years, by protocol, you have to make another assumption: evolution of the penetration rate of external sourcing (may vary by protocol), for the PHY and for the Controller (may be different).
  • Now, you can start to calculate the 5 years forecast. And when you have a doubt and need to make a new assumption, the answer will be strongly linked with your market understanding… that’s why the version 6 of the Interface IP survey is certainly the best ever written!

This forecast is currently in the validation stage, and the complete survey will be available before the end of September. You may find additional information here and the Table of Content for “Interface IP Survey 2010-2013 – Forecast 2014-2020” will be available soon (you may contact me through Linkedin if you want to receive it as soon as it will be completed).


Eric Esteve from IPNEST –

This survey is applicable to:

  • IP vendors

    • Marketing, Strategy Planning
    • CEOs
  • Silicon Foundries, ASIC companies

    • IP Marketing
    • Ecosystem and IP Qualification Managers
  • Research Consortium (IMEC, KSIA, Etc.)
  • Chip Makers (IDM or Fabless)

    • IP Purchasing Managers
    • IP Outsourcing Managers

IPNEST is the leader on the IP dedicated surveys, enjoying this long customer list:[INDENT=3]Synopsys, (US)
Cadence, (US)
Rambus, (US)
Arasan, (US)
Denali, (US) now Cadence
Snowbush, (Canada) now Semtech
MoSys, (US)
Cast, (US)
eSilicon, (US)
True Circuits, (US)
NW Logic, (US)
Analog Bits, (US)
Open Silicon, (US)
Texas Instruments, (US)
INTEL, (US)

PLDA, (France)
Evatronix,(Poland)
HDL DH, (Serbia)
STMicroelectronics (France)
IMEC, (Belgium)

Inventure, (Japan) now Synopsys
“Foundry” (Taiwan)
UMC, (Taiwan)
GUC, (Taiwan)
KSIA, (Korea)
Sony, (Japan)
SilabTech, (India)
Fabless,(Taiwan)

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Taiwan Trip Report: The Coming Simulation Crisis!

Taiwan Trip Report: The Coming Simulation Crisis!
by Daniel Nenni on 09-15-2014 at 7:00 am
Categories: EDA, Solido

Even though the flight to Taiwan is somewhat difficult, I really do enjoy my trips to Hsinchu. In addition to the top two pure-play foundries being there, one of the top SoC companies (MediaTek) and many of the leading semiconductor design companies are there as well. All are a quick taxi ride from my home away from home, the Hotel Royal.

This trip was with the CEO of Solido Design Automation. Solido even provided copies of “Fabless: The Transformation of the Semiconductor Industry” for the people we had meetings with. If you look closely at the bottom of the book in the picture the black stripe says “Compliments of Solido Design Automation”. You probably didn’t even notice the book since a beautiful girl is holding it. That is Etta Pincham, one of the best EDA sales people I have had the pleasure to work with.

Traveling the world with the CEOs of emerging technology companies is what I do during the day. I’ve done this with more than a dozen companies in the last 6 years and let me tell you it is quite an experience. Watching these entrepreneurs present their companies to the foundries and the top fabless semiconductor companies is an education in itself. One of the more interesting things I discovered during this trip is the coming SPICE simulation crisis. I will write about this in more detail later but here is the one paragraph version:

With the acquisitions of Magma (FineSim) and Berkeley Design Automation (AFS), SPICE licenses are more difficult to come by. These acquisitions coupled with the increasing amounts of simulations and longer simulation times required for double patterning and FinFETs mean companies will not be simulating as much as they should. Solido is already one of the beneficiaries of this crisis since their Variation Designer tool dramatically reduces the amount of simulations for memory, standard cell, analog, RF, and custom digital design. If you don’t believe me I can point you to solido customers who will tell you the same.

Solido will also be presenting and exhibiting at the TSMC OIP Forum on September 30[SUP]th[/SUP] at the San Jose Convention Center this month if you would like to meet them. Speaking of the TSMC OIP Forum, the detailed agenda is HERE. If you haven’t already registered you should do so immediately as this event will definitely fill up if it hasn’t already. I hope to see you there. Let me know if you will be there in the comments section and I will bring you a book, compliments of Solido of course.

The TSMC Open Innovation Platform® Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practice in TSMC’s design ecosystem will highlight the event.

More than 90% of last year’s attendees last year said that the Forum helped them “better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to leverage their technology to your design challenges!

This year, the forum is a day-long conference kicking-off withTrend-setting addresses and announcements from TSMC executives.

The technical sessions are dedicated 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion featuring up to 80 member companies showcasing their products and services.

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Intel Core M vs Apple A8!

Intel Core M vs Apple A8!
by Daniel Nenni on 09-14-2014 at 10:00 am
Categories: Foundries, Intel Foundry

There were two big announcements last week right in my backyard and I missed them both! Instead, I was in Taiwan investigating yet another big development and all three of these events will intersect next year, absolutely.

At IDF in San Francisco Intel outlined the new 14nm Core M. This is an impressive CPU, one that will fill the now half empty Intel fabs. I was even told that the shuttered fab in Arizona will be re-opened for added 14nm capacity in 2015. That is great news as there is nothing sadder than an empty $5B fab, absolutely.

Apple announced the hotly anticipated A8 (iPhone6) and was much more forthcoming with technical information than before. They certainly are proud of this SoC and if you take a close look at the specifications you will know why. It is….. wait for it….. LEGENDARY! Apple disrupts the semiconductor industry yet again!

The news out of Taiwan is the TSMC 16FF+ process, which Morris Chang said would be delayed until 2H 2015, has been pulled into 1H 2015 which puts it into reach of the coveted Apple business. Since Apple releases new iProducts in the Fall of each year the foundries have to lockstep with the rest of the Apple supply chain and deliver wafers in 1H 2015.

Going back to my blog, Who will Manufacture Apple’s Next SoC?, I suggested four different scenarios based on process release schedules. Now that TSMC 16FF+ is back in Apple lockstep TSMC wininng the A9 is not just possible, it is probable. In fact my prediction now is that Apple will use both Samsung 14nm and TSMC 16FF+, splitting them between the iPhone and iPad products. The foundry with the best yield wins! Anybody want to bet a lunch on this?

The interesting thing to note about the A8 vs Core M is that at TSMC 20nm Apple was able to pack in 2B transistors while Intel was only able to pack in 1.3B at 14nm. Apple’s die size is a tad larger (89mm2 vs 82mm) but seriously, this is a 20nm planar versus 14nm FinFET comparison and where is Intel’s so called transistor density superiority?!?!?!?! Let’s wait for the teardown and benchmarks but this has got to be a humbling experience for Intel. Kind of like when Apple released a 64-bit SoC last year and Qualcomm wet themselves.

The other interesting thing to note from IDF is that BK (Intel CEO) talked up the coming Sofia SoC which is manufactured by TSMC at 28nm. Sofia is for the low end smartphone market. The question I have is: Why didn’t BK talk up Broxton which is the 14nm SoC targeted at the Apple A8 class of SoCs? The answer I believe is that Broxton is cancelled and Intel’s mobile strategy is being scaled back. How about a little transparency here Intel? Now that the PC and server market has come back to life and your 14nm fabs will be full of CPUs, are you going to give up on SoCs? Or are you pushing your smartphone strategy out to 10nm?

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Pole Pole All the Way to the Top

Pole Pole All the Way to the Top
by Paul McLellan on 09-13-2014 at 6:25 pm
Categories: General

We made it! I have stood on the highest point in Africa, Uhuru Peak of Kilimanjaro.

Obviously this blog entry is totally off-topic. If you want to read about semiconductors and stuff, you can skip it.

So how do you get to the top of a nearly 20,000’ mountain? Slowly.

Slowly on two different levels. The first level is giving your body time to acclimatize to the altitude. And the second is to go so slowly that you minimize the demand for oxygen as you ascend.

We took 5 days to acclimatize. Each day we would go higher to a new camp. But more importantly, we would be higher still during the day and then come back down again, or take an acclimatization hike out of the camp to a high point nearby. “Climb high, sleep low.” With weight training, it is the rest days when your body rebuilds your muscles stronger. In the same way, it is at low level that your body adjusts to the altitude stress you just endured.

The second slow is going up the mountain. “pole, pole” the guides say the whole time. “Pole” is the Swahili for slow (pronounced like “pawley”). You move your feet very small steps, not very fast, but you are still making progress. On a steep slope the speed might be only be half-a-mile per hour but by going so slowly you are not demanding more than your body can deliver with the limited oxygen and you don’t find yourself panting with your heart racing, which happens if you try and go too fast.

From our base camp at about 15,000’ we went for the summit leaving at 11.30pm in the dark. It was a full-moon so head-lamps were barely needed. The first part is not too hard since your body is already used to heights like that. Plus you are walking on sooth gravel underfoot, so it is easy to set up a rhythm and stick to it. The last 500m (1/4 mile) to the crater rim (Gilman’s Point) are really tough. You are already up at about 18,000’ and you can’t really go “pole, pole” since you are clambering over big rocks and stepping up, your body is telling you to stop, you are short of breath needing to stop and rest every minute or so. Eventually you make it to Gilman’s point, which is on the crater rim (Kilimanjaro is a volcano, or a volcono as the spelling error on the carved sign on the summit has it). You want to rest but it is sub-zero centigrade, maybe 10F. The water bottles are a mixture of ice and water, the camelback hoses have frozen up. It is comparatively flat to go around the rim to the real summit, just a few hundred feet of ascent, but it is still about an hour and a half to get there. “pole, pole”.

In reality, the last part around the crater is a 3 hour round trip for a photo in front of the sign on the summit. But what a photo. As the sun comes up it starts to get warmer. There were even some people doing the ice-bucket challenge, which was pretty insane given the air temperature. Then it is down again. Lunch. Then an 8 mile hike to the next camp further down towards the entrance. That day is about 15 miles of hiking over about 18 hours with one meal.

Our group consisted of 7 people, the four of us, another Paul from Singapore, Dipankar from Calgary, and Eric from New Mexico. Eric was black and he asked our lead guide Harold, who has been a guide there for 22 years, how many black guests he had taken up. “One” he said. “One before me,” Eric replied. “No, you are it.” All the guides and porters are black Tanzanians but I still find it amazing that he was the first black client in over two decades. “Black guys don’t ski” is a cliché, but apparently they don’t do Kilimanjaro either.

This was the first trip I have done with porters carrying gear. Our party was 28 people. The 7 of us. Harold, the lead guide. Nelson and Emmanuel the other guides. And 18 other people, mostly porters but also a chef and a cook. We ate our meals in a big tent sitting in canvas chairs with a table covered with a cloth. It felt a little bit Hemingway colonial, back in the era when a safari meant shooting animals with guns not cameras. The porters carried everything we didn’t need to keep in our day-packs: tents, sleeping pads, sleeping bags, extra clothes, all the other stuff apart from waterproofs (it can rain at any time), something warm, sunscreen etc. Plus all the food, the mess tent, propane, stoves and who knows what.

So if you’re thinking of doing Kilimanjaro what would be my advice?

  • You really can do Kili with no technical mountaineering experience. It is a walk. But it is the toughest walk I have ever done, especially the last hour to the crater rim. Don’t underestimate it, even if you are fit. Being fit at sea-level will help, not being overweight will help, having hiked some high mountains before will help. But unless you have experienced that sort of altitude before you don’t know how your body will take it. Martina Navratilova didn’t make it and I did. She got altitude sickness badly and I didn’t. Even in retirement I’m sure she is way fitter than I am. You can’t take it for granted but the best way to improve the odds is to give your body time to acclimatize and don’t try and rush it. But 30-40,000 people a year attempt it and about half make it.
  • Find a good guide company. We went with Team Kilimanjaro, who are headquartered in Britain and I have nothing but praise for them (their boss has done Kilimanjaro up and back in 18 hours, which is close to the record). The cheapest you are legally allowed to do is to go with one guide and one porter but you will have a better experience if you don’t try and pretend you are still a 20-year old student.
  • If the trip is short, consider making them add an extra day. It will add a couple of hundred dollars to your bill but as a percentage of what you are already spending it is minimal. The rule of thumb apparently is that on 3-day tours 30% of people make it, 4-day tours 40% up to 7-day tours at 70% success. All seven of us made it, and our ages ranged from 49 to 72. Not young bucks.
  • You need good clothing for the final ascent. You need 3 good layers for the ascent. A good base layer, pants, and windproof pants. On top, a good base layer, a shirt, a fleece and a down/synthetic jacket with a hood. Thick mittens. Your guide company can probably rent you the stuff you don’t have.
  • If you have a porter carrying the stuff you don’t need in your day-pack, bring a few extra things like a pair of sandals (so you can take your boots off), a couple of books or a kindle. Maybe even some single malt scotch (we were dry all week since none of us had thought of that).
  • Bring some old T-shirts, hats and that sort of thing. It is traditional to give away clothing to the porters and while a 6-year old Disneyland T-shirt might not be that interesting to you, they will love it.
  • It is malaria country, although it is rare compared to down near Dar-es-Salaam and the coast. Take anti-malarial drugs. Typically you start 2 days before you get there, and continue for at least a week after you get back home. You also need other stuff like Hepatitis A/B, typhoid, tetanus if you don’t already have them. If you live in the bay area, I recommend the immunization clinic on Grove Street in the city. They really know everything and they do nothing all day but deal with people going to unusual countries. Your own doctor knows a lot less. They can give you everything on the spot, your own doctor will probably need to order stuff in and charge you more.
  • It is also safari country, with several national parks within a couple of hours drive. Having gone all the way to Africa it is great to see some giraffes, lions, zebra, elephants, water-buffalo, monkeys and more in the wild.

Bottom line: it is a wonderful experience but don’t underestimate it.


More articles by Paul McLellan…

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Sidense overlays OTP on TSMC 16nm FinFET

Sidense overlays OTP on TSMC 16nm FinFET
by Don Dingee on 09-13-2014 at 7:00 am
Categories: IP, Sidense

Process shrinks, which have served us well for most of the Moore’s Law journey, are reaching their limits. For switching transistors, the biggest problems of leakage current and gate oxide vulnerability in planar MOSFETs have led the industry to new 3D microstructures such as FinFET. For non-volatile memory, the problem is generally not speed, but endurance and reliability.

In flash memory, smaller cells are more vulnerable to wear when subjected to repeated write operations, and more susceptible to corruption related to noise from nearby cells under programming and other sources. To combat this, 3D V-NAND flash technology has moved to a cylindrical structure, stacking layers of flash cells vertically and relaxing the geometry from 1Xnm class back to 3Xnm class. This effectively packs more cells in the same die footprint, simultaneously relieving the pressure on smaller geometry cells that adversely affects endurance.

Discrete NAND flash is usually fabricated in its own bulk process with dedicated design rules, not a luxury in SoC design (barring stacked 3D substrates, which would still be costly). There have been significant advances in embedded NOR flash at larger geometries, but there are still problems at 1Xnm with respect to write endurance. The dawn of FinFET also brings the challenge of how to cost-effectively fabricate embedded flash structures; lots of research, little commercialization yet.

This makes the reflex to “just grab some flash” a bit problematic for SoC designers adopting FinFET processes right now. Fortunately, many use cases for non-volatile storage can be implemented with one-time programmable (OTP) memory. OTP doesn’t have the same write endurance consideration since each cell is only written once. It fits where the need is for a relatively small but very important space to store encryption keys, tuning parameters, and other information.

To be cost-effective, OTP should live within the confines of the process for the SoC it resides in, ideally requiring no additional process steps for implementation. Overhanging concerns with reliability naturally exist at smaller geometries, and OTP is no exception – but the right approach could manage those issues.

With that in mind, Sidense has announced a very significant breakthrough: a demonstration of OTP cells in TSMC 16nm FinFET. Initial reports are impressive: correct bit-cell operation, using a programming voltage comparable to Sidense 1T OTP in 28nm, with a 10x lower leakage current. Additionally, margins between programmed and unprogrammed cells and post-bake cell stability both appear on target.

How was this, which Sidense believes to be the first working antifuse OTP in FinFET, accomplished? Sidense shared the following diagram (but few details) exclusively with SemiWiki:


This shows how Sidense is leveraging the 3D nature of the FinFET to implement the bit cell, with “no extra steps to the process” quoting an unnamed R&D source. We didn’t get too far with inquiries for specifics, but respect that the technology is still in development and details may be patentable and changing. We do know that TSMC has done extensive work in aligning overlays on FinFETs, and is likely deeply partnered in this Sidense research.

Initial functional and reliability testing of the OTP implementation in 16nm FinFET gave Sidense and TSMC enough confidence to announce the progress, a good sign for SoC designers. This is a development to watch carefully.

Related articles:
FinFETs for your next SoC

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Expert Tool to View and Debug Design Issues at Spice Level

Expert Tool to View and Debug Design Issues at Spice Level
by Pawan Fangaria on 09-12-2014 at 7:00 am
Categories: Concept Engineering, EDA

Spice view of a design, block or fragment of the design is probably the lowest level of functional description of a circuit in terms of transistors, resistors, capacitors, interconnect and so on, which in several ways acts as an ultimate proof of pudding for any semiconductor design before manufacturing. However, it’s generally very clumsy and difficult, unless one is an expert Spice level engineer, to read and understand a design description (which may be a basic library cell) written in Spice. Not to mention, Spice levels circuits (which could be in the form of library cells) are integral part of digital, analog, mixed-signal, PCB and even MEMS designs. And it’s not possible to have large designs directly in Spice format; that’s the reason often a need arises to look at a small portion of design in Spice format. What if we have an automatic tool which can generate circuit schematic on-the-fly at any desired level of hierarchy, show multiple views in different windows including Spice source code to cross probe among them and several other features for easy debugging of a design at Spice level? I guess that will be an ultimate in getting us closer to that proof of pudding.

Although I have talked about several capabilities of Concept Engineeringaiding into SoC design, debug and verification, I realized the real value of SpiceVision PRO when I looked at its capabilities in detail and also watched a quick demo videodedicated to SpiceVision. It’s a must see to appreciate the real power of the tool.

SpiceVision provides a graphical Spice netlist viewer and analyzer for pre-layout as well as post-layout Spice including parasitic netlist in SPEF, DSPF or RSPF format. It supports 32-bit as well as 64-bit database to accommodate large SoCs. It also provides Tcl based userware API interface which can be used for advanced customization and electrical rule checks (ERC). The interface allows access to the internal database and GUI, through which users can analyze the design data and generate specific reports and design checks as desired. Selected fragments of circuit and critical paths can be easily and clearly displayed through a Cone Window feature. A circuit fragment can also be saved as a separate Spice file which can be simulated and debugged later. There is provision to export schematics into CadenceVirtuoso Schematic Editor Environment.

The design can be viewed at all possible hierarchy levels from top level to all sub-circuit levels. The hierarchy tree, source code and schematic diagram are displayed in different adjacent windows. A search engine can be used to generate a list of interest entities from which the designer can select any portion to generate the circuit diagram.

Any selected fragment or critical path can be displayed in magnified form in a Cone Window and details (such as R, C, and transistors) viewed and analyzed. The fragmented portion of the circuit can be exported as Spice netlist for partial simulation which can run 10 to 100 times faster compared to full circuit simulation.

At times, when a circuit become too much cluttered due to detailed display of parasitics, it becomes very difficult to recognize the actual circuit. SpiceVision has a feature where parasitics such as parallel capacitors can be merged to simplify the circuit. Also, the circuit can be displayed with just transistors or gates without parasitics, thus enabling designers for further design navigation and exploration.

As a final validation of the circuit, the layout at the final stage is extracted for verification which generates very large and complex SPEF and DSPF netlists with multiple critical paths. These critical paths can be displayed, analyzed and saved for critical path simulation. SpiceVision eases post-layout debugging significantly.

The specific part of a design saved in separate Spice file can also be used as IP in other designs. The symbols of components such as resistors, capacitors, transistors, current/voltage sources etc. are used as standard symbols, however they can easily link to external symbol libraries.

To get more information on this product, obtain the datasheet here.

More Articles by Pawan Fangaria…..

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Transceiver Verification of a 20nm Altera FPGA Device

Transceiver Verification of a 20nm Altera FPGA Device
by Daniel Payne on 09-11-2014 at 6:00 pm
Categories: EDA

FPGA devices are a great way to drive silicon technology development because they contain both digital and analog IP, along with sophisticated IO cells. The highest performance IOs are transceivers, and Altera has recently designed the Arria 10 device family to include up to 96 transceivers, using a 20nm technology that can achieve data rates up to 28.1 Gbps. Users just know that there is a transmit and receive pair, however inside of the FPGA there are complex building blocks to sustain these data rates:


Arria 10 FPGA Transceiver Block Diagram

These transceiver cells are really analog IP that require transistor-level circuit verification and validation to work across:

  • Process corners
  • Operating voltages
  • Temperature ranges

Multiple clock sources are used in the transceiver block diagram, one of them is called fPLL, or Fractional-N Phase Locked Loop, and it provides both integer and fractional frequency clocks, with a range of data rates from 611 Mbps to 12.5 Gbps.


Fractional-N PLL

A traditional SPICE circuit simulator could be used to verify the proper operation of this sensitive design, however you would likely have to wait days to get results with a dynamic range greater than 100dB. To get simulation results faster you might even be tempted to use a FastSPICE simulator, however the results wouldn’t be accurate enough. Fortunately, there’s a happy medium between using a SPICE and FastSPICE circuit simulator, and that is using an Analog FastSPICEtool instead. Engineers at Berkeley Design Automation(now owned by Mentor Graphics) created this product category several years ago, and it has found a growing place in the family of transistor-level simulators where speed and analog accuracy are required.Related: Analog FastSPICE Update at DAC

Mentor has nicknamed their Analog FastSPICE tool AFS, and at Altera they were able to use AFS on transceiver simulations with up to 16M elements, which included post-layout netlists. Eye diagrams are a common analysis method to evaluate how clearly a sequence of 1-0 can be sent or received.


Transceiver Eye Diagram

At the 20nm node, a more rigorous validation and characterization flow was specified at Altera to include five metrics:

  • Systematic verification under all conditions, well-defined pass/fail criteria.
  • Automated regressions for pre-layout and post-layout netlists.
  • Ensure a common design environment and simulation conditions, consistency.
  • Uncover any statistical failing corners prior to tape-out.
  • Track all validation progress.

Within the Mentor EDA tools there’s something called the Analog Characterization Environment(ACE), and this was used to ensure that the five metrics listed above were actually adhered to and accomplished. Some 250 tests were defined in this validation suite, and there were over 6,000 simulations run, including Monte Carlo.Related: Analog FastSPICE AMS — Simple, Fast, nm-Accurate Mixed-Signal Verification

With this flow you can look at statistical results to help make design decisions. The probability of each iteration is displayed in chart format with Percentage on the Y-Axis and parameter (foundry process variation) on the X-Axis:


Voltage Regulator Monte Carlo Distribution

The statistical results on the voltage regulator show that the design is not centered yet between the two red line values of 1.09 and 1.11, so tweaking the transistor sizes is required for this design to be centered for maximum yield.

Two more Monte Carlo simulation results uncovered circuits that required more tuning to meet specifications:


Rx AC Peaking Monte Carlo Results


DC Offset Results for the Secure Digital block

With over 6,000 circuit simulations used in this characterization and verification flow, accurate results were delivered in a timely fashion by using AFS technology, like:

  • Multithreading
  • Multi-core parallel
  • Distributed multi-core parallel

Many of these runs could be automatically distributed across cores in a single machine, and across multiple machines. Managers and designers could look at the progress of verification across all the characterization variations.

Summary

20nm design is demanding, requiring a massive amount of circuit simulation to characterize and verify across: corners, sweeps, Monte Carlo and nests. Altera was successful in using Mentor tools like AFS and ACE in the design of their 20nm transceivers for the Arria 10 family.

There’s a six page white paper on this topic, ready for download after a brief registration step at Mentor’s web site.