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DAC: March Update

DAC: March Update
by Paul McLellan on 03-02-2015 at 7:00 am
Categories: EDA, IP

DAC is coming up. It is already March. If you are in the EDA industry then it is basically three months away, which sounds a lot until you actually have to get everything pulled together so that your booth is ready to go on Monday June 7[SUP]th[/SUP]. Exhibit hours have been extended and now run from 10am to 7pm (only until 6pm on Wednesday). To ensure attendance that late in the day, the executive committee will be walking around the halls with rawhide whips…no wait, the evening receptions at the end of the first couple of days will be moved to the show floor. The poster sessions will also be moved to the show floor to give them more visibility. So you can read the posters while you sip a DACquiri.

Usually at DAC there turns out to be a theme, not something official but a sort of collective wisdom of the industry. My prediction for 2015 is that this is going to be the year of 10nm. Of course 10nm is not ready but the tools need to be ahead of the curve: no point in having a process ready to go and nothing to run in it. That is the semiconductor equivalent of “all revved up with no place to go.” That means that if you don’t have 10nm tools close to being shippable to early adopters and teaching customers then you are probably going to be late to market. Test chips are being designed now. IP will be needed before anyone other than the biggest, most leading edge, companies can tape out designs.

New this year is DACtv. It will be showing videos for both exhibitors and attendees. You can find it here. If you are an exhibitor and have a YouTube channel then you can be listed as an associated channel. Send a link to pr@dac.com. Videos already up on the site are Rich Nass on embedded, Daniel Bourke on the designer track, “Mac” McNamara on IP, and an interview with General Chair Anne Cirkel. Anne has also been blogging once a week here.

There is no free Monday for the exhibits, just like the last 4 years. But there will be free access through the I love DAC scheme, as there has been for those 4 years. Details nearer to the time. And if you miss the cut for I love DAC you will still be able get in for free. Email Anne Cirkel with the titles of her last three blogs and she’ll give you a free exhibit badge. I think you can thank SemiWiki blogger Daniel Payne for that last offer.

A few upcoming deadlines:

  • Submissions for the Marie Pistilli Women in EDA award are due by March 6[SUP]th[/SUP]
  • Submissions for the Richard Newton Young Student Fellow Program are due March 26[SUP]th[/SUP]
  • Submissions for the P.O. Pistilli Undergraduate Scholarship are due March 6[SUP]th[/SUP]
  • Work in Progress submissions are due March 2[SUP]nd[/SUP]. That would be today!

The DAC website, as always, is here.

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3D-IC: Embedded Passives

3D-IC: Embedded Passives
by Arabinda Das on 03-02-2015 at 1:00 am
Categories: EDA, Foundries

IEDM 2014 was held in the second week of December 2014 in San Francisco. The excitement is over now and the dust has settled. Last week, at my leisure, I was glancing through the conference proceedings and short course material from IEDM 2014, when a slide from the 3DIC short course caught my attention. The slide presented below gives an overview of different interposer substrates used in the industry.


One of the things that I remembered during this short course was the discussion about how the industry has changed its outlook on interposers. In the initial phase, it was conceived to facilitate devices with a very large number of I/O counts and thus the interposer was an extension of the packaging platform. But now it is being considered as a real estate saver, where passive devices can be embedded to reduce the overall footprint. Passive devices such as capacitors, resistors, and inductors can occupy more than 50% of the precious die area and thus if they can be removed from the processor die, it would lead to more efficient integration. This slide made me think about integrated passive devices (IPD) in an interposer and their cost evaluation. I was curious to know if any device manufacturers have got their hands dirty on this topic.

To my surprise, there was one paper from TSMC in IEDM 2014, in which they described a MIM capacitor on a Si-interposer, using Cu-Damascene process. The Si-interposer had the possibility of connecting to external devices both on the top and the bottom side. On the top portion of the topmost metal layer, a re-distribution layer is connected to a μ-bump to facilitate connection to a processor die; while at the bottom part of the substrate, a TSV is connected to a C4 bump pad to attach to the packaging substrate. I believe, at present, this is the most cutting edge story of passives in a Si-interposer.

I also searched for embedded passives on glass substrates. Glass substrates have attracted a lot of attention, especially for high frequency applications because glass has low loss properties over a wide range of operating frequencies and temperatures. Some of the main players are Georgia-Institute Technology, IMEC, ST-Micro, Frauenhofer Institute, Schott AG, Asahi Glass and Dow Corning. All these companies have very strong R&D activities in glass interposers and all of them have fabricated passives on glass and have presented their findings in several conference proceedings. In most cases, an organic BCB layer is deposited on the glass substrates and passives have been made in the organic layer. Georgia-Institute’s web site also shows passive devices using through-glass-vias.

However, in my limited search, I could not find a commercial product with IPD on an interposer, and where the interposer is connected to a processor. If so, this would make truly a 2.5D integration scheme. The same question applies also to glass substrates. Glass interposers are probably lagging behind silicon interposers as glass has some inherent manufacturing challenges compared to Si. For example, in Si substrates, all the know-how of semiconductor industry can be applied. Fine dimensions can be patterned using advanced lithography techniques, a high density of TSVs can be made on the substrate, and the carrier wafer can be easily thinned down to below 50 μm. On the other hand, glass is difficult to work with and thinning the glass substrate is quite challenging. Nevertheless, glass has its positive attributes; it can be made into panels of 900 mm x 900 mm and these large panels can generate a very high number of glass interposer substrates, almost an order of magnitude higher than Si-interposers can be diced out from a 300 mm Si-wafer, thus reducing the overall price of the glass substrates. And the low lossy behavior of glass is suitable for high frequency applications; especially for passives like inductors. Both materials have their advantages and disadvantages.

Based on research and conference proceedings, it is clear that the industry is going to use embedded passives in the interposers for miniaturization and increase of functionality. It is probably delayed because of yield, test & quality standards, and reliability issues. The processor is a product of high quality standards but if it were connected to an interposer with a passive device in it, then there would be some additional reliability concerns; especially at the connection of the processor and the interposer. The fact that rework of embedded components is not possible, it is crucial that embedded passives have a high yield. But knowing the advantages of embedded passives for system in package (SIP), the industry would soon determine the most cost effective process for 2.5D integration. There is a tremendous R&D activity by major device manufactures, research consortiums and OSAT players on interposers; so most likely, we do not have to wait long before commercial products with IPD in interposers are the mainstream and the missing blanks on the slide presented during the short course of IEDM 2014 would be completed and fully understood.

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STMicro to Showcase Turnkey NFC Design at MWC

STMicro to Showcase Turnkey NFC Design at MWC
by Majeed Ahmad on 03-01-2015 at 10:00 pm
Categories: EDA, IoT, Mobile, STMicroelectronics

Near-field communication (NFC) technology is finally realizing its potential, thanks to the impetus provided by Apple Pay, and it’s becoming evident from the pre-Mobile World Congress (MWC) buzz coming from several makers of chips, smartphones and wearable devices.

Among the companies displaying NFC products at the 2015 MWC in Barcelona is STMicroelectronics, a leading supplier of Secure Element, a special storage block typically built into an NFC controller chip that safeguards vital information like bank account numbers. The other key building block of the contactless access solution is NFC radio for which STMicro is joining hands with ams AG to put together its analog front-end chip featuring NFC booster technology in the turnkey design.

The outcome of this collaboration is a turnkey NFC design solution, which comprises of ams’ boostedNFC chip combined with ST’s system-in-package (SiP), which in turn, contains controller and 32-bit secure microcontroller for Universal Integrated Circuit Card (UICC), embedded Secure Element and microSD-card applications. According to Laurent Degauque, Embedded Security Marketing Director at STMicroelectronics’ Secure MCU Division, the common reference design can be easily integrated into mobile phones, smart watches, wearables, and Internet of Things (IoT) devices.

ST claims that the turnkey NFC design supports all important NFC standards governing card emulation, including ISO14443 type A/B, FeliCa at data rates of up to 424 Kbps, active peer-to-peer bit rates of 212 Kbps and ISO18092 communication at up to 424 Kbps. Moreover, it boasts major certifications, including Common Criteria, EMVCo and GlobalPlatform as well as certifications from Visa, MasterCard, American Express and People’s Bank of China (PBOC).

ams, the Austria-based supplier of analog ICs and sensors, claims that its AS39230 RF chip boosts the signal on the antenna while increasing the signal strength by up to 10 times when compared with conventional passive load modulation (PLM) methods of transmitting a signal from an NFC tag, card or card emulator to an NFC reader. Moreover, ams promises help for space-constrained designs through reduction in the size of the antenna by as much as 20 times, down to 100mm[SUP]2[/SUP] or less, while maintaining the same signal strength.


Block diagram of ams’ RF front-end for NFC

ST’s part in the turnkey solution—rolled into an SiP device—is made up of the ST21NFCC controller and the ST33G1M2 Secure Element. ST’s Secure Element is based on the ARM SecurCore SC300 32-bit RISC core and it comes with Common Criteria-certified security features and a large and flexible embedded eFLASH. It boasts Trusted Service Management (TSM) infrastructure compatibility and supports banking and digital access applications through compliance with Global Platform GP2.2 OS and the complete MIFARE portfolio, including MIFARE Classic and MIFARE DESFire.

ST will be exhibiting the new reference design in Hall 7, Stand 7B146 at the Mobile World Congress (MWC) in Barcelona being held on 2-5 March 2015.

2015: The Year of NFC

ST’s partnership with ams for creating an NFC system reference design underscores two crucial facts. First, ST seems to have acknowledged the critical importance of turnkey solutions after the failure of its ST-Ericsson joint venture in mobile baseband business. Chipmakers like MediaTek and Qualcomm provided complete design solutions to a horde of smartphone makers in China and won a very lucrative market.

Second, after going through a number of pain points, the NFC technology finally seems ready for a mass adoption. There had been an industry joke about “The Year of NFC” that perpetually moved to the following year. But now 2015 actually looks like the year of NFC with a number of manufacturers of smartphones and wearable devices lining up to make product announcements at the MWC floor in Barcelona.

The NFC-centric mobile payment ecosystem—mired by security concerns, resistance from mobile operators and a complicated tap-to-pay retail market—had largely been limited to pilot projects. Then, there came Apple Pay, which not only played a significant role in the astounding success of the iPhone 6, but also reinvigorated the sleepy mobile commerce market.


(Image courtesy of Visa)

Apple came up with a simple and effective solution that left mobile operators out of the mobile payment and transaction system. The Cupertino, California–based consumer electronics firm incorporated a Secure Element inside the iPhone 6 so that the Apple Pay service could be provisioned over the air by the issuing bank or the credit card company. Mobile consumers using the Apple Pay app took a picture of the debit or credit card, and after a security check, Secure Element would allow the service to mobile users with the right credentials.

Don Tait, senior analyst at IHS, had told Reuters at the launch of the Apple Pay service back in September 2014 that ST’s strong presence in Secure Element chips would give it a plenty of scalability when NFC takes off. Apparently, NFC’s moment of glory has come, and for ST it’s about time to build a leading NFC position on top of its strong presence in Secure Element components.


STMicro’s ST33G1M2 Secure Element

There is a lot of talk in the technology press about NFC coming to new smartphone models such as Samsung Galaxy S6 and connected wearables like Apple Watch. That could lead to a much bigger market for the NFC silicon—1.64 billion sockets in 2018, according to market research firm IHS.

Majeed Ahmad is the author of Mobile Commerce 2.0: Where Payments, Location and Advertising Converge. The book outlines the major building blocks of the mobile commerce business while providing success and failure stories and profile of key industry players.

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IP for IoT: Thanks for the Memory

IP for IoT: Thanks for the Memory
by Paul McLellan on 03-01-2015 at 4:57 pm
Categories: eSilicon, Semiconductor Services

The Internet of Things (IoT) is clearly the buzzword of the moment, and like many catchy phrases it also tends to mean what you want it to mean, rolling up some things that exist like the automotive market or industrial automation, along with markets for things like wearables and healthcare that are largely in the future. But however you look at it, it is clear that a lot of devices are going to be connected to the internet and so it is big opportunity even if the estimates of its market size are all over the place.

eSilicon have been looking at the success factors for IoT. They discovered that all markets can be broken down as:

  • Consumer

    • lifestyle, home, mobility (automotive), healthcare
  • Industrial

    • manufacturing, logistics, retail, services
  • Government

    • buildings, city, infrastructure, services
  • Infrastructure

    • communications, security

The (semiconductor) market leaders right now are automotive, communications, industrial and home-automation. These are segments where products are being designed and shipped now rather than just appearing as a colored bar on somebody’s 2020 powerpoint slide.

eSilicon’s approach to the IoT market is two-fold. Firstly, to automate as much as possible of the process of choosing a semiconductor process and supplier, getting quotes, getting prototypes, ramping to volume. Gartner reckon that over 50% of IoT solutions will be provided by startups less than 3 years old. Startups do not have whole departments dedicated to getting quotes or managing production operations and so reducing the friction is very important.

The second area of importance is IP. There are a number of factors that are important for IoT depending on the application, but one that is pretty much universal is power. Many IoT devices are battery powered. At the very least the battery can only be recharged or changed occasionally and, in some cases, never: the battery the product ships with has to last the lifetime of the product.


Standard power reduction techniques such as clock gating and power down will continue to be important. eSilicon have a lot of experience given the wide range of chips they build for a broad spectrum of customers. Almost any feature you can think of they already have in production or at least have seen silicon. See the table above.

Most IoT devices seem to contain a lot of memory and as a result the most important area of IP are ultra-low-power memories. For example the SoC analyzed below has 96% of the chip is memory.

eSilicon has done lots of designs incorporating 3rd party IP. They don’t design their own microprocessors, for example. But one area that eSilicon does invest in, is building differentiated memory IP. And in the context of IoT, ‘differentiated’ means ultra power (ULP), both during operation, and, especially during the long periods of time when the chip is idle, waiting for something interesting to happen. They have ULP memories available in many processes, which is important since IoT SoCs are largely not going to be designed on the most bleeding edge processes due to cost, difficulty of incorporating analog and RF, and possible sensor integration.

For many applications such as automotive the characterization of the SoCs and so also the IP contained within, is over an extended range. Your car has to work in both a Minnesota winter and an Arizona summer, and not just when the chip ships but also 20 years later. So it is not good enough to build memories that look good in typical operating conditions, they have to cover the extremes too. For example, eSilicon have delivered memory IP that is qualified up to 175°C operation.

In networking applications, the normal sorts of memories used in other applications are not enough. For packet matching they also need ternary content addressable memories (TCAMs). These allow loading and matching through “don’t care” masks. eSilicon is the largest supplier of TCAMs in the market, having delivered solutions over many years from 180nm down to 14nm and all stations in between.

On March 11th fromm 9am to 9.30am pacific, eSilicon are presenting a webinar Winning the IoT Race with the Right Chip: Customizing Memory IP for IoT Applications. It will presumably also be available for replay later like all other eSilicon webinars (which you can find here). More details on the webinar, including a link for registration, are here.

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Xilinx’s 16nm UltraScale+ FPGA is Revolutionary

Xilinx’s 16nm UltraScale+ FPGA is Revolutionary
by Luke Miller on 03-01-2015 at 7:00 am
Categories: FinFET, FPGA, Xilinx

Well a very belated Happy New Year dear reader. I must admit, it has been a very long winter and it has caused the Miller’s to rethink this vital question. “What in the world are we doing living in NY”. So we are moving, and hopefully this is my last ‘real’ winter as we headed down south. To perhaps alleviate some of the winter blues from you a bit I see Xilinx has released their16nm UltraScale+ Product Tables. You can read them here.

While much of the news and attention is on the MPSoC and the VU13P that has like near ~12,000 DSP, 128 30g SERDES, ~500Mb RAM and the kitchen sink. I really could put a complete RADAR on that chip, Amazing! Just study this figure for a few minutes.

Being a Xilinx employee I can personally attest that these parts were intelligently designed, no evolution here. There was many, many hours of hard work across all disciplines to create these FPGAs. I personally like working for Xilinx for that reason, you can participate in the product of hard team work. Then to see the FPGAs working in real systems, at the least is very satisfying. Almost like watching a mom giving birth. (Believe that do you?) Miller #8 is expected end of March Lord Willing. I shall name him “Zynq MPSoC Miller”.

Over the last few months, I heckled Xilinx via email, nicely of course, “hey can I leak just a little bit about the 16nm FPGAs?” I mean they were great written emails, proof read by the wife. I eagerly awaited my response which was ‘No’. I understood, but boy the suspense was killing me but after some patience testing, this was the week. My kids were as excited as Christmas Day. Xilinx revealed what was in store at 16nm. By me not being ‘leaky’ prevented any type of miscommunication.

Speaking of miscommunication, this is a REAL conversation I had with the wife, really. Can any of you readers of the male persuasion relate here?

  • Luke: “I’m going out, do you need me to pick up anything.” (Safe question, and necessary, 50 points)
  • Wife: “Well, we are out of hamburger, so do not get that.”
  • Luke: “huh” …(With a very complicated look on my face)

Now in ‘marriage conversation’, I believe the Lorenz dilation does in fact take place and hours go by when talking with the wife on such subjects. Men speak blue, Women pink. Please translate accordingly. Can any of you guess what she really meant?

Back to Xilinx but I needed to get that off my chest.

At 16nm remember this phrase “Tools, Tools, Tools”. I must admit you simply cannot just pick up one of these devices and start coding blindly. It is now about Tools and Architecture. The MPSoC, has ARMs, Legs, R5’s, GPU, H.264/265 , Power Management and Programmable Logic. I believe it is the time to embrace across team disciplines (systems, software, and hardware) and High Level Synthesis. You cannot simply be competitive and program these puppies by hand. C/C++, OpenCL are the key to stay portable and to keep from wheel spinning. Xilinx Vivado HLS will give you better QoR (Smaller, Faster, Denser designs).


What does 12,000 DSP and 128, 30g SERDES give you. About 20 TMACs of processing power and a plethora of options to all the revolutionary serial standards like JESD204b (c is chartering out) and Hybrid Memory Cube. Friend DDR has died, and I believe we are about to witness the death of wide LVDS ADC/DAC devices soon when lower latency is achieved in the JESD204 devices. This is why you need 128 GTs. Five years ago you probably did not. A 32 channel RADAR receiver is cake in such a part. 30g is all important. The next gen HMC, and JESD204 will need that rate, 28g will not cut it. What should you do next? Read ALL the materials which Xilinx has posted. Contact you sales rep and get more info. Get a 16nm evaluation board when available. You simply cannot beat having a fully working framework ready to go. Get HLS training, Start C/C++, OpenCL coding. Get Vivado training and for goodness sake stay warm and safe the rest of this winter!

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Faster ECOs Using Formal Analysis

Faster ECOs Using Formal Analysis
by Daniel Payne on 02-28-2015 at 7:00 am
Categories: EDA, Synopsys

Your latest SoC has just begun the tape-out process and then marketing comes back with a small update to the specification to make your design more competitive, or maybe your regression tests just found a minor bug in a single IP block that needs to be fixed. Should you go back in your design flow, change the RTL source code and then completely re-run all of the logic synthesis and physical implementation tools? Probably not, instead you likely will opt for an ECO (Engineering Change Order) flow instead to save time. Since an ECO flow is often equated with manually editing a gate-level netlist and hacking together script files, there is plenty of room for introducing new errors into a design, so be careful.

Engineers at Synopsys have come up with a method to speed up this ECO process and at the same time add some automation to ensure that you’re not introducing any new bugs. I spoke by phone with Graham Etchells and Mark Patton to get an update on their Formality Ultra flow to manage and automate the ECO flow. Here’s the concept:


Functional ECO Implementation

A design change comes in, the design engineer updates the RTL code, Formality Ultra shows you exactly where in your gate level netlist the effected net is, and the ECO scrips are generated for both Design Compiler (logic synthesis) and IC Compiler (place and route) tools. There’s a final verification that the new netlist matches the changed RTL code.

Related – Formality Ultra, Streamline your ECOs

A manual ECO approach would have you looking at your gate-level netlist with a text editor after logic synthesis, trying to find a net of interest, after all of the optimizations and you may not even find your net name. With this automated ECO approach you can visually find your net of interest at the RTL or gate level, click on it, then see where this same net is in the post-synthesis netlist:


​Highlight equivalent nets

You can now implement and view each ECO interactively by:

  • Graphically using the Verdi nECO tool

or

  • With macro commands

ECO Schematic Editing

There’s even a way to see where your changed nets are in both the RTL and layout views, helping you to understand the physical impact before committing to a change.


Cross-highlightint

Verification of each ECO now only takes minutes, because only the limited areas of the logic change are automatically identified and run. Even if your entire design is millions of gates, the ECO verification runs in minutes so you can do more what-if analysis on how to best implement each ECO.

Related – LSI’s Experience with Formality Ultra

Once you are satisfied with each ECO fix, then the scripts to control IC Compiler and Design Compiler are created automatically:


Integrated Tool Flow

Most ECO changes effect a few dozen gates, so if your RTL changes impact hundreds of gates or more then you’ll probably just re-synthesize and re-implement that part of your design instead of trying an ECO flow.

Related – How STMicroelectronics uses Formal Tools (Webinar)

Summary

SoC designers can be more productive by moving from a manual ECO flow to a more automated approach using the Formality Ultra, Design Compiler and IC Compiler flow. Instead of taking weeks on a manual ECO approach, you can now do the same work in days. The learning curve for Formality Ultra is a day or two, and customers like Cavium and Centaur Technology are shaving valuable time off their schedules.

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Mentor 2014 Results

Mentor 2014 Results
by Paul McLellan on 02-27-2015 at 7:25 pm
Categories: EDA, Siemens EDA

Yesterday Mentor announced their quarterly results. Since their financial year is not aligned with the calendar year, this was also the end of their fiscal 2015. The quarter was an all-time record with revenues of $439M and (non-GAAP) EPS of $1.09. The year was also an all-time record with revenues of $1.24B and EPS of $1.77. Half of their business comes from system companies and half from semiconductor companies.

But guidance is basically flat with 2016 forecast at $1.28B and EPS of $1.45, so revenue flat and EPS down from this year. Like Cadence and Synopsys they have initiated an early retirement program.

Sometimes you hear the opinion that Mentor makes all its money on Calibre and everything else is an also-ran. And indeed they have a more than doubling of design-to-silicon bookings this quarter. But it is not all Calibre. I assumed that synthesis, place & route (SP&R) was pretty much all Synopsys and Cadence with a sprinkling of Atoptech, but Mentor seems stronger than I realized. On the call Wally said that four of the top-ten semiconductor companies are using Mentor SP&R flows (I assume not exclusively).

To be a bit more explicit, Wally Rhines (CEO) said:Challenges with multi-patterning the 10-nanometers have provided an advantage for Mentor and the need for the increased capacity and speed of next generation logic synthesis has stimulated bookings for Oasys RTL Synthesis.

Of course if that just meant that Mentor’s sales-force had managed to stuff some SP&R tools into some customers on the back of a Calibre deal, where they then sit unused on the shelf, that would not be a total surprise. But they are not sitting on the shelf. Wally continued:During fiscal 2015 Mentor place-and-route technology was used on more than 50 tape-outs at leading edge design rules…We’ve been involved in 10-nanometer design and one of the trendsetters for the industry is now increasing their commitment to Mentor place-and-route because of the success they’ve achieved.

Another area where Mentor is strong is automotive. They have a unique wiring harness design business, and they are the only one of the big 3 EDA companies to address the embedded software market. And it is all producing results. Bookings grew 95% in fourth quarter. They have an all-star list of customer names:Customers included Daimler, Magna and Continental for advanced driver assistance, Visteon and Continental for in-vehicle infotainment, Daimler and Delphi and PSA for AUTOSAR Ethernet and safety capabilities and Lockheed Martin, Jaguar Land Rover, Boeing, Lear and Tesla for integrated electrical wiring…and purchase from Great Wall Motors, which is China’s largest manufacturer of SUVs and pickup trucks.

They expect the growth in automotive to accelerate in fiscal 2016 starting in first quarter (now). It is already 15-20% of total Mentor business.

Automotive also was a driver in the increase in services, where bookings are up 75% year-on-year. Services are often perceived as low margin business but Greg Hinckley (COO/CFO) said:Service bookings have more than doubled for us over the last five years and now approach 10% of total bookings. Service gross margins have improved by 20 points over that time. Despite an increasing mix of products and services that are assumed to carry less favorable economics, joint programs to both enhance differentiation, while driving efficiency have allowed us to maintain near record total company gross margin.

Verification overall was down slightly but emulation was up, with emulation having 6 new customers in the quarter, although as always initial purchases from new customers are small. The overall emulation business (for the industry) has been growing about 20-25%/year for the last four years. If this continues for a few more years then emulation is going to be a big part of EDA. Mentor had a huge order in emulation in Q4 last year, which won’t repeat. In fact they expect no bookings from that historically largest customer this year. Emulation, since it is hardware, is almost always sold as a permanent license not a ratable license like most software, meaning that a big order from a customer one year typically means it is some time before they will need to place another big order. Mentor expects emulation to grow this year, but reading between the lines, not by much.

Integrated System Design (mostly PCB) was down a lot, 45%, partially due to a very strong fourth quarter in mil-aero last year leading to a tough compare.

I don’t know how much you can read into Mentor’s bookings by region to deduce anything about the overall macro-economic climate but the numbers are interesting anyway:

  • Pacific-Rim was up 175% (driven by design-to-silicon)
  • US was up 30% (driven by automotive)
  • Europe was down 30%
  • Japan was down 70% (ouch)

By the way, nothing was said (and nobody asked) about the rumored Mentor acquisition of Tanner EDA.

SeekingAlpha transcript of the earnings call is here.

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Sonics vs Arteris Lawsuit Update!

Sonics vs Arteris Lawsuit Update!
by Daniel Nenni on 02-27-2015 at 3:00 pm
Categories: Arteris, IP, Sonics

As strange as it may seem one of my hobbies is reading case law. It’s not only interesting to see what the human race is really up to, it is also good to know your rights in regards to things like defamation, especially when you are a New Media mogul like myself. Some of the funnier defamation cases are called “Twibel” as in libel on Twitter. Did you know that you risk legal action if you re-tweet a defaming tweet? Well, now you do. It may only be 140 characters but it could cost you millions of dollars in legal nonsense. Posting on LinkedIn is even more risky since your current employer is attached to everything you do.

I also follow the legal actions in our industry. Mostly because it makes for interesting reading but also because one of the things I do during the day is help keep my consulting clients out of trouble. Seriously, I have seen some very petty behavior amongst the fabless semiconductor ecosystem companies turn into multi-million dollar legal liabilities, absolutely.

Speaking of that, Sonics just posted an update to their legal action against Arteris:

Sonics vs. Arteris Lawsuit(s) Fact Sheet — As Of February 2015

Fact: Sonics is suing Arteris andArteris is activelyinvolved as defendant in the legal case brought by Sonics against Arteris in November 2011. The case was filed in the United States District Court, Northern District of California. The judge has allowed the case to be put on hold (stayed) until the patent re-examinations are completed. EE Times coverage of the original filing of the lawsuit can be foundhere. A copy of the original filing can be foundhere.

Fact: Both Sonics and Arteris must provide information to the judge in a “Joint Status Report” every 6 months. The most recent report was filed in February of 2015. The report is signed by the lawyers of both companies, a copy of which is available at thewww.pacer.gov website.

Fact: With the past and continued sale of its NoC products in the market place, Sonics asserts that Arteris continues to infringe upon Sonics’ patents.

2) Arteris’ suit against Sonics for infringing two Arteris patents dismissed by the court

Fact: Arteris brought a legal case against Sonics in January 2012.Sonics rejected those claims.

Fact: Arteris’ case against Sonics has been dismissed by the court and since the Arteris patents are now owned by Qualcomm, Qualcomm entered into a covenant not to sue. See,Sonics Announces Patent Non-Assert Agreement with Qualcomm–July 2014. This agreement has no effect on Sonics case against Arteris which is still being litigated. Given that Arteris has sold all of its patents to Qualcomm, Sonics believes this provides some additional protection from future claims by Qualcomm and Arteris.

3) Arteris attempts to use the US Patent and Trademark Office (“US Patent Office”) to re-examine the patents asserted by Sonics against Arteris

Fact: Arteris attempted, but failedto put all sevenof the Sonics patents named in Sonics lawsuit against Arteris into re-examination with the US Patent Office. Sonics Patent No. 6,182,183 in its entire and original form overcame the challenge by Arteris in the Patent Office.

Fact: Those patents that aresubject to re-examination are still in processat the US Patent Office.

Fact:The US Patent Office maintainsstatistics about outcomes of re-examination proceedings. By all measures, Sonics’ patents are performing far better than the averages.

The interesting twist here is the Arteris technology acquisition by Qualcomm which brings me to the following questions: What does it mean to Qualcomm and their customers if Sonics prevails? Why didn’t QCOM do a preventive patent licensing agreement like ARM did? Is this a “WE HAVE MORE EXPENSIVE LAWYERS THAN YOU DO” situation?

Let’s not forget a little IP company called Tela sued QCOM’s customers and recently won a rumored $130M settlement. Preventative patent licensing agreements are a fraction of litigation which is why enlightened companies do them, right? Unless of course your legal staff has nothing better to do…

Also Read: The PTAB Inter Partes Review process: Danger, Will Robinson

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New CEVA-XM4 vision IP does point clouds and more

New CEVA-XM4 vision IP does point clouds and more
by Don Dingee on 02-27-2015 at 6:00 am
Categories: Ceva, IoT, IP

When Intel created the OpenCV vision processing library, the idea was algorithms could take advantage of the single instruction multiple data (SIMD) capability in Intel architecture processors. (Intel’s ulterior motive is always to sell processors.) As the library has matured, optimized functions take advantage of SSE or AVX.

If you have enough cores, memory, fans, and a wall plug, you can run some very sophisticated vision processing techniques on an Intel desktop processor. The problem with scaling SSE or AVX, or any add-on vector instruction set in a general purpose CPU, is you have to bring the rest of the scalar elements of the architecture along for the ride, burning real estate and power. Intel is hoping to solve this with “Skylake”, shrinking everything until it all fits.

From another direction, the GPU guys got in the act. GPUs are designed primarily to handle large numbers of polygons, shading, and physics. They operate on threads, which usually render an object. By shackling threads together in hardware and software, one can create cores that are in essence vector processing engines.

This is why Intel “Cherry Trail” is getting so much attention. Ditto for the NVIDIA Tegra X1, with its four ARM Cortex-A57, four Cortex-A53, and 256 Maxwell core GPU. In today’s multimedia tablet environments, a GPU is certainly along for the ride anyway, so slimming down the CPU and beefing up the GPU is a good tradeoff. All good, if you have something like 15W handy to power either of those chips.

Many embedded applications run on something more like 1.5W, or less. If you want to put vision processing in that kind of a product, you need an entirely different approach. CEVA has announced the CEVA-XM4, their fourth-generation vision processing IP block.

What kinds of algorithms are we talking about, and why won’t a smartphone-class mobile GPU handle them? For those interested in computer vision, “Computer Vision Metrics” by Scott Krig (available as a free e-book) is a great resource to decipher the history of vision algorithms. He sets up an interesting taxonomy of vision processing:

Figure 2-6 from “Computer Vision Metrics”, Scott Krig, Apress, June 1, 2014.

Here’s the catch: mobile GPUs are made to render known objects, not analyze images to identify and track an object across a scene. That takes horsepower. Some imaging algorithms do work well, but operating on point clouds is a good example of one type of operation that can tax a small GPU beyond its usefulness. Point clouds are becoming increasingly important for 3D object recognition in mobile robotics, and embedded vision in general.

The CEVA-XM4 vision IP is optimized for operations across the processing taxonomy. By stripping away extra stuff and concentrating on a fast vector processing unit, it can operate on a 4096-bit wide swath of data in a single cycle, keeping memory bandwidth under 512-bits. Compared to the NVIDIA Tegra K1 (similar in power, about half the performance of the Tegra X1), CEVA says they can perform object detection and tracking in 1/10 the power using only 5% of the die area.

The IP block also includes support for user-defined accelerators, allowing further customization for specific applications. Its Harvard architecture splits instruction and memory, keeping the flow of vision data smoother.

CEVA is also looking at more advanced algorithms for the CEVA-XM4, particularly a class of deep learning and convolution neural network (CNN) that allow embedded vision to take on more intuitive operations. This could be important for automotive ADAS applications, where the object presenting an issue could be just about anything in a very complex scene. Correctly identifying objects of interest, and preventing false positives, in real-time is crucial.

The CEVA-XM4 outperforms its CEVA-MM3101 predecessor by up to 8x in computational speed, with 35% better energy efficiency. The CEVA-XM4 will be on display in the CEVA booth at Mobile World Congress 2015.

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Atmel’s new car MCU tips imminent SoC journey

Atmel’s new car MCU tips imminent SoC journey
by Majeed Ahmad on 02-26-2015 at 4:00 pm
Categories: EDA, IoT

The automotive industry has reached a new era marked by giant initiatives like infotainment, connected car and semi-autonomous vehicles. And no one seems more excited than the MCU guys who have been a part and parcel of in-car electronics for the past two decades. However, the humble microcontroller is going through a profound makeover in itself in order to come to terms with the demands of the connected car environment.

Take Atmel Corp., one of the top MCU suppliers, who has launched its SAM DA1 family of microcontrollers at the Embedded World 2015 show in Nuremberg, Germany. The automotive-grade ARM Cortex-M0+-based MCUs come with capacitive touch hardware support for human-machine interface (HMI) and local interconnect network (LIN) applications. The SAM DA1 series integrates peripheral touch controller (PTC) for capacitive touch and eliminates the need for external components while minimizing CPU overhead. The feature is aimed at capacitive touch button, slider, wheel and proximity sensing applications.

Moreover, SAM DA1 microcontrollers offer up to 64KB of Flash, 8KB of SRAM and 2KB read-while-write Flash. The other key features of SAM DA1 series include 45 DMIPS and up to six serial communication interface (SERCOM), USB and I[SUP]2[/SUP]S ports. SERCOM is configurable to operate as I[SUP]2[/SUP]C, SPI or USART, which gives developers flexibility to mix serial interfaces and have greater freedom in PCB layout.

The automotive-grade MCUs—operating at a maximum frequency of 48MHz and reaching a 2.14 Coremark/MHz—are qualified to the AEC Q-100 Grade 2 (-40 to +105degreeC). According to Matthias Kaestner, VP of Automotive at Atmel, the company is targeting the SAM DA1 chips for in-vehicle networking, infotainment connectivity and body electronics.


Automotive touch surface demo at Embedded World 2015

The fact that the SAM DA1 devices are based on high-performance ARM cores clearly shows a trend toward gaining the ability to run more tasks on the same MCU. The Cortex-M0+ processor design comes with a two-stage pipeline that improves the performance while maintaining maximum frequency. Moreover, it supports a new I/O interface that allows single cycle accesses and enables faster I/O port operations.

That’s no surprise because the number of electronic control units (ECUs) is on the rise amid growing momentum for connected car features like advanced driver assistance systems (ADAS). However, a higher number of ECUs will make the communication among them more intense; so automotive OEMs want to reduce the number of ECUs while they want more value from the MCU.

Moreover, car vendors want to bring down the number of ECUs to avoid complexity within the larger car network. The outcome of this urge is the integration of more performance and functionality onto the MCU. Each ECU has at least one microcontroller.

Atmel and the Evolution of MCU

Atmel’s SAM DA1 device is another testament that the boundaries between MCU and SoC platforms are blurring. The fact that these MCUs are targeting highly sophisticated connected car applications like infotainment and ADAS means that the journey toward bigger and more powerful chips is now inevitable.

Atmel is an MCU company, and this product line has played a crucial role in its transformation that started in the late 2000s. At the same time, however, the San Jose, California–based chipmaker seems fully aware of the critical importance of the system-level solutions. Atmel calls the SAM DA1 family of chips MCUs; however, its support for more peripherals, larger memories and intelligent CPU features show just how much the MCU has changed over the course of a decade.


Memory Protection Unit in Cortex-M0+

Atmel has a major presence in the automotive market with its MCUs and touch controllers being part of the top-ten car vendors. It’s interesting to note that, beyond its MCU roots, Atmel has a lot of history in automotive electronics as well. Atmel was one of the first chipmakers to enter the automotive market.

Moreover, Atmel bought the IC division of Temic Telefunken Microelectronic GmbH for approximately $110 million back in 1998. Telefunken was an automotive electronics pioneer with an early success in electronic ignition chips that made way into Volkswagen cars back in 1980.

The release of SAM DA1 series marks a remarkable opportunity as well as a crafty challenge for Atmel in the twilight worlds of MCU and automotive electronics. Tom Hackenberg, senior analyst at IHS, calls the phenomenon ‘SoC on wheels.’

Hackenberg says that the automotive industry consumed approximately a third of all MCUs shipped in 2013. However, now there is an SoC on the road, the brain behind the connected car, and it commands a deeper understanding of the AEC-Q100 standard for automotive quality and ISO 26262 certification for car’s functional safety.

Atmel’s AvantCar touchscreen demo at the CES 2015

The integration of touch controller into SAM DA1 chips can be an important value proposition for the car OEMs who are burning midnight oil to develop cool infotainment platforms for their newer models. Next, while AEC Q100 Grade 2 qualification is a prominent part of the SAM DA1, Atmel might have to consider augmenting the ISO 26262 certification for functional safety, a vital requirement in ADAS and other connected car features.

Image credit: Atmel Corp.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.