Primarius Webinar Banner 1
WP_Term Object
(
    [term_id] => 158
    [name] => Foundries
    [slug] => semiconductor-manufacturers
    [term_group] => 0
    [term_taxonomy_id] => 158
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1075
    [filter] => raw
    [cat_ID] => 158
    [category_count] => 1075
    [category_description] => 
    [cat_name] => Foundries
    [category_nicename] => semiconductor-manufacturers
    [category_parent] => 0
)

3D-IC: Embedded Passives

3D-IC: Embedded Passives
by Arabinda Das on 03-02-2015 at 1:00 am

IEDM 2014 was held in the second week of December 2014 in San Francisco. The excitement is over now and the dust has settled. Last week, at my leisure, I was glancing through the conference proceedings and short course material from IEDM 2014, when a slide from the 3DIC short course caught my attention. The slide presented below gives an overview of different interposer substrates used in the industry.


One of the things that I remembered during this short course was the discussion about how the industry has changed its outlook on interposers. In the initial phase, it was conceived to facilitate devices with a very large number of I/O counts and thus the interposer was an extension of the packaging platform. But now it is being considered as a real estate saver, where passive devices can be embedded to reduce the overall footprint. Passive devices such as capacitors, resistors, and inductors can occupy more than 50% of the precious die area and thus if they can be removed from the processor die, it would lead to more efficient integration. This slide made me think about integrated passive devices (IPD) in an interposer and their cost evaluation. I was curious to know if any device manufacturers have got their hands dirty on this topic.

To my surprise, there was one paper from TSMC in IEDM 2014, in which they described a MIM capacitor on a Si-interposer, using Cu-Damascene process. The Si-interposer had the possibility of connecting to external devices both on the top and the bottom side. On the top portion of the topmost metal layer, a re-distribution layer is connected to a μ-bump to facilitate connection to a processor die; while at the bottom part of the substrate, a TSV is connected to a C4 bump pad to attach to the packaging substrate. I believe, at present, this is the most cutting edge story of passives in a Si-interposer.

I also searched for embedded passives on glass substrates. Glass substrates have attracted a lot of attention, especially for high frequency applications because glass has low loss properties over a wide range of operating frequencies and temperatures. Some of the main players are Georgia-Institute Technology, IMEC, ST-Micro, Frauenhofer Institute, Schott AG, Asahi Glass and Dow Corning. All these companies have very strong R&D activities in glass interposers and all of them have fabricated passives on glass and have presented their findings in several conference proceedings. In most cases, an organic BCB layer is deposited on the glass substrates and passives have been made in the organic layer. Georgia-Institute’s web site also shows passive devices using through-glass-vias.

However, in my limited search, I could not find a commercial product with IPD on an interposer, and where the interposer is connected to a processor. If so, this would make truly a 2.5D integration scheme. The same question applies also to glass substrates. Glass interposers are probably lagging behind silicon interposers as glass has some inherent manufacturing challenges compared to Si. For example, in Si substrates, all the know-how of semiconductor industry can be applied. Fine dimensions can be patterned using advanced lithography techniques, a high density of TSVs can be made on the substrate, and the carrier wafer can be easily thinned down to below 50 μm. On the other hand, glass is difficult to work with and thinning the glass substrate is quite challenging. Nevertheless, glass has its positive attributes; it can be made into panels of 900 mm x 900 mm and these large panels can generate a very high number of glass interposer substrates, almost an order of magnitude higher than Si-interposers can be diced out from a 300 mm Si-wafer, thus reducing the overall price of the glass substrates. And the low lossy behavior of glass is suitable for high frequency applications; especially for passives like inductors. Both materials have their advantages and disadvantages.

Based on research and conference proceedings, it is clear that the industry is going to use embedded passives in the interposers for miniaturization and increase of functionality. It is probably delayed because of yield, test & quality standards, and reliability issues. The processor is a product of high quality standards but if it were connected to an interposer with a passive device in it, then there would be some additional reliability concerns; especially at the connection of the processor and the interposer. The fact that rework of embedded components is not possible, it is crucial that embedded passives have a high yield. But knowing the advantages of embedded passives for system in package (SIP), the industry would soon determine the most cost effective process for 2.5D integration. There is a tremendous R&D activity by major device manufactures, research consortiums and OSAT players on interposers; so most likely, we do not have to wait long before commercial products with IPD in interposers are the mainstream and the missing blanks on the slide presented during the short course of IEDM 2014 would be completed and fully understood.


Comments

There are no comments yet.

You must register or log in to view/post comments.