My typical DACtrip is a blur of non-stop interviews with EDA, IP and Semiconductor vendors followed by a few dozen blogs to share what I’ve learned. I just became aware of something a bit different at DAC this year by talking with Jill Jacobs, an organizer for an event dubbed Heart of Technology (HoT) where they raise money for a worthy, local charitable cause.
Jill Jacobs, Mod Marketing
Continue reading “DAC, IP, Parties and Philanthropy”
SEMICON West is coming up July 14-16th. As always it is in San Francisco at the Moscone Center. Why should you go? Because SEMICON West attracts more than 30,000 professional attendees representing the leading global technology companies, including IDMs, foundries, fabless, contract packaging and test houses, OEMs, materials manufacturers, components and sub-systems companies, and many others. Visitors come to see the latest products and technologies, meet with and learn from technologies and technical experts, and source solutions that enable them to advance their own product development and move their ideas and businesses forward. The exhibits are open every day of the show from 10am to 5pm (4pm on Thursday). There are over 650 exhibitors.
The keynotes at SEMICON West are always a good way to feel the pulse of the industry. This year’s are:
Tuesday July 14th from 9.00am to 9.45am: Scaling the Walls of Sub-14nm Manufacturing. This is a keynote panel session with panelists:
Wednesday July 15th from 9.00am to 9.45am, an (as yet untitled) keynote from Douglas Davis, the SVP of Intel’s IOT group.
As usual, there are two TechXPOTs. Sessions at the TechXPOTs are aimed at engineers and technologists looking for solutions to key technology challenges and looking to better understand cutting-edge and future technology developments. Developed in conjunction with SEMI technical committees, partner organizations, and technologists, the TechXPOT agenda will provide a deeper view of key technology developments.
In the south TechXPOT there are sessions on MEMS, sub-20nm contamination control, 450mm status, using 200nm fabs for IoT, 3D printing and more. In the north TechXPOT there are sessions on test productivity, next generation memories, flexible electronics, packaging for autonomous vehicles (aka self-driving cars), CMP trends. There will probably be other sessions added.
On Tuesday and Wednesday there is the Silicon Innovation Forum (SIF), a two day innovation conference that includes a one day startup/investor forum and a one day research forum.
There are various co-located events too. This is not an exhaustive list.
The imec Technology Forum (ITF) will be held on the afternoon of July 13th in the Marriott across the street. The schedule is not yet finalized but you can save the date. I believe it is free but it is by invitation only.
In parallel in the next ballroom over will be the SEMI/Gartner Market Symposium with a keynote by Ian Ferguson of ARM. This is $370 and up depending on whether you are a member of SEMI and how early you register. It is followed by the SEMI VIP Reception intended for senior-level executives, including C-level management, vice presidents, directors, and managers.
It is LETI day on July 14th, which is also appropriately Independence Day in France where LETI is headquartered. It is 5pm to 8pm in the W Hotel (by invitation only).
And if you are really in save the date mode, SEMICON West 2016 will be July 13th-15th.
If you register by May 8th (err…that would be tomorrow) it is free. So save yourself $50 by going now to the registration page for SEMICON West here.
If you’ve been following DAC general chair Anne Cirkel’s weekly blog, you know the conference program is now final. There’s much to suggest it will be a great DAC, including a record number of submissions in several content categories and a compelling lineup of keynoters. The week will start with an update on Google’s smart contact lens project and end with a MacArthur genius. If you haven’t already registered, you should, and not just to see the luminaries on the main stage. You can register for the conference here.
Fireside Chat with Wally Rhines
Join us for a more informational interaction with Wally Rhines, CEO of Mentor Graphics. Come to the DAC pavilion to be part of an onstage chat where SemiWiki.com Founder Daniel Nenni engages him in a wide ranging conversation spanning his career, the path he sees for the industry, and the changing role of design automation. Please be prepared to ask you own questions.
Monday June 8th @ 4pm
Turns out some of the best and brightest at Mentor will be at DAC this year. They represent a wide cross section of the company, both in terms of seniority (yes, of course, CEO Wally Rhines has a prominent slot) and subject matter (topics range from automotive reliability to automated voltage-aware DRC, trends in functional verification, and tutorials in next-gen lithography).
The DAC site does a great job of giving you multiple ways to access the program, and that should be your first stop for planning your time at Moscone. However if you’re a Mentor-phile and want to see how the most diverse of the Big 3 EDA companies will be represented in San Francisco, scan through the listings below. There will also be several Mentor presenters at the Designer and IP track poster session on Tuesday, and lots more information (and Lego Mixels giveaways!) at Mentor’s booth.
Despite its multibillion dollar size, EDA is a fairly close-knit, friendly industry, one marked by technologists with deep expertise that takes years of formal and informal training to acquire. If you are curious if one of the presenters below might be answering a specific question in a session put it in the comment section and I will be sure to get an answer for you. It’s in everyone’s interest — Mentor’s presenters and DAC’s attendees — to have the seats full at the conference, and if some old-fashioned pre-conference matchmaking can help make that happen, I’m more than happy to help.
Monday, June 8
● John Park, 2.5D/3D Memory & Logic Integration: Tools, Methodologies, Requirement and Infrastructure, tutorial
● Wally Rhines, Fireside Chat, Pavilion panel
● Andres Torres, Understanding the Impact of Next Generation Lithography on Design, tutorial
Tuesday, June 9
● Harry Foster, Trends in Functional Verification: A 2014 Industry Study, SKY talk and tech paper
● Andrew Patterson, The Convergence of Multiple Vehicle Networks: How to Select One Network Over the Other and the Ensuing Challenges, special session
Wednesday, June 10
● Robert Bates, Developing to ISO 26262 Compliance for Component Reuse, special session
● Mathew Hogan, Are You Ready for The Rigors of Automotive Reliability?, tech panel
● Valeriy Sukharev, Interconnect Reliability Modeling and Analysis for Multi-Branch Interconnect Trees, tech paper
● Andres Torres, Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias, tech paper
Thursday, June 11
● Janusz Rajski, Nilanjan Mukherjee, and Elham Moghaddam, Design for Low Test Pattern Counts, tech paper
See you in San Francisco! It would be a pleasure to meet you!
Once again there is a Heart of Technology event at DAC. It is the Love IP Party on Monday evening. Full details at the end of this entry, but first a bit of context. Heart of Technology was started by Jim Hogan who probably doesn’t need much introduction to anyone who has worked in EDA for any length of time.
I met with Jim, along with Randy Smith and Jill Jacobs, to talk about Heart of Technology and why Jim started it. He said it started in 2007 at the depths of the recession when a lot of people were struggling. Jim had previously given money to San Jose State (his alma mater) but decided that maybe prioritizing getting people food was more important. He also realized that a lot of good causes, such as the food banks, were just not well-equipped to put on significant sized events, whereas Jim knew lots of marketing people in the EDA and IP industries who knew the ropes, plus he knew lots of musicians, including himself, to provide the entertainment. It that sense HOT is a sort of “charity accelerator.”
As Jim puts it:At the heart of technology are people with passion for innovation and change. HOT harnesses that power to go beyond code and silicon and fund programs to help raise awareness of charitable causes that add to the betterment of life in local communities.
So the first event was held at South First Billiards in San Jose to raise money for Second Harvest Food Bank. Subsequent events have benefited Court Appointed Special Advocates (CASA) of Travis County TX (DAC was in Austin that year, which is in Travis County), CASA of San Francisco, a luau at Jim’s house that benefited FleaHab Sober Living Environment of Santa Cruz County. Most recently there was a Rock for CASA holiday event held at Ken Potts’ Doc Auto in Santa Cruz, this time to benefit CASA of Santa Cruz Country. In total over $100,000 dollars has been raised to benefit local charities.
HoT is not just a one-man operation. Now many other people are involved to organize and publicize the events, and a whole group of EDA and IP companies sponsor the events.
This years DAC event will be on Monday 8th of June from 7-11.30pm. It will be at Jillian’s, which is in the corner of the Metreon just opposite Moscone West. The party features fabulous food and an open bar with 17 microbrews on tap and specialty cocktails.
Jillian’s also has lots of pool tables, in fact the largest number in San Francisco, so there will also be the first Spyglass Pool Competition. To enter go to the Atrenta booth earlier in the day and pay your $20 entrance fee.
And that is not the only competition. There will also be a costume contenst. Wear your grooviest outfit and show off your Summer of Love style! Prizes to the hippest outfits. So get your hippie vibe on along with your Birkenstocks and join the fun on stage. Special recognition for original clothes of the day.
[TABLE] align=”center” style=”width: 500px”
|-
| 7pm
| Doors Open
|-
| 7-7.45
| The Sonics on stage with cool jazz
|-
| 7.30
| Pool tournament starts, silent auction starts
|-
| 7.45
| Welcome
|-
| 8-8.45
| Groovy Love brings the party on stage
|-
| 8.45-9.05
| Summer of love lookalike and costume contest
|-
| 9.05-9.30
| Heads tales games with the Big Kahuna
|-
| 9.30-10.15
| Groovy Love back on stage
|-
| 10.30
| Announcement of pool competion winners
|-
| 11.30
| Event ends
|-
This year the event will benefit the San Jose State University Guardian Scholars Program which helps kids who are coming out of the foster care program with nothing, and want to attend college (well, specifically SJSU). As they say on their web page:The SJSU Guardian Scholars Program (GSP), part of the Educational Opportunity Program, is committed to helping students exiting the foster care system, wards of the court, under legal guardianship or unaccompanied homeless youth. Our mission is to guide determined and ambitious Guardian Scholars through their academic and personal journeys by providing comprehensive support.
Please join our generous sponsors and distinguished guests at the Love IP Party. Entry is open to all DAC attendees, but a donation of $50 or more to the Guardian Program at San Jose State University will ensure you a spot at the party. Guests who have provided donations are assured entry into the party and will receive a one-of-a-kind event t-shirt.
More details on the SJSU Guardian Scholars Program is here.
The Love IP Party page with full details is here.
Peace, love and IP. Groovy baby.
Why selecting ARM Cortex-M7 processor based Atmel SAMV70/71 for automotive entertainment application? The top three reasons are the Cortex-M7 clock speed (300 Mhz), the integration of a floating point (FPU) DSP and, last but not least because Atmel SAMV70/71 has obtained automotive qualification. If you dig into SAMV70/71 features list, you see that this MCU is declined into several versions integrating Flash: 512 KB, 1024 KB or 2018 KB. And if you compare with the competition, this MCU is the only Cortex-M7 supporting the 2 MB Flash option, being automotive qualified and delivering 1500 CoreMark (thanks to the 300 MHz clock speed when the closest competitor only reach 240 MHz and deliver 1200 CoreMark)…
In fact which makes the SAMV70/71 unique are the FPU DSP performances. Let’s make it clear for the beginning, if you search for pure DSP performance, it will be easy to find standard DSP chip offering much higher performance, like for example Analog Device AD21489 or Blackfin70x series. But the automotive market is not only very demanding, asking for specific qualification, it’s also a very cost sensitive market. A simple calculation shows that, would you select AD21489 DSP, because you have to add external flash and a MCU, the total BOM would be x4 if not x5 compared with the SAMV71 price. Let’s keep this AD21489 as a reference in term in performance, and take a look at DSP benchmark results, coming from third party DSP experts “DSP Concept”.
Before analyzing the results, we need to describe the context:
Some more explanation, this FIR is used to build equalization filter, the higher Taps count the better will be the equalization filter. If we look at the “50 Taps” benchmark results, the SAMV71 (Cortex-M7 based) exhibits 22734 clock cycles (about three times more than the SHARC21489). The Cortex-M4 needs 50% more, which is not surprising, but you have to integrate a Cortex-A15 to get better results, as both Cortex-A8 and Cortex-A9 need respectively 30% and 40% more cycles! And when looking at standard Analog Devices Blackfin DSP, only the 70x series is better by 35%… the 53x being 30% worst.
Now, if you want to build a graphic equalizer, you will have to run Biquad. For example, if you want to build 8 channels and 6 stages graphic equalizer, your DSP will have to run 48 Biquad.
Again the context:
In fact the results are very similar to the FIR benchmark results: only the Cortex-A15 and the SHARC21489 exhibits better performances. The integrated FPU DSP (into the Cortex-M7 core) is using 2x the number of clock cycles when compared with the SHARC21489. If you compare the performance per $, the Cortex-M7 integrated in the SAMV71 is 50% cheaper! Let’s say that using a SHARC DSP certainly makes sense if you want to build high performance home cinema system, but if you target automotive, better to select a FPU DSP integrated together with Flash (512KB to 2MB) and a full featured MCU.
Atmel SAMV71 is specifically dedicated to support automotive infotainment application, offering Dual CAN and Ethernet MAC support and this complete features list:
Don’t forget that when you have built this automotive high end radio you still need room for Ethernet MAC and AVB support… And the SAMV71 only consume 68% of the DSP resource, leaving well enough for AVB and Ethernet MAC.
More information about this DSP benchmark can be found on DSP Concept web here.
From Eric Esteve from IPNEST
Why selecting ARM Cortex-M7 processor based Atmel SAMV70/71 for automotive entertainment application? The top three reasons are the Cortex-M7 clock speed (300 Mhz), the integration of a floating point (FPU) DSP and, last but not least because Atmel SAMV70/71 has obtained automotive qualification. If you dig into SAMV70/71 features list, you see that this MCU is declined into several versions integrating Flash: 512 KB, 1024 KB or 2018 KB. And if you compare with the competition, this MCU is the only Cortex-M7 supporting the 2 MB Flash option, being automotive qualified and delivering 1500 CoreMark (thanks to the 300 MHz clock speed when the closest competitor only reach 240 MHz and deliver 1200 CoreMark)…
In fact which makes the SAMV70/71 unique are the FPU DSP performances. Let’s make it clear for the beginning, if you search for pure DSP performance, it will be easy to find standard DSP chip offering much higher performance, like for example Analog Device AD21489 or Blackfin70x series. But the automotive market is not only very demanding, asking for specific qualification, it’s also a very cost sensitive market. A simple calculation shows that, would you select AD21489 DSP, because you have to add external flash and a MCU, the total BOM would be x4 if not x5 compared with the SAMV71 price. Let’s keep this AD21489 as a reference in term in performance, and take a look at DSP benchmark results, coming from third party DSP experts “DSP Concept”.
Before analyzing the results, we need to describe the context:
Some more explanation, this FIR is used to build equalization filter, the higher Taps count the better will be the equalization filter. If we look at the “50 Taps” benchmark results, the SAMV71 (Cortex-M7 based) exhibits 22734 clock cycles (about three times more than the SHARC21489). The Cortex-M4 needs 50% more, which is not surprising, but you have to integrate a Cortex-A15 to get better results, as both Cortex-A8 and Cortex-A9 need respectively 30% and 40% more cycles! And when looking at standard Analog Devices Blackfin DSP, only the 70x series is better by 35%… the 53x being 30% worst.
Now, if you want to build a graphic equalizer, you will have to run Biquad. For example, if you want to build 8 channels and 6 stages graphic equalizer, your DSP will have to run 48 Biquad.
Again the context:
In fact the results are very similar to the FIR benchmark results: only the Cortex-A15 and the SHARC21489 exhibits better performances. The integrated FPU DSP (into the Cortex-M7 core) is using 2x the number of clock cycles when compared with the SHARC21489. If you compare the performance per $, the Cortex-M7 integrated in the SAMV71 is 50% cheaper! Let’s say that using a SHARC DSP certainly makes sense if you want to build high performance home cinema system, but if you target automotive, better to select a FPU DSP integrated together with Flash (512KB to 2MB) and a full featured MCU.
Atmel SAMV71 is specifically dedicated to support automotive infotainment application, offering Dual CAN and Ethernet MAC support and this complete features list:
Don’t forget that when you have built this automotive high end radio you still need room for Ethernet MAC and AVB support… And the SAMV71 only consume 68% of the DSP resource, leaving well enough for AVB and Ethernet MAC.
More information about this DSP benchmark can be found on DSP Concept web here.
From Eric Esteve from IPNEST
Xilinx users will welcome the brand-new release of Vivado Design Suite 2015.1. For openers, device support for the latest FPGAs in the UltraScale family – XCVU440, XCVU190, and XCVU125 – has been added in the release, and early access code for the XCVU160 is available from a local Xilinx FAE. Installation has been streamlined, removing the need for root or sudo privileges on Linux for the suite, with a new dedicated script for handling cable drivers manually as an option if needed. Borrowable, floating FlexLM license support is improved in this release, and a new standalone hardware microserver (it’s small, less than 1% of the code for the total product) handles remote debug over Ethernet, easing distributed development.
One of the biggest new features in this version is actually … a variant with fewer features, available free of charge. Sometimes, all one needs to do is program and debug a part, like in test or academic environments. Now, a new lightweight edition – Vivado Lab Edition – does just that and nothing else. It comes in a 75% smaller, 1GB download, doesn’t require license keys or activation, and supports all the same Xilinx devices of the full suite.
For development users who crave the full-price Vivado Design Suite and the latest feature enhancements, this release has those as well. The need for speed has been addressed, with improved simulation script algorithms that speed up compile time by 2 to 2.5x. This and other improvements yield 20 percent faster simulations than previous Vivado releases, and an order of magnitude improvement in simulator disk footprint. Using the Vivado TCL store infrastructure, this version integrates with Aldec Riviera-PRO for more advanced simulation, as well as with simulation flows from Cadence, Mentor, and Synopsys.
With the extensive changes in the UltraScale clocking structure and far more clock regions in the part, the likelihood of clock domain crossings (CDCs) in a large FPGA design continues to increase. CDC detection in this Vivado release now spots 16 typical topologies, with summaries by clock pair or by rule type with cross probing to schematic and RTL.
There are also new enhancements for Zynq-7000 All Programmable SoC developers, with additions to analyze performance of the processor subsystem (PS) and the bandwidth used between the PS, the programmable logic (PL), and external memories. System model designs with AXI traffic generators are also provided for the ZC702 and ZC706 evaluation boards.
The partial reconfiguration feature introduced previously has been further expanded, including UltraScale support. There are numerous improvements in IP and its integration, and changes specific to IP leveraging UltraScale features. Among new IP in the release is a block for UHD-SDI video in several SMPTE formats.
Noteworthy is for the full-featured Vivado Design Suite 2015.1, 32-bit operating system support has been removed. This allows performance optimization for design entry and implementation to move forward. Vivado Lab Edition 2015.1 is still supported on older development hosts such as Windows 7 and Red Hat Enterprise Linux 6.
Vivado users should head for http://www.xilinx.com/download to get their new version, including the hardware microserver, documentation navigator, and license management tools. A short video highlighting many of these changes is also available at
Since Aart de Geus, co-CEO and co-founder of Synopsys, gave his keynote at the Synopsys User Group (SNUG) conference in Silicon Valley last March, I’ve been hearing a lot more about the “Shift Left” in semiconductor design. Although I couldn’t attend Synopsys’ 25[SUP]th[/SUP]SNUG, I found some short videos on the Synopsys website in the News Room that summarized key ideas that were discussed there, including this “Shift Left.”
At the SNUG Designer Community Expo, Synopsys’ Phil Dworsky, Director of Strategic Alliances, interviewed Aart de Geus and Andreas Kuehlmann, GM and Sr. VP of Synopsys’ Software Integrity Group. Here are my key takeaways from these videos –
When Aarttalked about SoC design and verification shifting left in his keynote address, he meant something big. It wasn’t simply doing more things faster to accommodate larger SoCs in the same schedule; of course that task itself is not so simple with today’s SoCs containing several functionalities, multiple heterogeneous IP blocks, gate counts running into billions, and a huge heap of software sitting on top of it. Synopsys has already taken a leap in providing SoC design acceleration and productivity through its powerful platforms for designing and verifying SoCs, and developing and re-using IP. Recently, Synopsys introduced IP accelerator kits that enable IPs to be quickly developed and verified in larger designs. Aart says IP is a never ending investment area for Synopsys. That being said about what is already happening; the big question now is how to gain 100 times more productivity from here. That’s where the software comes into the picture. Today, designs are driven by software; there are more software engineers than hardware engineers in semiconductor companies. In Aart’s words, “most of the chips are supercomputers already.” So, the focus is software; that has to be disciplined, strengthened and made robust. It’s software that will take us to larger contexts of designs. Of course, the software development has to be augmented with what we’ve learned from hardware design.
It’s something being pursued on a major scale at Synopsys. Synopsys has even modified its logo. If you haven’t noticed it already, read the line “Silicon to Software” below the logo itself. Aart’s keynote includes more details on the strategy behind this change. It will be interesting to follow how Synopsys executes on this new theme.
In the other video on the News Room page titled, “Silicon to Software,” Andreas Kuehlmann talks about what EDA has done for the electronics hardware industry over the last 30 years and how that relates to what Coverity(now part of Synopsys) has been doing for the last 10 years in the software domain. Comparatively, hardware design is much more rigorous; there is sign-off at every stage whereas there is no sign-off of software. Patches are implemented when any problem arises. Enabling developers to find bugs with respect to security and quality early in the development cycle will enable a “Shift Left” in software, as well. But this is a practice that has yet to be adopted into the culture of most software organizations. It has to be a daily routine for software developers and Coverity tools can significantly help there.
Today, IC design includes static and dynamic sign-off tools. Software needs similar solutions to help developers make sure that their applications are secure and provide the intended value to customers. With Coverity’s methodology, developers can make software quality measurable and enforceable through a quality matrix.
See the actual videos “Design Flows: Shifting Left”and“Silicon to Software”here on the Synopsys New Room website. Choose the title from the list of videos at the bottom of the page and click on the video icon; it’s readily viewable without requiring registration.
Also view Aart’s full keynote, “Silicon to Software: Shift Left!”
Lessons learned from hardware design must be applied to software development. That’s how software integrity will be realized. I expect we’ll be hearing a lot more about this at future SNUGs.
Pawan Kumar Fangaria
Founder & President at www.fangarias.com
Sourcing MIPI CSI-2 or DSI IP to a respected IP vendor is mandatory to build a peripheral IC or a SoC targeting mobile application as the chip maker simply can’t afford to do a re-spin because of Time-To-Market imperative. Buying this IP to a vendor also offering MIPI powered FPGA Prototyping Platforms is even better! Northwest Logic was one the first IP vendors to develop controller for MIPI camera (CSI-2) and display (DSI) specifications and they know that their customer very first need is for silicon proven solution and right after to benefit for a FPGA Prototyping Platforms integrating MIPI D-PHY and CSI-2 (or DSI) controller. That’s why S2C and Northwest Logic have built such a partnership. The cores are now a part of S2C’s expansive library of Prodigy Prototype Ready™ Interfaces, see picture:
A fully defined MIPI D-PHY interface requires one clock lane and four data lanes using in the above board Meticom MC20901 as a Rx D-PHY chip and Meticom MC20902 as a Tx D-PHY chip. Let’s take a short look at these Meticom FPGA to D–PHY bridge ICs allowing for example connecting MIPI (CSI-2) powered camera controller to MIPI (DSI) powered display controller through any FPGA only supporting LVDS or CMOS I/O, but not MIPI D-PHY:
S2C’s MIPI D-PHY Prototyping Kit includes one S2C MIPI D-PHY Interface Module, one OV2710 Camera Module, and one 70WW2A WVGA Display. The MIPI Module supports the fully defined MIPI Rx Interface and MIPI Tx Interface through an MMCX connector. MIPI D-PHY Interface Module occupies one Logic Module connector and can be used on S2Cs Prodigy Virtex-7 Series Logic Modules.
The MIPI D-PHY Interface Module features:
As you can see on the above graphic extracted from the “MIPI Ecosystem 2015” survey from IPnest and simplified to only show the most used interfaces in mobile phone and tablet, for multimedia (Camera, Display, Soundwire, SLIMBus), storage (UFS, UniPro and M-PHY) and RF (RFFE, DigRF and M-PHY) the winners are…
… Camera (CSI-2, CSI-3) and Display (DSI and DSI-2).
If you want to figure out which of the camera and display specification release are the most used, just look at the difference between D-PHY and M-PHY adoption rate, keeping in mind that M-PHY should also be used with UFS and DigRF on top of CSI-3 and DSI-2. Clearly D-PHY is the most used of the MIPI PHY specification and by consequence the winners are DSI and CSI-2.
Accelerating TTM is crucial in such a fast-moving market like mobile. The chip maker will use an already proven solution (Northwest Logic has used the S2C’s MIPI D-PHY Prototyping Kit to validate their own IP design) and will be able to jump-start his own FPGA Prototyping Platforms by using S2C’s prototyping kit.
You better understand why when Northwest Logic and S2C have developed a demo to showcase the effectiveness of the integrated solutions (above), this demo was based on CSI-2 and DSI. Simply the most used MIPI specifications! The video captures video data through a camera using a CSI-2 interface, stores the data into DDR3 memory, and then transfers the data via a DSI channel and display. The demo utilizes Northwest Logic’s MIPI CSI-2 camera controller, DSI display controller and DDR3 controller IP cores. The demo features support for multi-lane MIPI CSI-2 and DSI operations and pause capability.
This demo will be featured at this year’s Design Automation Conference, June 8-10, in the S2C booth #3108.
Link for S2C’s MIPI D-PHY Prototyping Kit
Availability
S2C’s MIPI D-PHY Prototyping Kit is available now.
From Eric Esteve from IPNEST
Because it is such a major impact on the semiconductor industry, being the largest and fastest growing market ever, I follow the ups and down of the mobile industry. So what happened in Q1?
Total shipments are up 2% to a record (for Q1) 440 million units but that is down 16% from Q4 which remains the biggest quarter ever.
First thing is that Samsung is back at #1 which I predicted last time I wrote about mobile. This is not due to the new Galaxy models (S6 and S6 Edge) which were only announced in the quarter and were not actually available until April. Samsung is up 11% sequentially and analysts put them around 83 million units. With the new Galaxies reportedly selling well I expect Samsung to pull ahead of Apple even more next quarter.
See also Mobile 2014 and the Future
Apple is far and away the most profitable company, of course, but their unit sales were down 11% sequentially (although up nearly 40% on a year ago). They reported 61 million units, so 25% behind Samsung. It is quite a change of fortune given that they were bigger than Samsung (or a dead heat according to some analysts) in Q4. But Apple always has a huge quarter when they release their new models. iPad sales were down a lot, presumably partially due to being cannibalized by the phablet iPhone 6 plus, although iPad is still the #1 tablet by a long way (it is very fragmented). And it took them one day to become a clear #1 in watches too although the jury is still out on just how significant a market that will turn out to be. I remain a little skeptical although my friends who have one (I don’t) rave about them.
Here is an interesting factoid: during Q1 NASDAQ was up 0.7%. But without Apple, it was down 5.1%. Apple is propping up the whole index. Indeed the S&P would have lost an extra percentage over what it did without Apple.
Lenovo (now with added Motorola) third with sales, according to Strategy Analytics, of 19 million, and Huawei fourth with 17M. Plus LG (who are Korean of course) who reported sales of about 15 million phones. In fact some analysts put LG at 4[SUP]th[/SUP], ahead of Huawei. The rest of the top ten are Xiaomi, Coolpad, ZTE, TCL and maybe Vivo. All Chinese brands. In fact below the top 3 (Sammy, Apple, Lenovo) the numbers are clearly hard to predict with everyone not far from being equal and different analysts coming to different conclusions.
Notable for their “new normal” absence were Microsoft/Nokia, Blackberry, and (newly fallen from grace) Sony. How the mighty brand names of just a few years ago have fallen.
Nokia Networks (the old Nokia, now a networking and mapping company, not Microsoft which bought Nokia’s old smartphone business and the name, although they don’t use it) livened things up a little last week when they announced in China that they would get back into the smartphone business. And then they denied it and said it:reiterates [Nokia Networks] currently has no plans to manufacture or sell consumer handsets.
Given that they probably still have excellent carrier relationships, especially given their acquisition of Alcatel-Lucent making them the biggest supplier of the base-stations, the big question may be “why not?”
