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This is how FPGA Prototyping Works

This is how FPGA Prototyping Works
by Majeed Ahmad on 07-02-2015 at 1:00 pm
Categories: EDA, S2C EDA

FPGA prototyping has come a long way since the late 1980s when chipmakers began using FPGA devices for building system prototypes of ASIC designs. The utility of a working FPGA prototype allows hardware designers to develop and test their systems, and it provides software developers early access to a fully functioning hardware platform.

A lot has changed since the late 1980s when FPGAs emerged on the semiconductor realm. Chip developers are now dealing with mega-million gate counts for the larger ASIC/SoC designs, and here, design partitioning, debug and scalability requirements are turning the FPGA-based prototyping technology into an even more viable design tool.


A prototype is used to develop both hardware and software iteratively

S2C Inc.’s e-book titled “Getting the Most Out of FPGA Prototyping” can serve as a handbook on how this design methodology works. Moreover, it debunks the myths surrounding the issues regarding how FPGA prototyping works and what value it brings to ASIC/SoC designers. S2C has cobbled the e-book on FPGA prototyping systems using a series of articles published in EE Times.

The series of articles can help chip designers navigate the world of FPGA prototyping technology—everything from overcoming FPGA prototyping hurdles to expanding the use of FPGA prototype design flow to even the larger designs.

Furthermore, the e-book from S2C looks into the specifics of how FPGA-based prototyping can accelerate design and verification process. And by doing that it offers an insight into how a complete prototyping platform can be helpful at any design stage and for any design size.

FPGA Prototyping: Challenges and Solutions

The book kicks off with an outline of five key challenges to FPGA prototyping and provides a detailed treatment of issues such as partitioning, debug and reusability. Next, it delves into ways for addressing these challenges and details the criteria for selecting FPGA-based prototyping systems.

The e-book also clears the air about this myth that FPGA prototyping is only suited to small designs; it forcefully makes the case for the use of FPGA prototyping in large SoC designs. Here, the book refers to the recent advancements in partitioning, debug, and scalability that have made FPGA-based prototyping a far more suitable solution for the large ASIC/SoC designs.

The book also shows how extending the functionality of FPGA prototyping through the use of a transactor interface can open up tremendous possibilities to designers. Next up, Getting the Most Out of FPGA Prototyping resorts to transactor as a use case of an interface between a software program and AXI-compliant hardware.


Transactors make early software development a reality

Finally, about the SoC designs, which are growing both in size and complexity, it’s worth noting that software development and hardware verification are the two leading factors in SoC design cost. Here, at this SoC premise, the book shows how today’s off-the-shelf FPGA prototyping systems can offer value in every stage of the SoC design flow. And it claims that FPGA-based prototyping technology is ready to cater to the next-generation SoC designs through extensible and scalable systems that offer a variety of both hardware and software interfaces.

The ebook Getting the Most Out of FPGA Prototyping is short, sweet and well worth an ASIC/SoC designers’ time.

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SmartDV at DAC and More

SmartDV at DAC and More
by Pawan Fangaria on 07-02-2015 at 7:00 am
Categories: IP, SmartDV

As we are aware about SmartDV Technologies, a fast emerging company in IP space with offices in Bangalore and San Diego, its booth in 52ndDACwas located at a prominent position in front of DAC Pavilion on the exhibits floor. So, most of the crowd coming to attend sessions in DAC Pavilion had a glimpse of SmartDV. I met Deepak Kumar Tala, Founder & CEO and Harish Poojary, VP of worldwide sales and business development at SmartDV.

On Sunday night, the day before start of the conference, I attended Gary Smith’s presentation about the future of EDA and IP where he predicted the IP business to be almost flat until 2019. Gary sees Designware IP to become commodity and platform-based IP (a model that ARMfollows) to remain premium. Also, in Gary’s list of what to see at 52[SUP]nd[/SUP]DAC, SmartDV was mentioned at the top of his list where he recognized the intelligent testbench technology for VIPs from SmartDV. The link to Gary’s list is provided at the end of this page.

SmartDV has a wide range of IP products including MIPI, Networking and SoC, Automotive and Serial Bus, and Storage VIPs, and also Memory models and Design IPs. And they have customers across the world for these IPs. So, I talked to Deepak and Harish about how they see the current IP business and the expected growth in future. Here is the conversation–

Q: SmartDV has a large VIP portfolio and you have a good customer base. How do you see the current IP business and future growth potential from your perspective?

A: From SmartDV business perspective, we have a large growth potential at key accounts. There is lot of work to be done to develop our major accounts and also acquire new customers. We are excited about the growth opportunity ahead of us. However, if you are asking about usual VIP business, we see simulation VIPs becoming more of commodity products whereas there is a premium uptapped market out there for simulation acceleration IPs.

Q: Your VIPs are easily customizable in customer’s environment and they run order of magnitude faster, so that’s like providing a customized VIP to a customer. How do you see profit margin playing out in that space?

A: We are able to maintain high profit margins while offering low cost VIPs to customers. Our Cost of Goods Sold (COGS) is way lower than competitors. We keep operational cost as low as possible by removing redundancies and also by increasing efficiency through automation. All our engineering is based in India and our support is remote. Also, there is lot of automation from engineering side due to compiler technology.

Q: Your own language and compiler technology must be providing you a good edge for differentiating your VIPs from the rest in the market?

A: Yes, our compiler is the key reason why our time to market is very short. Also, it helps maintain high quality and standard architecture across all VIPs. It is because of the compiler we are able to ship compliance test suites with all VIPs along with detailed documentation without high engineering cost.

Q: Recently you released six new VIPs – USB-Power Delivery, MIPI-CPHY, MIPI-DBI, AMBA5 CHI, LPDDR4 and DDR4. How are they performing in the market?

A: We have customers for all except AMBA5 CHI. We are very happy with the quality of top tier customers engaged for these VIPs. In addition to existing customers, we are currently engaged with several other propsects for evaluating these VIPs.

Q: I see networking, automotive, and storage gaining most traction in the near future. Where would be your focus in the next 3-5 years? Which area you see as most growing?

A: Our focus is to be the leader in simulation and acceleration VIP market including memory models. We see the major growth for SmartDV to come from acceleration IPs.

Q: How about Design IP? Which area you are pursuing?

A: Our strategy is not focussed on Design IPs. Instead, we are focussed on delivering complete portfolio in simulaiton and acceleration VIP market.

Q: How about a model for a complete solution in a particular area? For example, networking where you provide IPs for design, verification, interface, and other required hardware and software?

A: This is not something we have currently planned to accomplish. However, depending on market situation, we may consider such a solution in the future.

Q: What are your upcoming products this year? Is there any new release in immediate horizon?

A: There is lot of push from customers to develop comprehensive solution for memory models and platform independent acceleration IPs. This is our focus area for next 12 months while maintaining leadership in simulation VIP market.

Q: Would you like to talk about your customer(s)? What do they like most about SmartDV?

A: We can’t mention our customer names. We can proudly say most of the semiconductor companies are our customers. Some of the top companies use 10+ VIPs from us. They like our flexibility with technical customization, support model, pricing and quality of the products. Engineers love the fact that every VIP comes with a compliance test suite which gives them a jump start.

This was a great conversation with Deepakand Harish. I can see SmartDV’s strategy panning out quite well. Their innovative language and compiler technology is paying good dividends to keep them differentiated from others in the VIP space.

Gary’s list of what to see is HERE.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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Global Foundries Completes IBM Semiconductor Acquisition

Global Foundries Completes IBM Semiconductor Acquisition
by Paul McLellan on 07-01-2015 at 4:40 pm
Categories: Foundries, GlobalFoundries

Today the deal for GlobalFoundries to acquire IBM’s semiconductor division closed, having had regulatory clearance from Committee on Foreign Investment in the United States a couple of days ago. GlobalFoundries is, of course, owned by Mubadala which is owned by the government of the Abu Dhabi, and I have heard that there were some issues with foreign ownership since IBM supplies the US military.

The merged company has five main manufacturing sites with a total capacity of around 7M 200mm equivalent wafers per year (mostly 300mm wafers in fact):

  • East Fishkill NY (previously IBM) running 90nm down to 22nm, with a capacity of 14,000 300mm wafers per month
  • Malta NY (GF’s fab 8) running 28nm down to 14nm and will go lower with 60,000 300mm wafers per month
  • Burlington VT (previously IBM) running 350nm down to 90nm with a capacity of 40,000 200mm wafers per month
  • Dresden Germany (GF, the old AMD fab) running 45nm down to 28nm with a capacity of 60,000 300mm wafers per month
  • Singapore (GF, previously Chartered) running 180nm down to 40nm with a capacity of 68,000 300mm wafers and 93,000 200mm wafers per month

The company is now structured into 3 business units:

  • CMOS platforms BU, with a broad technology portfolio across leading-edge and mainstream nodes (I think this is mostly GF’s existing business)
  • RF BU, accelreating RF leadership and manufacturing with technologies such as RFSOI, RFCMOS and SiGe (I think this is the IBM RF business)
  • ASIC BU, with the richest portfolio in the foundry industry of IP for wired, wireless infrastructure applications (I think this is the old IBM ASIC business)

To quote directly from the press release:In RF, GLOBALFOUNDRIES now has technology leadership in wireless front-end module solutions. IBM has developed world-class capabilities in both RF silicon-on-insulator (RFSOI) and high-performance silicon-germanium (SiGe) technologies, which are highly complementary to GLOBALFOUNDRIES’ existing mainstream technology offerings. The company will continue to invest to deliver the next generation of its RFSOI roadmap and looks to capture opportunities in the automotive and home markets.

In ASICs, GLOBALFOUNDRIES now has technology leadership in wired communications. This enables the company to provide the design capabilities and IP necessary to develop these high-performance customized products and solutions. With increased investments, the company plans to develop additional ASIC solutions in areas of storage, printers and networking. The most recent ASIC family, announced in January and built on GLOBALFOUNDRIES’ 14nm-LPP technology, has been well accepted in the marketplace with several design wins.

I had a phone call this afternoon with Mike Cadigan. He was formerly (well, until yesterday I guess) General Manager of IBM Microelectronics Division, and is now head of the Product Management Group at GlobalFoundries.

Mike said that as part of IBM their semiconductor offering had been reined in by the reluctance to invest in both product solutions (R&D) and capacity (basically capital for manufacturing). With the acquisition those technologies should be more widely available to the merchant market.

The company now has 16,000 patents and has a rich portfolio of technology not just in silicon but also in packaging, materials, manufacturing knowledge and more.

Processes will now be developed with early research done in Albany and then moved into the Malta fab 8. I asked Mike about next generation process (10nm) since IBM has historically done a lot of work on SoI. He said that SoI will continue to be important, especially for RF where IBM has historically been strong, down to 14nm. But moving forward they will have a high-performance bulk solution that the combined IBM/GF team will develop. Remember that GF licensed 14nm from Samsung. All 3 companies historically were part of the Common Platform which gradually seems to have faded away, but it is not inconceivable that there will still be 10nm collaboration.

Another aspect of the deal is that GlobalFoundries will be a partner with IBM (the non-semiconductor part) for ten years to provide the most advanced semiconductor solutions including access to the $3B in advanced semiconductor research that IBM is continuing to do. I asked about the design automation tools. Those seem to be remaining in IBM although there is an intention that anything needed will be shared.

The press release is here. A presentation on GlobalFoundries post acquisition is here (pdf).

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A Systems Company Update from #52DAC

A Systems Company Update from #52DAC
by Daniel Payne on 07-01-2015 at 12:00 pm
Categories: Dassault Systemes, EDA

On Sunday night at DAC we heard from Gary Smith that traditional EDA companies need to grow into new market segments in order to stay relevant, and that a systems-level approach to multi-disciplinary engineering was called for. I almost jumped out of my seat and said, “Hey, what about Dassault? They are already doing that now.” Hopefully Gary is reading this blog, and will update his slides for DAC 2016 in Austin and at least mention the several systems-oriented companies that intersect with EDA.

To better understand what is happening at DassaultI met with Michael Munsey in the Press Room, where it was much quieter than the exhibit floor and we could talk without interruptions.

Q&A

Q: What is a trend that you see at DAC this year?

Well, one big thing at DAC is the discussion on requirements-driven verification (RDV) strategy. Design companies are understanding that you must tie requirements to EDA tool results.

Semiconductor companies have requirements that are unfortunately spread out in over a dozen different places, but in a functional verification flow a bug could be in your plan, the design or the testbench. RDV tracks the entire path from requirements to verification results. Anything that produces a report can be linked back to requirements.

Related – Design Collaboration, Requirements and IP Management at #52DAC

Q: I remember hearing about a requirements tool called DOORS back in the 1990s. What’s new in this space?

Rational Software created a requirements management tool called DOORS, now owned by IBM. Reqtify is the Dassault tool for requirement traceability and impact analysis, but it links with all the other requirements tools and imports them into our system to create the traceability. If someone changes requirements, it tells the designers what the effect is, new requirements are in place, your old results are valid.

A graphical representation of requirements, test benches, design files and results are available with Reqtify. That tool answers questions like what has changed, what is out of date. If a requirement changes, we know all about.

The ad-hoc approach to requirements is now replaced with this structured flow.

Q: How does this requirements traceability process work with EDA tools?

All the outputs of EDA tools are now stored away and cataloged, and you have a dashboard across the flow, so that you can now look at historical trends and ask an important question – are we getting better?

  • functional coverage
  • timing closure
  • DFT coverage
  • etc.


The dashboard is configurable by the user and new tools can be added for tracking.

Related – Managing Semiconductor IP

Q: Who would be using a requirements tool on a design team?

It could be any engineer, but mostly we see that it is a verification engineer.

Q: What is management concerned about on large system projects?

Management likes to work with project plans – using the notion of invisible governance, where you can actually track EDA tool data against your milestones so that status is auto-updated once you install the infrastructure. End-users can focus on each of their specialized design tasks, while reporting is automated for them.

We do find that there is a bit of a big-brother aspect, because your design tasks are being tracked and reported.

Engineering data can come from design engineers, product engineers, even manufacturing – because all can be included in the system.

Q: What is a decision support system and why is it useful?

A decision support system answers the primary questions of:

  • Where am I in this process, are we really done designing yet?
  • How well are we tracking against plan, with these engineering resources?
  • Which design team is most effective in their projects?


With a decision support system I will know which resources will help me get to my goals. The more that you use the system, the better the prediction results are.

Related – Filling the Gap between Design Planning & Implementation

Q: How does this all work with other EDA vendor tools?

All of the big three EDA companies work well with Dassault, because each of their point tools work well within the Dassault environment.

Also Read

Design Collaboration, Requirements and IP Management at #52DAC

Managing Semiconductor IP

Filling the Gap between Design Planning & Implementation

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Synopsys Aquires Security IP Company Elliptic

Synopsys Aquires Security IP Company Elliptic
by Paul McLellan on 07-01-2015 at 7:00 am
Categories: IP, Synopsys

On Monday Synopsys announced that it was acquiring Elliptic Technologies. They have one of the largest portfolios of security IP consisting of both semiconductor IP blocks and software. Increasingly, security requires a multi-layer approach involving both secure blocks on the chip and a software stack on top of that.

Elliptic’s products are used in areas that you might expect such as for payment processing and for digital rights management (DRM). But it is also closer to the silicon than most security solutions including protecting against rogue semiconductor devices, IP theft and more. In each of these situations, cryptographic credentials such as keys or certificates must be managed and inserted into the target device to authenticate it. For example, if a manufacturer wishes to protect against anti-cloning when using a ODM, or overbuilding at a foundry, it can securely inject credentials from a secure server administered by the manufacturer. Only those products that receive these credentials will function correctly. Similarly, a designer of DSP algorithms for example could decrypt and enable the code only for authenticated use through the secure injection of credentials during manufacturing by customers. This will ensure that only authorized and paid-for copies are enabled.

Security IP is a significant growth area due to two factors. Firstly, the importance of security increases on a daily basis, and the risk of poor solutions can be measured in hundreds of millions of dollars for large companies. Secondly, the growth of connected consumer electronics such as smartphones and tablets, networking infrastructure, gateways, base stations, femtocells, and mobile applications. And, of course, an obligatory mention of IoT where security is up there alongside power as an issue.

Or, as Joachim Kunkel put it in the press release:We live in an internet-connected world and built-in security is critical in protecting devices from malware, data breaches and more.

One key capability is the Ellipsys Trust Framework that enables:

  • Manufacturers to protect against counterfeiting, cloning, overbuilding of products produced by ODMs and contract manufacturers;
  • IP designers to protect IP in the form of firmware-embedded algorithms, programs, and FPGA bit files, through all phases of product life cycle;
  • Content Distributors to protect high value content such as High Definition video;
  • Device manufacturers to activate and provision products at the point of sale;
  • Network operators and administrators to manage the identity of devices and subscribers, and to enable features, applications and services in mobile and wired networks

The portfolio includes:

  • Symmetric Cryptographic Engines
  • Hashes and MACs
  • Public Key Accelerators
  • Random Number Generators
  • Software Libraries
  • Security Protocol Processors
  • tRoot Embedded Security Modules
  • Security Accelerators
  • tVault DRM
  • DTCP-IP content protection
  • HDCP 2.2 content protection

This acquisition follows Synopsys’ recently announced acquisition of Codenomicon and announced plans to acquire Quotium’s Seeker product, also providing some of the necessary technology for developing secure products. Between pure software solutions which are grouped with Coverity, and semiconductor IP grouped into DesignWare, Synopsys has an increasingly broad portfolio of security products. Just as importantly, they have an increasingly large team of experts in software and silicon security implementation.

Terms of the acquisition were not announced, but it is not financially material to Synopsys (which means the price was not enormous). If you are curious about Elliptic’s name, I think it comes from two things (I’m guessing): getting IP into the name, and one of the major modern encryption techniques is elliptic curve cryptography (ECC), so to anyone in security the word elliptic doesn’t bring ovals to mind, but ECC which gets higher levels of security from the same key length as older approaches.

The Synopsys security IP page is here.

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eSilicon ♥ ARM!

eSilicon ♥ ARM!
by Daniel Nenni on 07-01-2015 at 5:00 am
Categories: EDA, eSilicon

The things I enjoy the most at conferences are presentations by customers, the companies that solve the problems we face every day with modern semiconductor design. We all have access to the same tools and IP and use the same foundries so it’s the actual design and implementation that separates the wheat from the chaff, absolutely.

SemiWiki has direct access to dozens of customer presentations from #52DAC and will be writing about them over the summer. These types of blogs are the most viewed and the bigger the customer the more views. Or you can just mention ARM and the views go exponential because let’s face it, ARM IP is in just about every design, mobile or not.

The nice thing about eSilicon is that they are both a vendor and a customer so they have no problem talking about what they are doing and rightly so since they have taped-out hundreds of designs and shipped MILLIONS of chips so who better to listen to, especially when they talk about using ARM IP. This presentation was titled “ARM Based Designs in the Internet Age”and was well worth listening to.

eSilicon starts by using an IP hardening project to ensure the flow works well. They don’t push performance here but once eSilicon engages with a customer design on a validated flow they use design virtualization to get the best possible results (performance, power, price). The example used in this presentation is a baseband processor implemented in TSMC 28nm HPL. One of the first questions you will face when you start a design is: Which of the TSMC 28nm processes will be best for my design?

TSMC now has seven versions of 28nm: HP (high performance), HPM (high performance mobile), HPC (high performance computing), HPL (high performance low power), LP (low power), the recently added HPC+, which is an even faster version of HP, and ULP, which is ultra-low power for IoT and other battery powered applications. So many choices so little time, right?

The complete presentation can be found HERE.

Take a look at slide#3 to better understand Design Virtualization. What they are talking about here is a big data analytics system that contains a characterization of all the IP used across all the process options available. Using this technology, eSilicon can help users pick the right combination of IP, process options, operating conditions, Vt mix, etc… in real time by querying a data base. This essentially “virtualizes” all these choices. Users are typically stuck with their first decision on all these items because trying something new is a multi-week experiment and no one has that kind of time. Thanks to this virtualization layer, users can now try new choices and get quick feedback on the results. eSilicon can also provide an optimal set of choices for a given power, performance, or area target. They use design virtualization internally on all customer designs to make sure they deliver the best chip possible.

Slide #5 shows where design virtualization is used early in the flow to drive the best selections and then later in the flow to continue to optimize things like memory configurations. As the implementation gets closer to tapeout more is learned about the design and therefore more optimization is possible.

Slide #9 introduces a way for all design groups (not just eSilicon customers) to access design virtualization. It is delivered as a service. The customer provides a block that needs to be optimized and then eSilicon experts analyze and provide guidance on what to tweak to make it better. If they can’t achieve the required improvement there is no charge for the service. eSilicon was founded on a success based business model and this type of design virtualization service is yet another example.

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Why Did Intel Pay $15B For Altera?

Why Did Intel Pay $15B For Altera?
by Paul McLellan on 06-30-2015 at 12:00 pm
Categories: Foundries, FPGA, Intel Foundry, TSMC, Xilinx

While I was at the imec Technology Forum someone asked me “Why did Intel pay $15B for Altera?” (the actual reported number is $16.7B).

The received wisdom is that Intel decided that it needs FPGA technology to remain competitive in the datacenter. There is a belief among some people that without FPGA acceleration available for vision processing, search and other algorithms that map better onto a hardware fabric than a processor, then Intel will gradually have more and more competitors in the datacenter. Even if you only put that possibility at 50-50 (say) then the “only the paranoid survive” attitude is to get an FPGA acceleration solution anyway. Of course they don’t need to buy Altera to do that. I’m sure Altera (or Xilinx even) would be happy to sell them all the chips they need. But at some point that technology may need to be embedded in which case having it on the same process already counts for something.

The next question was “Couldn’t they just build an FPGA solution themselves? It wouldn’t cost $15B.” At the technical level I am sure that the answer is that they could do it. Intel has great engineers and if they put their mind to it I’m sure they could produce something.

But I see 3 problems with doing it in-house.

[LIST=1]

  • Time. Intel might be able to design a suitable fabric but how many years would it take them to get it up to a competitive standard. Altera and Xilinx have spent decades doing it. Intel would be trying to catch them from a standing start.
  • Patents. It is basically impossible to design an FPGA without violating Altera and Xilinx’s patents. Those two companies have a cold war of mutually assured destruction. But anyone else would get problems if and when they got commercial traction. Intel would probably get problems even earlier. If (say) Xilinx felt Intel was violating their patents blatantly they may launch. Against an FGPA startup, the most they could win would be their entire cash balance which probably wouldn’t cover the legal fees.
  • Software. FPGA is as much about software as hardware. I once did due-diligence for a VC on a hardware fabric (arrays of tiny CPUs) and told the VC to run away fast because the company didn’t even realize they were basically in a software business, where they had no expertise. They, and Intel, could probably build the hardware fabric. But could they build and mature a software tool chain allowing them to take C and other software languages and move them into the fabric seamlessly? That takes years too.

    Besides, Intel has already tried to grow their own FPGAs from seed with Tabula and Achronix, in both of which they were major investors and provided foundry services. Tabula closed its doors. Achronix’s are still open but rumors are not enthusiastic.

    So if Intel wants a mature FPGA fabric with a working tool chain that allows compilation of offload software into hardware, they pretty much have to buy Altera or Xilinx. I don’t think Lattice have powerful enough software or large enough arrays, it’s not what they do. Xilinx are deep partners with TSMC, 10nm just announced. Altera are partners with…Intel (and TSMC too, to be fair). So easy decision which girl to chase at the dance.

    The next question. “So why would Intel want to run a merchant FPGA business?” I have to say that I agree with the question. If I put myself in Intel’s shoes I wouldn’t want to. Mostly they are shipping TSMC silicon and have no opportunity to move it into an Intel fab. The Intel/Altera 14nm arrays are not even sampling (or even taped out, I hear). For anti-trust reasons they may have had to promise to keep the business going as a condition of the deal closing, but otherwise the first thing I would do is shut it down, or at least not invest in it for the future. It doesn’t need enough wafers to “fill the fab”. And it doesn’t move the needle in revenue either (Altera is a little less than $2B, all TSMC silicon, and Intel is $60B or so). So Altera’s merchant business is a pure distraction from Intel’s business in the datacenter and notebooks.

    Who benefits? Everyone else. The Altera 14nm FPGAs have ARM processors on them. Who in their right mind is going to kick off an ARM-based project on Altera FPGAs now? Xilinx would seem a much safer choice. They are not about to exit the merchant FPGA business, nor switch ARM out for Atom, nor fail to get timely access to ARM’s latest and greatest next-generation cores, or whatever your nightmare of choice is.

    With regards to the acceleration in the datacenter question, there are two outcomes. One, it turns out to be really important, which bodes really well for Intel/Altera but also for the ARM/Xilinx ecosystem, which will be basically everyone else other than Intel, including some powerful players such as Qualcomm. Or, two, it isn’t a major factor. ARM’s partners can still compete on the basis of power, price and physical size and may get some traction. And Intel wasted $15B.

    Also Read: Xilinx in an ARM-fueled post-Altera world

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    Analog/Mixed-Signal Data Management with Custom Designer

    Analog/Mixed-Signal Data Management with Custom Designer
    by Majeed Ahmad on 06-30-2015 at 7:00 am
    Categories: Cliosoft, IP

    In recent years, a number of technologies as well as the constant desire for faster and more pervasive mobile communication systems have set in motion a well sustained growth trend for the “next big thing” such as the Internet of Things (IoT), wearables, automobile electronics, advances in medical devices etc. In all these areas of growth, analog and mixed-signal (AMS) designs play a very crucial role.

    With the increased use of analog designs in today’s system-on-chips (SoCs), analog designers are becoming a much sought after commodity. As a result, in part owing to the design complexity as well as the paucity of analog designers at a location, design teams with analog designers are getting distributed over several locations.

    The growing trends such as IoT, connected cars, medical wearables, etc. bring another critical analog design issue to the core: synergy with digital subsystems. In front-end digital design, where most of the design data is in the form of Verilog or VHDL code, engineers usually use tools like Subversion or Git that are commonly used by software developers.

    On the other hand, AMS design mainly involves schematics and layouts, which come as a binary representation. So design data management systems (DDMS) commonly used in software development and digital design are becoming increasingly error prone and inefficient for AMS environment where complexity is rising while the time-to-market window is shrinking.


    Elmos uses ClioSoft SOS data management for analog/mixed-signal design in Custom Designer tool flow

    According to Thilo Schmidt, a design engineer at Elmos Semiconductor AG, the design data management system for AMS environment should first and foremost be aware of the data structure. Moreover, it should be tightly integrated with the design tool flow. He presented a paper on this subject at the Synopsys User Users Group (SNUG) Germany held in Munich on June 25, 2015.

    In the paper titled “Analog/Mixed-Signal Data Management with Custom Designer and ClioSoft,” Schmidt shows how the SOS data management tool can be used for AMS design while being tightly integrated with the Synopsys Custom Designer platform. He presented ClioSoft SOS in combination with Synopsys Custom Designer EDA platform as a case study of how a data management tool can be integrated into an AMS design flow.

    Data Management for Analog/Mixed-Signal Design

    Schmidt opens the paper with an overview of the traditional way of carrying out data management for AMS designs. It’s usually based on a project directory on a common file server that hosts a set of shared project libraries, a PDK library, libraries with IP modules and individual work libraries for each design engineer. Next, he shows why the traditional methods don’t work anymore for large design teams amid issues such as maintenance and syncing of project libraries and accidental overwriting of changes.

    Schmidt also outlines four basic operations in a data management workflow: Check-out, check-in, tag and update. A user who wants to change a design object would start with an update operation on his workarea. Next, he would check-out the design object for editing. After he safely edits and verifies the design object in his workarea, he can check-in the design object, which will automatically create a new revision of the file in the repository. Finally, the design object is tagged as verified.


    Synopsys’ Custom Designer Library Manager with SOS integration

    Then, Schmidt goes into specifics of data management required for AMS design and shows why popular software solutions like Git aren’t suitable for the analog environment. For instance, the data management system for AMS design has to differentiate libraries, cells and cellviews. Moreover, it should know dependencies between individual cellviews. However, the data management system can only be aware of these dependencies if it’s tightly integrated into the design flow and its data structures.

    Here, Schmidt resorts to Synopsys’ Custom Designer use case that utilizes an application programming interface (API) to integrate a third-party data management system, ClioSoft SOS. ClioSoft SOS has a client-server architecture in which server can host several projects, and each project is completely independent and has its own repository.

    One of the prominent features that distinguishes SOS from other data management systems is the use of local cache servers. A user has the option to set up one or more cache servers apart from access to the main repository server. A cache server holds all the current revisions of design objects, and that saves disk space as well as prohibits users to circumvent access control by merely changing Unix file permissions.

    ClioSoft SOS also features a more elegant way to handle external data like IP modules. Here, SOS allows to reference data directly from other projects, so a special IP project can be set up instead of managing the IP modules in the design project.

    Design Flow Integration

    Finally, Schmidt comes to the crux of the subject matter: how to integrate design data management into an AMS design flow. He opens this section by showing how the project workarea is organized around the Analog directory and the Digital directory, which is home to the RTL flow. The SOS data management tool allows the RTL data to be kept in a separate project, but on the same server, so the user can tread digital data differently from analog data.

    The files in the Analog directory are generated as symbolic links to a cache server while the files in the Digital directory are local copies. Having analog and digital development work in the same project hierarchy is highly beneficial because tagging and verification results include both analog and digital domains.


    Thilo Schmidt: Data management should be tightly integrated with the design tool flow

    Schmidt also mentions the tool configuration feature that comprises the release of all tools in the design flow along with configuration options. That ensures all users have access to the same tool releases and configuration to manipulate and verify the design data.

    Schmidt closes the paper with the tapeout use case where last minute changes to the layout after the final verification runs are a common source of errors. He outlines two key objectives that have to be reached during the tapeout: a consistent and verified project state and securing of project state in a reproducible way.

    In this regard, he explains two important SOS features: Snapshot, a permanent tag that cannot be moved between revisions, and a versatile query engine that can be used to analyze the current status of all design objects. Schmidt also provides details of the tapeout flow and how it can be implemented in six concise steps.

    With a number of factors such as increased design complexity, reduced time-to-market and high NRE cost, it becomes difficult to manage and deliver SoC devices successfully the very first time. The traditional approach of handling design data is getting more and more inefficient and error prone with increasing design complexity and team sizes. A way to cope with these challenges is the deployment of design data management systems which is already common in software development and digital design.

    However, due to the complex nature of analog designs, adopting a software-based data management system becomes rather tedious and cumbersome and it becomes important to use a data management system which is aware of the data structure and is tightly integrated with the EDA design tool. A tool like ClioSoft’s SOS platform which is tightly integrated with Synopsys Custom Designer becomes an important tool to improve designer productivity and efficiency.

    Also read:

    Managing Design Flows in RF Modules

    Data Management: Bridging Digital and Analog Domains in RF Designs

    The Secret Sauce of Successful Mixed-Signal SoC Tapeouts

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    Xilinx in an ARM-fueled post-Altera world

    Xilinx in an ARM-fueled post-Altera world
    by Don Dingee on 06-29-2015 at 5:30 pm
    Categories: Arm, FPGA, Xilinx

    When the news broke about the on, off, and on-again Intel-Altera merger a few weeks ago, I checked off another box on my Six Degrees of Kevin Bacon scorecard. That plus a $5 bill gets me a Happy Meal at McDonalds, but in a post-Altera world, it might be worth more.

    On January 16, 2008, I’m sitting in a meeting with some Intel strategic marketing types discussing the embedded market. It’s a brain-picking session with Intel asking open-ended questions about trends and the competitive landscape – no NDA, because Intel isn’t sharing their information. I casually mention the concept of “SoC reconfigurability”, the idea of an FPGA sitting next to a processor core Continue reading “Xilinx in an ARM-fueled post-Altera world”

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    More about “MIPI beyond Mobile” Paper at DAC

    More about “MIPI beyond Mobile” Paper at DAC
    by Eric Esteve on 06-29-2015 at 12:00 pm
    Categories: IP

    The “MIPI Beyond Mobile” paper has been presented during the 52th DAC in San Francisco and I can share the key findings with Semiwiki readers. This paper has been written to synthesize certain results of the “MIPI Ecosystem Survey-2015” and evaluate the impact on the MIPI IP sales in the future. At first the MIPI Ecosystem has really changed between 2012 and 2015. During 2013 and 2014 the number of companies joining the MIPI Alliance in two years has been as high as during the six years before (2007-2012). MIPI technology is becoming very attractive!

    Which companies are joining the Alliance? In majority young companies (start-up), most of these targeting non-mobile (phone) applications like IoT and wearable. But we also see new members coming from Asia (China and Taiwan) developing chips for the mobile phone (smartphone) ecosystem. In summary the MIPI Alliance is renewed by emerging: emerging chip makers targeting mature application (assuming we may call smartphone a “mature” product!), and start-up and well-established companies targeting emerging applications.

    IPnest has been created in 2008 to analyze the IP market so it’s not a surprise if this paper has been proposed in DAC IP track. The initial assumption was that the MIPI IP market should benefit from these emerging (chip makers and application). What could be the metrics to validate this assertion? The first one is the MIPI IP growth rate in comparison with the other similar IP segments, like USB, PCIe, HDMI, etc. Let’s have a look at the ranking by CAGR for these different segments:

    The MIPI IP segment is clearly exhibiting the highest CAGR (47%)… it’s also the youngest IP segment in the list, so we will have to dig more: is this highest growth rate due to the normal penetration of the MIPI technology, or is it the consequence of a real pervasion of MIPI? In other words, is the growth a consequence of MIPI adoption in emerging application or by emerging (Asian) chip makers?

    Better to look at the MIPI IP market in detail, with this ranking by IP vendors in 2014:

    For those who are familiar with the Interface IP market, no surprise, Synopsys is also dominant in MIPI segment (like in PCIe, USB, DDRn, HDMI, etc.). If we look at Synopsys’s customers and analyze their nature (emerging chip maker?) and the targeted application (smartphone or emerging?), we should get a good indication about the MIPI IP market…

    From the company website, we have found these recent success stories:

    MIPI IP for Application Processor

    MIPI DSI & D-PHY IP for Application Processor

    MIPI D-PHY IP for Vision Processor Unit (VPU)

    MIPI DigRFv4 & M-PHY for 4G chips

    The first two companies are emerging Asian application processor chip makers targeting smartphones. Why externally sourcing MIPI IP to a vendor? Time-To-Market (TTM) is certainly a good incentive. As a newcomer (at least compared with Qualcomm and the like), buying MIPI DSI and PHY is not only a good way to accelerate TTM, it’s also a way to avoid re-spin by using a production proven function.

    Movidius is also an emerging chip maker developing Vision Processor Unit, but for emerging markets like IoT and wearable. Movidius core competencies are centered on vision processing and selecting MIPI technology is certainly a strategic option, but developing MIPI D-PHY will not bring any differentiation, outsourcing the PHY and concentrate on how to attack emerging markets is the best option. Even Fujitsu, obviously not a newcomer, serving an ASIC market could validate the initial assumption:

    MIPI IP segment is growing fast and is expected to grow again in the future, because MIPI technology adoption is going beyond pure mobile (phone) to serve emerging applications like IoT and wearable, or because emerging chip makers (serving the mobile market) tend to source MIPI IP externally for faster TTM and safer development by using Silicon proven IP. Just for your information, the latest forecast from IPnest suggests that MIPI IP segment should weight $90 million by 2020, plus or minus 10% and be in the $80 to $100 million range.

    From Eric Esteve from IPNEST