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June 24, 2015

Growth drivers shifting to emerging economies

Growth drivers shifting to emerging economies
by Bill Jewell on 06-24-2015 at 4:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

Global real gross domestic product (GDP) growth in 2015 is expected to be 3.5%, according to the International Monetary Fund (IMF) April 2015 report. 2015 is a slight acceleration of 0.1 percentage points from 3.4% growth in 2014. The IMF projects 2016 global growth of 3.8%, an acceleration of 0.3 percentage points from 2015. The table below shows GDP growth and acceleration/deceleration for advanced economies and emerging/developing economies. Key countries are listed under each category.

The advanced economies are expected to provide the growth acceleration in 2015. The United States, the largest economy accounting for about 23% of global GDP, is the largest contributor to the 2015 acceleration with GDP growth moving from 2.4% in 2014 to 3.1% in 2015 – accelerating 0.7 points. The Euro Area countries combined are the second largest economy and the second largest contributor to the global acceleration. Japan’s recovery from a 0.1% decline in 2014 to 1.1% growth in 2015 is the third major factor in accelerating GDP growth.

The emerging/developing economies as a whole are expected to show deceleration of 0.3 points, from 4.6% in 2014 to 4.3% in 2015. However these same countries drive the acceleration of global GDP growth in 2016 with 0.4 points of acceleration. Russia is in a major recession in 2015 with a forecast GDP decline of 3.8%, but begins to recover in 2016 with a 1.1% decline. Thus Russia contributes to global GDP acceleration in 2016 by being less of a drag on the economy than in 2015. South America shows a similar effect, led by Brazil and Argentina.

China has been a major driver of global economic growth for several years. Although China’s GDP is still expected to grow at almost twice the global rate, growth is projected to slow from 7.4% in 2014 to 6.8% in 2015 and 6.3% in 2016. India’s GDP growth is forecast to accelerate from 7.2% in 2014 to 7.5% in 2015 and hold at 7.5% in 2016. Thus India will replace China as the fastest growing major economy. The ASEAN-5 countries (Indonesia, Malaysia, Philippines, Thailand and Vietnam), the Middle East & Africa and Mexico also contribute to global GDP acceleration.

The overall message from the table is the advanced economies have recovered from slow growth in 2014 to close to long term growth rates in 2015 and 2016. The emerging/developing economies are still growing faster than the advanced economies, but growth leadership is shifting from China to India and Southeast Asia.

What is the impact on the electronics and semiconductor markets of these trends? The May 2015 smartphone forecast from market research firm GfK shows near term growth will depend on emerging regions, excluding China. Global smartphone unit growth is projected to slow to 10% in 2015 from 23% in 2014. China, a major growth driver and the largest single market for smartphones, is expected to show a 3% decline in 2015. The developed economies – North America, Europe and developed Asia/Pacific (APAC) – show growth slowing from 18% to 8%. The emerging economies – Latin America, Middle East, Africa and Emerging PAC – drive 2015 growth at 26%.

[TABLE] border=”1″
|-
| colspan=”6″ style=”width: 671px; text-align: center” | Smartphone Unit Forecast (Source: GfK, May 2015)
|-
| style=”width: 347px” |
| colspan=”3″ style=”width: 203px; text-align: center” | Millions of Units
| colspan=”2″ style=”width: 121px; text-align: center” | Change
|-
| style=”width: 347px” |
| style=”width: 78px; text-align: center” | 2013
| style=”width: 66px; text-align: center” | 2014
| style=”width: 59px; text-align: center” | 2015
| style=”width: 65px; text-align: center” | 2014
| style=”width: 55px; text-align: center” | 2015
|-
| style=”width: 347px” | World
| style=”width: 78px; text-align: center” | 998
| style=”width: 66px; text-align: center” | 1227
| style=”width: 59px; text-align: center” | 1355
| style=”width: 65px; text-align: center” | 23%
| style=”width: 55px; text-align: center” | 10%
|-
| style=”width: 347px” | North America, Europe, Developed APAC
| style=”width: 78px; text-align: center” | 374
| style=”width: 66px; text-align: center” | 440
| style=”width: 59px; text-align: center” | 476
| style=”width: 65px; text-align: center” | 18%
| style=”width: 55px; text-align: center” | 8%
|-
| style=”width: 347px” | China
| style=”width: 78px; text-align: center” | 359
| style=”width: 66px; text-align: center” | 393
| style=”width: 59px; text-align: center” | 383
| style=”width: 65px; text-align: center” | 9%
| style=”width: 55px; text-align: center” | -3%
|-
| style=”width: 347px” | Latin Amer., Middle East, Africa, Emerging APAC
| style=”width: 78px; text-align: center” | 265
| style=”width: 66px; text-align: center” | 394
| style=”width: 59px; text-align: center” | 496
| style=”width: 65px; text-align: center” | 49%
| style=”width: 55px; text-align: center” | 26%
|-

The PC unit forecast from IDC in May 2015 shows a 2015 decline of 6.2%. Mature markets show a slightly bigger decline of 6.6% compared to the emerging market decline of 5.9%. The emerging market decline is dragged down by China, which had an 8% decline in 1Q 2015 PC shipments versus a year ago according to government statistics.

IDC’s forecast for tablets and 2-in-1 PCs is a 3.8% decline in 2015 following 2% growth in 2014. Tablet growth in 2013 and prior years exceeded 50%.

How will these trends affect the semiconductor market in 2015 and 2016? The slowing of key market drivers such as smartphones and tablets will limit growth for semiconductors. The first quarter of 2015 started weakly with a 4.9% decline from 4Q 2014, according to World Semiconductor Trade Statistics (WSTS). The outlook for 2Q 2015 revenue growth for key semiconductor companies is mixed, as shown below.

Several companies are guiding for 2Q 2015 growth with around 3% at the midpoint (Intel, TI, STM and NXP). The highest growth rates are from Infineon at 9% and Avago at 7%. A few companies are expecting double digit declines (Qualcomm, SanDisk and NVIDIA). Weighted average guidance is about 3%, with a high end around 5%.

Our Semiconductor Intelligence March 2015 semiconductor market forecast was 8% for 2015 and 7% for 2016. Based on the weak 1Q 2015 and moderate expectations for 2Q 2015, we have lowered our 2015 forecast to 5.5%. We are maintaining our 2016 forecast of 7% based on some improvement in the global economy and slightly better prospects for the key drivers of smartphones and tablets.

The chart below shows recent forecasts for 2015 and 2016. 2015 forecasts are in a narrow range, from WSTS’ 3.4% to our 5.5%. Forecasts for 2016 range from WSTS’ 3.4% to our 7.0%.

Overall, the outlook for the global economy, electronics and semiconductors is slow to moderate growth over the next two years. The risk is more on the downside than the upside. Factors which could lead to slower growth are more plausible than factors which could lead to higher growth. However the prospects of an economic downturn in the near future are low.

June 24, 2015

UMC and SMIC 14nm, Too Little Too Late?

UMC and SMIC 14nm, Too Little Too Late?
by Daniel Nenni on 06-24-2015 at 1:00 am
Categories: eSilicon, Semiconductor Services

Pretty much out of nowhere UMC let fly a press release about taping out a 14nm test chip with ARM and Synopsys IP which was quickly followed by an SMIC 14nm press release about a joint venture with Huawei, Qualcomm, and imec. It caught me a bit by surprise since I spent time with both UMC and SMIC at #52DAC and nothing was mentioned. Of course Samsung and TSMC are already in production at 14/16nm and were showing 10nm wafers so maybe it would have been anticlimactic. As I mentioned before, FinFETS will forever change the foundry landscape so let’s talk about that for the remaining 400 hundred words.

Currently there are three very different versions of FinFET processes available to foundry customers: Intel 14nm, Samsung 14nm, and TSMC 16FF+. If and when SMIC and UMC are FinFET capable there will be five very different versions since UMC is licensing the IBM version and SMIC will be developing their own. UMC is expected to start FinFET production in 2016 (2017 would be my bet) and SMIC in 2020. Wait, what? 2020? Hopefully that is a typo but probably not.

Never in the history of the foundry business has there been 5 very different versions of a leading edge process offered so you have to ask yourself: “Self, just what is the fabless semiconductor ecosystem to do?” Do EDA and IP companies really have the bandwidth to support all five foundries with silicon proven FinFET tools and IP? And without the full support of the design enablement community how are all five foundries going to make money?

One thing I can tell you is that this level of competition, one which we have never seen before, will make Gordon Moore proud. The FinFET transistor cost will decrease inline with Moore’s Law despite what the idiot analysts are saying. Take a hint from the TSMC 16FFC announcement last April, 16FFC is a more cost effective version of 16FF+ aimed at the consumer marketplace. Same design rules, simpler manufacturing process (less masks), and tighter process corners. Power is said to be reduced by over 50% and the PRICING is cost-competitive against OTHER processes (meaning planar and FD-SOI).

Welcome to the new foundry landscape where cost is “MOORE” important than performance and power, absolutely. And if you believe what you read about the industry staying with 28nm forever because FinFETs are too expensive good luck with that. Let me introduce a new term for companies that linger on 28nm: FinFOOLed.

The other interesting foundry announcement is SMIC supporting the new eSilicon STAR Design Virtualization Platform. eSilicon launched this internet enabled platform with TSMC last year and I was a bit surprised that SMIC is the #2 adopter. This is a slide from the eSilicon presentation in the SMIC booth at #52DAC. You can see the full presentation HERE. Take a look at the demographics of the users, it truly is a global community. eSilicon ships MILLIONS of chips every year so yes this is a very big deal and congratulations to SMIC for being #2!

June 23, 2015

EUV: the view from imec

EUV: the view from imec
by Paul McLellan on 06-23-2015 at 7:00 pm
Categories: Foundries

I’m at the 2015 imec technology forum (ITF) in Brussels the next few days. One of the presentations today was by Peter Wennink, the CEO of ASML. The thing that most interested me in his presentation is what the status of EUV is today. ASML is the only company developing EUV steppers so what they think is important. On the other hand, they are the company building the steppers so what they say has to be looked at with some skepticism. First, what Peter said.

The motivation for EUV is that without it we will need increasingly multiple patterning. He pointed out that the biggest problem is not even the number of mask steps but the number of overlay metrology steps which goes up even faster. But EUV has to work at 7nm. It is already too late for 10nm, the plans are already set at least for the introduction. And 5nm will require double patterning even with EUV.

Since this time last year, EUV has made huge progress:

Productivity requirement 1000 wafers/day
- using 80W source printed 1022 wafers in 24 hours at one customer
- 110W power demonstrated at ASML
Availability 70%
- 55% average at multiple sites
- 82% for one week achieved at one customer
- sustained source availability about 85% on track for end of 2015
System shipments in 2015: 6
- integration of multiple systems in progress at ASML
- 2 systems on order intended for production
- volume purchase agreement with one customer (presumed by everyone to be Intel) for 15 systems of which 2 ship in 2015

Next issue, the pellicle. Clean scanner remains a priority and they are on track for 10X per year reduction in front-side defects (basically contamination from the light source or other parts of the scanner getting onto the mask, which is actually a mirror).

ASML started their own pellicle program since the traditional pellicle manufacturers were not interested. They now have a full size pellicle that covers the whole mask. Transmissivity is 85% (in one direction, the light has to go through twice though: reflective mask remember). No impact on alignment.

Inspection is a problem. Pellicle is not transparent to either visible light or e-beam so it has to be removed for mask inspection, and then replaced after inspection. Pellicle is compatible with both the mask flow and the scanner.

So it all sounds great right? Here are problems that people at the conference told me about during dinnner and breaks.

So what are the next problems?

Problems are being solved linearly. Until light source is working, nobody is worrying too much about all the other problems. Everything has to work perfectly by about 2017 if it is to be on schedule for 7nm. The equipment cannot be changed after start of qualification which is about 2 years before volume is ramped fully
Pellicle inspection. With transmissive masks, the mask can be inspected, then the pellicle added and then a final inspection done through the pellicle. With EUV can’t do that. So if a particle gets trapped under the pellicle it will print and thousands of wafers may be wasted. Currently no way to inspect unless EUV light is used but no inspection equipment like that has been developed
Heat. The light source is up to 110W and desired to go to 250W. The mirrors absorb about 30% of energy so they will get really hot. The mirrors are made of silicon molybdenum alternating layers but they have different coefficients of expansion and delaminate around 150C. Also, the mask is early in the light path and absorbs a lot of energy but must not distort or it will cause printing errors
Mask blanks are not defect free. Before adding the silicon molybdenum layers the defects are too small to see with visible light, and after they are get bigger as the mirror is built up. By the time they are visible it is too late to do anything about it. Currently no good way to fix a defect on the mask blank before patterning

If all this gets fixed and EUV is commercially viable then we should get back on track for the 40% node to node reduction in cost, which is basically an increase in node to node cost per wafer of around 20% combined with a doubling of the number of transistors per area.

June 23, 2015

Sonics’ New NoC

Sonics’ New NoC
by Paul McLellan on 06-23-2015 at 7:00 am
Categories: IP, Sonics

Today Sonics announced the latest version of their network-on-chip (NoC) technology, SonicsGN-3.0. As with any new release there are lots of improvements that are of interest mainly to existing users, but the big area with increased capability is the expanded interleaved memory technology (IMT). This was first introduced in SonicsSX in 2008 and has been in wide customer use ever since.

SoCs often communicate through external DRAM memory. But bandwidth requirements tend to go up faster than DRAM performance, and so the solution to this is to use more pins and wider memories. But with modern memory technologies such as DDR3/4 the access is burst oriented and it is really only efficient to use an 8-word burst. But that might deliver 256 bytes of which only a few are useful, while the next access has to wait for its own burst. The solution is to interleave the memory, instead of having 4 banks have 2 banks of 2. But then the challenge then is to make sure that memory access is balanced so that both banks get used heavily. If access is mostly to the first bank then that will become a bottleneck and bandwidth to the second bank goes to waste.

In a PC or Mac this is fairly straightforward to arrange, memory alternates between the two banks. That’s why, if you upgrade your memory, the DIMMs come in pairs. Alternating blocks of 64 bytes are stored in first one bank and then the other. Since most data-structures that the microprocessor is manipulating are larger than this, typically activity to the two banks will statistically get balanced between the two banks. However, this doesn’t work for memories that are being used, say, by the video subsystem on an SoC.

As Drew Wingard, the CTO of Sonics, points out:SoC designers were early in the move to multi-channel memory architectures. Use of multi-channel DRAMs and memory sub-systems is now pervasive in SoC designs, for example, in mobile applications where maximizing memory throughput takes precedence over increasing memory capacity.

In SoC designs with multi-channel DRAM subsystems, the processor speed and the total number of processors has grown to the point that the memory bandwidth bottleneck is the biggest problem. The purpose of using multi-channel memory is to exploit parallel access to memory, while avoiding bandwidth loss due to wide DRAM data buses. By breaking data into smaller word sizes and interleaving the transactions across multiple channels, IMT enables designers to improve concurrency and overall throughput by up to 20 percent using the same external DRAMs.

But to be manageable, this needs to happen transparently to the software address space view of the world (just as in your laptop you didn’t need to know about the interleaving to write code). The traffic needs to be split for delivery to the correct channel. Doing it in the memory controller causes a bottleneck at the arbiter and doesn’t really scale past two channels. IMT is a full distributed architecture which scales well. Throughput is maximized since the network automatically overlaps channel access. But by using IMT to isolate the channels from the IP cores (including processors) it is transparent to software and other hardware.

Another related concurrency management problem is ordering of requests that may be simultaneously outstanding to multiple targets, including multi-channel memories. SGN’s flexible reordering buffer architecture enables single initiator agents to have transactions outstanding to an arbitrary collection of targets, including memory channels, while respecting the protocol-defined ordering.

The other area for a major upgrade are improved links with physical design. Modern SoCs are often so big and so fast that a signal cannot get across the chip in a single clock cycle requiring registers to be inserted for retiming. Obviously these registers need to be physically spread across the chip, it is no good putting all the re-timing registers right by the receiver, for example. But with multiple power and clock domains a register cannot just be dropped down at an arbitrary location. SGN 3.0 includes new, user-controlled hierarchical partitioning and re-timing stage insertion capabilities that give designers control of which domains are associated with each re-timing stage so that they can match the floorplan. Using these features, designers can better structure their SoC designs and optimize RTL netlist generation for physical layout, which results in fewer iterations in the back-end design flow.

The Sonics press release page with full details is here.

June 22, 2015

3 Projections About Nokia’s Smartphone Reboot

3 Projections About Nokia’s Smartphone Reboot
by Majeed Ahmad on 06-22-2015 at 8:00 pm
Categories: Mobile

I have written a book on Nokia’s smartphone problem. The name of the book is Nokia’s Smartphone Problem: The End of an Icon? and it chronicles the Finnish company’s journey from a mobile handset maestro to a smartphone also-ran.

Nokia’s smartphone story began with the launch of the Communicator 900—arguably the first commercial smartphone—at the CeBIT fair in 1996. And it came to a sad end in September 2013 when Microsoft announced to buy Nokia’s mobile phone business for $7.2 billion.

An account of Nokia’s past and present situations

Here are three projections based on the chronicle of Nokia’s first smartphone play that spans from 1996 to 2013.

Leaner Business Model

The fact that Nokia is back in the smartphone game is hardly a surprise. The mobile handset is in its DNA, and the Finnish firm can’t keep away from it for long. However, more important is the fact that a far more cautious Nokia will play it safe this time around and won’t drain its resources by trying to establish full-fledged smartphone operations. Instead, Nokia will return to the smartphone market in a gradual and calibrated manner.

Nokia, probably taking cues from China’s Xiaomi, the third largest smartphone maker, will try to create an innovative business model for its smartphone market reentry. The Finnish company will most likely design the handset and then license the design and Nokia brand name to its partner who will carry out the phone manufacturing, distribution, marketing and sale.

Nokia N1 tablet provides cues on the firm’s future smartphone roadmap

Nokia demonstrated this model with its N1 tablet last year. Foxconn acquired the license for the tablet’s manufacturing, distribution, sale and after-sale support. The licensing model is similar to the approach that photography pioneer Kodak has taken after the bankruptcy.

It’s pretty ironic that the book Nokia’s Smartphone Problem has found some analogies between Kodak and Nokia. Kodak’s internal teams argued for the shift toward digital photography that the top guys ignored. Similarly, back in 2000s, Nokia’s senior management didn’t heed engineers outcry for Internet-centric, touchscreen-based app phones. A leaner Nokia seems to have learned the lesson and is moving carefully in the cut-throat smartphone business.

Continued Focus on LTE Networks

The new Nokia will remain focused on its core business of wireless infrastructure for 4G networks. Inevitably, the company sees its future in the LTE-centric mobile infrastructure business. The mega acquisition Alcatel-Lucent is a testament of that shift.

The new Nokia is led by the infrastructure man Rajeev Suri

However, the Finland–based firm still boasts valuable resources and intellectual property related to the smartphone technology. So it’s not in Nokia’s larger interest to put all eggs in one basket: mobile networks. It’s worthwhile to note that Nokia seems open for selling its HERE location business at a good price.

Moreover, mobile business with both network and terminal units is still seen as a panacea in the wireless telecom world. The two businesses have a natural synergy. It’s just that consumer-focused mobile phone business will merit a lower priority for Nokia than engineering-heavy business-to-business focus of LTE-based mobile networks equipment.

Choice of Mobile Platform

It’s most likely going to be Android. The book Nokia’s Smartphone Problem narrates the story of how Nokia secretly began to work on an Android fork in 2012, and the outcome was Nokia X phone launched at the Mobile World Congress (MWC) in Barcelona in February 2013. Apparently, Nokia’s mobile OS partner Microsoft didn’t like it. In the hindsight, Nokia’s advances toward Android became a factor in Microsoft’s decision to buy Nokia’s mobile business later that year.

Nokia’s Android phones launched in 2013

The fact that Nokia has based its N1 tablet on Android mobile operating system further reinforces this premise. There are some industry watchers who point to Jolla’s Sailfish operating system, which is a MeeGo progeny. MeeGo was the mobile operating system that Nokia co-developed with Intel as an alternative to hopelessly buggy Symbian platform.

But Nokia’s liaison with Jolla’s Sailfish platform is unlikely because the new Nokia won’t take an unnecessary risk and will go with the flow. And the flow is apparently with Android.

Predicting Lifetime of Analog ICs

Predicting Lifetime of Analog ICs
by Pawan Fangaria on 06-22-2015 at 12:30 pm
Categories: EDA, Siemens EDA

With the increase of transistors per unit area, high density interconnects and manufacturing variability at lower nodes, the electronic devices have become more vulnerable to failures. The devices that operate under extreme conditions such as automotive devices that operate at high temperatures need to be robust enough to sustain through their lifetimes. Automotive devices typically have longer lifetimes which can last for ten or more years. There can be several factors that can degrade the reliability of a device, thus affecting its lifetime. The major reliability degradation factors include NBTI (Negative Bias Thermal Instability), HCI (Host Carrier Injection), and TDDB (Time Dependent Dielectric Breakdown). How to predict the life of an IC amidst such degradation effects?

The effects such as BTI and HCI have to be modeled and simulated. For analog and RF circuits, advanced analog and mixed-signal simulators are used which need to simulate the circuit efficiently and provide accurate results including statistical aging analysis. The reliability and aging analysis must be done early in the design cycle to avoid product recall later which may incur significant loss to the company.

Mentor Graphicshas a very effective and efficient verification flow for reliability which uses their Eldo circuit simulator. It compares the behavior of a fresh circuit just out of fab against the behavior of the same circuit aged after N years of operation under arbitrary periodic conditions. The lifetime of the fresh circuit can be predicted from the comparison of results.

Eldo uses a model which computes instantaneous stress of transistors subject to a given bias and temperature. The stress for each device is computed and integrated during normal simulation. The accumulated stress after Y years is computed by linear extrapolation. Eldo uses another set of equations which model the way ‘fresh’ model parameters are modified into ‘aged’ ones by this accumulated stress. A new ‘aged’ simulation is run using these updated model parameters. This flow can be performed, either quickly in 2 steps or in N steps. The N-step flow can provide more accurate results, however it will be slower by N times.

The aging by nature is a statistical process. Two identical devices can have slightly different threshold voltages, drive currents, and leakage currents. They also can have different aging profiles. Even if the bias conditions are identical, they do not age the same way. The required measurements are complicated, lengthy and costly. Eldo UDRM (User Defined Reliability Model) extensions support Monte Carlo simulation on aging parameters; supported models include BSIM3/4SOI, PSP, HiSIM etc.

The aging sensitivity analysis provides insight about which aging device is important and has most impact on outputs. A significantly degraded device may have little impact on circuit performance whereas a little degraded device may have significant impact on output performance. The reliability analysis with Harmonic Balance Steady-State is supported for RF circuits.

Eldo UDRM flow provides a robust and flexible solution for reliability analysis of ICs. It supports customizable aging models in Spice and Verilog-A languages. The reliability simulation offers encryption mechanisms to protect intellectual property of equations and models of degradation effects. The advanced model definitions allow designers to account for these degradation effects much early in the design.

This methodology was presented in 52[SUP]nd[/SUP] DAC at Mentor booth by Ahmed Eisawy, Eldo Product Marketing Manager at Mentor. Also, there is a case study done by Vitessewhich is posted on Mentor website; Joint Design – Reliability flows and advanced models address IC reliability issues. This case study also shows how reliability issues can be debugged by visualizing instantaneous stress pulses as experienced by the device.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

June 22, 2015June 14, 2019

SEMulator3D on Silicon Cloud International

SEMulator3D on Silicon Cloud International
by Paul McLellan on 06-22-2015 at 7:00 am
Categories: Coventor, EDA

Almost exactly a year ago I wrote about Silicon Cloud International (SCI). Their mission is to help smaller countries that have targeted semiconductor design as a way to move up the technology ladder from low-cost manufacturing. Last year everything was in the future but SCI now have their first two centers up and running. The first, a pilot program, was announced at the end of last year and is in UAE. The second, announced a couple of months ago is in Singapore (which is also SCI’s home).

In EDA the pioneer in using the cloud was probably Nimbic (now part of Mentor). If the cloud is going to work anywhere in EDA then these types of applications that require hugely scalable compute resources, don’t involve gigabyte files, and don’t contain the entire company crown jewels are likely to be the first places. I just wrote a blog last week on the IBM announcement of its library characterization tools in the cloud, with some skepticism about doing an entire design in the cloud.

Another area that seems a good match is virtual fabrication whereby a full 3D model of a part of a process is built up from the process recipe and a small amount of layout. This can then be verified. The process is computationally expensive and a lot of verification can be run in parallel, so the scalable nature of the cloud is idea.

At DAC on the SCI booth I watched a demo of Coventor’s SEMulator3D Virtual Fabrication platform with broad parallel computing offered by Silicon Cloud. Coventor is calling this 3D Design-Technology Checking (3D-DTC).

SEMulator3D enables process predictive virtual fabrication of any design in any process flow. I’ve blogged about this before, most recently about vertical flash memory. Using SEMulator3D’s Automation features, users can easily virtual fabricate hundreds or thousands of models representing process or design variations, and then check them in true 3D space for critical yield criteria. The broad computational resource added by Silicon Cloud allows this to be done across a huge process space in a very short time. This especially important for companies that do not have extensive compute farms available (or “private cloud” seems to be the trendy word for a compute farm these days).

GlobalFoundries IBM Deal to Close July 1st!

GlobalFoundries IBM Deal to Close July 1st!
by Daniel Nenni on 06-21-2015 at 5:00 am
Categories: Foundries, GlobalFoundries

Probably one of the most awaited semiconductor events is coming next week if the Poughkeepsie Journal is correct, which from what I’m told by my Albany friends, they are. The official announcement was made last October using the slide deck which can be found HERE. It was originally thought that the approval process would take a year so someone must have really pushed this one through.

ARMONK, N.Y., and SANTA CLARA, Calif., October 20, 2014: IBM (NYSE: IBM) and GLOBALFOUNDRIES today announced that they have signed a Definitive Agreement under which GLOBALFOUNDRIES plans to acquire IBM’s global commercial semiconductor technology business, including intellectual property, world-class technologists and technologies related to IBM Microelectronics, subject to completion of applicable regulatory reviews. GLOBALFOUNDRIES will also become IBM’s exclusive server processor semiconductor technology provider for 22 nanometer (nm), 14nm and 10nm semiconductors for the next 10 years.

Given the latest semiconductor acquisition spree this may not seem like a big deal but I think it is by far the most interesting one we will ever see. Some say this is an exit strategy with Samsung being the ultimate suitor. Others say it is a Greek tragedy in the making. Time will tell but personally I think it is a brilliant move in what will prove to be one of the more interesting chess games our industry has ever seen, absolutely.

Paul McLellan and I spent quite a bit of time on this from both the GF and IBM side of things. Here is a quick summary of the benefits we see for this acquisition:

The IBM ASIC business is exactly what GF needed to get into the system houses
The IBM IP portfolio is exactly what GF needed to differentiate in the fabless semiconductor ecosystem
The IBM talent (5,000+ employees) is exactly what GF needed to create an East Coast semiconductor dynasty
The IBM patents (10,000+) is exactly what GF needed to secure their semiconductor legacy
The IBM acquisition is exactly what GF needed to secure a nice investor exit (IPO)
Reinforces GlobalFoundries’ long-term commitment to manufacturing and technology leadership
Provides R&D expertise to give a path to 10nm and beyond
Expands segment growth in RF and ASIC
Becomes IBM’s sole source foundry partner
Gives them strategic relationships with top OEM industry suppliers

“This acquisition solidifies GLOBALFOUNDRIES’ leadership position in semiconductor technology development and manufacturing,” said Dr. Sanjay Jha, CEO, GLOBALFOUNDRIES. “We can now offer our customers a broader range of differentiated leading-edge 3D transistor and RF technologies, and we will also improve our design ecosystem to accelerate time-to-revenue for our customers. This acquisition further strengthens advanced manufacturing in the United States, and builds on established relationships in New York and Vermont.”

“The Agreement expands our longstanding collaboration, which began when GLOBALFOUNDRIES was created in 2009, and reflects our confidence in GLOBALFOUNDRIES’ capability,” said IBM Senior Vice President & Director of Research Dr. John E. Kelly III. “This acquisition enables IBM to focus on fundamental semiconductor and material science research, development capabilities and expertise in high-value systems, with GLOBALFOUNDRIES’ leadership in advanced technology manufacturing at scale and commitment to delivering future semiconductor technologies. We are grateful for the leadership and investments by the states of New York and Vermont in supporting the semiconductor industry.”

IBM, GlobalFoundries deal to close July 1; new look for tech

June 20, 2015June 14, 2019

Unlock the Key to Ultra-Low Power Design

Unlock the Key to Ultra-Low Power Design
by Tom Simon on 06-20-2015 at 7:00 am
Categories: EDA, Events, MunEDA

We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low power and it brings with it a completely new level of expectations, and design complexity.

Ultra low power is needed to run RFID, implantable devices, remote sensing platforms, or wearable tech. It needs to run with no built in power source, as is the case for RFID, or with very limited power, such as with small lithium polymer batteries charged by solar energy. The needs of ultra low power have pushed design methodology into new areas, like sub threshold CMOS analog design. With this shift in design comes the need for new tools to solve difficult design problems.

While digital designers are looking to drive their transistors into strong inversion rapidly to quickly move through the highly resistive transition that draws power and dissipates thermal energy, analog designers are interested in weak and moderate inversion modes so they can save power and achieve high gain – gm/Id. Threshold voltages have dropped to save power across the board, and analog designers are looking to operate their circuits at sub threshold voltages for a variety of reasons.

Circuits that operate in the moderate inversion region are very conducive to analog design. In fact gain values can exceed those of BJT’s, and thermal noise can be lower because of less carrier scattering. But care needs to be given to evaluate the effects of variation and the properly optimize the circuit to ensure operation in the region that was intended.

Designers end up with a complex multi-variable, multi-objective design problem that has many dimensions and tricky sensitivities. The old days of picking gate dimensions with a spreadsheet and running a few simulations to verify and fine tune the results are long gone. In fact simulation needs to move from being a verification tool to a design tool.

This is exactly what Munich based MunEDA was showing at #52DAC recently in San Francisco. I met with Michael Pronath VP of Products and Solutions at MunEDA to see a demo and discuss their solutions for optimizing analog circuits designed for ultra-low power. He used theoir WiCKeD suite to run through the flow on a Miller OpAmp operating at 1.2V. The design targets were: Phase Margin > 70, GBW = 1MHz and of course absolute minimum power. He used WiCKeD to optimize all the transistor W,L values, set the bias current, etc.

While maintaining all the design objectives Michael showed me how the design can be optimized with their Deterministic Nominal Optimization DNO to achieve the lowest power with all the transistors operating in moderate inversion. They can even add in process and thermal variation to be sure that the circuit is well behaved for high yield and reliability.

The results were impressive and showed an improvement over the classical and gm/Id methodology. Certainly gm/Id is a good method for evaluating transistor circuits in moderate inversion, but WiCKeD’s numerical sizing approach is good at optimizing yield and reliability, which are nearly impossible with other approaches with capacity constraints. WiCKeD works comfortably with:

>100 specifications and constraints handled simultaneously
>200 design variables
>2000 MOS Post-layout effects and parasitics supported
Multiple test benches, goals, and corners are considered

The user interface also allows designers to go through the flow by combining step visually to arrive at a set of alternatives to pick the best results.

MunEDAhas quietly been collecting a large majority of the top semiconductor companies in its customer list. For me seeing the software in use helped clarify the operation and advantages of their unique approach. I can see why designers would like their approach for getting the lowest possible power out of sensitive designs.

MORE INFORMATION ON LOW POWER CUSTOM IC DESIGN HERE!

June 19, 2015June 14, 2019

An Universe of Formats for IP Validation

An Universe of Formats for IP Validation
by Pawan Fangaria on 06-19-2015 at 4:30 pm
Categories: EDA, Fractal Technologies

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the number of different formats and databases the tool supports. Crossfire’s unique common data model allows different databases and formats to be cross-checked for completeness and correctness against a golden reference format or against a previous release.

There are formats to support different levels of descriptions for a design at the chip/IP, cell, transistor, or layout levels. Also there are specialized formats to describe parasitic, power, timing, test, parameter variation, and other aspects of circuits at the cell or macro levels. As the technology progresses through lower process nodes, new physical effects come into existence and they need to be modeled in many different ways. It’s not simple for designs to migrate to newer technology nodes without provisioning for newer physical effects through newer, perhaps complex models. The result is ever increasing number of design formats including but not limited to verification and power and timing specifications. Also, there are different databases from major vendors in the semiconductor industry, e.g. OpenAccess and Milky Way. Imagine this volume and diversity of data that has to be accommodated and managed in a common system like that of Crossfire. Provision to accommodate all types of formats and databases is imperative because an SoC can have IPs from multiple vendors in multiple different formats. Crossfire has a robust process of including any new format into its data model.

Fractal Technologiescommon data model for Crossfire is extensible to easily accommodate any new format. Crossfire’s first phase is to check completeness of the format for all object types including cells, pins, nets, timing arcs, and also power domains. The Crossfire compares any item that has been parsed with the equivalent item from a reference. Once a new format is proven complete, it means that its generation is well integrated into the automated characterization flow. So, any new cell or process corner added into the IP will be correctly and automatically included into the new format as well. At the SoC level, after Completeness Checks for all formats of an IP, the IP becomes ready for integration.

In the second phase, the intrinsic quality of the format is checked where characterization data such as timing and power values are checked for their correctness according to their physical aspect. Crossfire provides a rich set of quality assurance checks to dive deeper into the models provided by different formats such as trend-checks for timing and power values across process corners. For example, it can take various process corners described in the .lib files and check whether delays will indeed increase with rising substrate temperature or decrease with increasing supply voltage. The Intrinsic Quality Checks of IPs are done for final verification of the SoC before tape-out.

Recently some very important formats were added into Crossfire –

Apache Power Library (APL): This format models all power aspects of a particular cell or IP and is an important input to ANSYS’RedHawk for IR drop and reliability verification. Besides completeness check, Crossfire also checks trends for APL such as increasing currents at increasing output loads.

Unified Power Format (UPF): This is another power format promoted by Synopsys. The purpose of UPF is to describe power domains, voltages and related pins for the entire design. The power domains have to be physically separated networks in the IP design. Crossfire verifies this requirement by cross-checking UPF against SPICE netlist.

Core Test Language (CTL): This is an IEEE standard for describing the Design for Test (DFT) interfaces of a particular IP. Crossfire checks consistent naming of pins for test-control and scan-chains and their proper functionality.

Advanced On Chip Variability (AOCVM): This is an extension to Synopsys’ Liberty and is aimed at modeling the variation of cell-delays during manufacturing at lower process nodes like 14nm and 10nm. Crossfire checks for completeness and consistency of AOCVM against the available Liberty models for timing and power. It also checks for trends such as reduced variability of delays with increasing logic depth.

The Crossfire is versatile enough to include documentation formats as well. Through a PDF reader, the end-users also can parse their own proprietary datasheets into the Crossfire common data model and check the documentation for completeness. Currently, Crossfire supports over 40 different formats and databases and is able to add a new format within a few weeks time. Crossfire also provides a flexible API for users to code their proprietary checks on their IP, and those can be added on the GUI as well.

Thus Crossfire offers a very powerful environment to check IPs before their integration into an SoC and also to verify quality before the SoC tape-out. There is also a whitepaper HERE to read for more information.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com