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A Brief History of Apple Mobile and SoCs

A Brief History of Apple Mobile and SoCs
by Daniel Nenni on 09-09-2015 at 2:30 pm
Categories: Arm, Mobile

The big Apple iProduct announcement was today so I thought it would be a good time to premier a draft of the Apple chapter in our upcoming book. Try as I might I was unable to get one of the 7,000 tickets to the live event (it was like getting a Willy Wonka golden ticket!) so I live streamed it from my iPhone like millions of other people. It ran over two hours but is definitely worth your time, especially if you like the band OneRepublic.

The Apple chapter starts with Steve Jobs 2.0 (his return to Apple) and chronicles the rise of the iProducts from start to finish. This is a no holds barred account of how Apple redefined mobile and became the most powerful fabless semiconductor company in the world, absolutely.

SemiWiki Book Download:A Brief History of Apple Mobile Devices and SoCs

The Apple chapter is in wiki form so please excuse the formatting. This advanced look is exclusive to SemiWiki members. If you are not currently a member please join as my guest: https://www.legacy.semiwiki.com/forum/register.php

If you have questions, comments, and/or corrections post them in the discussion section of the wiki. The following is the prologue of the book. Enjoy!

MOBILE, UNLEASHED
The Origin and Evolution of ARM Processors in Our Devices

How does a company go from a crazy idea a couple of engineers had for designing a processor from scratch to power a “business computer,” to being the maker of the family of processor cores at the heart of roughly 95% of the world’s mobile phones today?

At the dawn of the ARM architecture, the project was a tightly kept secret in a few technologist’s hands at Acorn Computer Group. It was so secret that Olivetti, a firm at that time in the process of shifting its fortunes from typewriters to computers, was not aware of the existence of the chip design or its development team until after an investment stake in Acorn became final.

What Acorn had was a processor quite unlike any other of the period – but that was far from all. They established a reduced instruction set for machine-level programming most users never see, software development tools for using it, and the concept of a customized processor core for independent fabrication.

Challenging the Mainstream
Given that breakthrough, one would think Acorn could have taken the world by storm right out of the gate. However, in the mid to late 1980s, the scene was far from ready for an alternative to the mainstream chips.

Intel was building its empire on the processors that throbbed inside nearly every personal computer. Semiconductors came from Silicon Valley, designed in big, expensive buildings – not in rustic barns near Cambridge, UK. Parts were typically complex, huge, costly, and hot. Being the fastest gun in town, and staying that way, was priority number one under Moore’s Law.

The source of popular software was Redmond, Washington, and anything incompatible with Microsoft was unable to survive for long. A thriving flock of personal computer companies found out the hard way that PC compatibility was the only thing people cared about, or asked for. If a processor could not run MS-DOS, Lotus 1-2-3, Word Perfect, and Turbo Pascal, what good was it?

Those forces left even the now mighty Apple dangerously near bankruptcy at one point after initial success with the Apple II. The comeback was underway; their latest innovation was the Macintosh, built on a Motorola processor and a graphical user interface (GUI) that introduced the mouse to millions of people. It was just different enough to hang on pitted against a wide row of function keys and never-ending combinations of ALT, CRTL, and SHIFT codes on the other side.

Coincidentally, those two companies – Apple and Motorola – running on separate tracks in the early 1990s paved the way for ARM to rise from the relative obscurity and limited volumes of Acorn.

Research on computing alternatives had been underway at Apple for some time, spawned in part by a leadership change from Steve Jobs rev 1.0 to John Sculley. The objective: break off from the desktop and into handheld platforms then known by the clunky category name of “personal digital assistant.” The first Apple PDA project was Newton, and along the way, they reached out to Acorn for an ARM core.

Meanwhile, Motorola led the way to the height of the analog cellular telephone sensation. As phones evolved from analog to digital, one key to reducing size and bill of materials cost became digital signal processing (DSP). In a twist of fate, seeking to diversify business and not compete with customers for capacity, Motorola did not leverage their own semiconductor parts. Instead, as the digital handset revolution took shape they opted mostly for popular DSP chips from Texas Instruments – as had Ericsson, Nokia, and others.

More Than a Cool Idea
Those Apple and Motorola tracks may seem completely separate, but they collided head on in digital mobile devices. Microprocessors were too big and power hungry, and microcontrollers were too slow. Code such as multitasking operating systems, wireless communication stacks, and handwriting recognition – once thought to be the killer application for PDAs – sucked the life out of most CPU architectures.

A dire need was developing for a more optimized but fast processor core, and better integration with lower power DSP capability for handling wireless signals.

With a complex instruction set, or CISC, changing anything to improve performance risked mangling instructions, and breaking software. Motorola would enjoy early success in PDAs with their scaled-down part, the MC68328 DragonBall, winning designs such as the original Palm Pilot. Intel and their X86-compatible ecosystem had initial device wins at IBM, Research In Motion, and Nokia. Both CISC processors found themselves displaced as alternatives emerged.
Long before Steve Jobs rev 2.0 returned and eventually defined the post-PC era, Apple saw greater potential for the ARM architecture. With the Acorn development team and their fab partner VLSI Technology, Apple helped form a joint venture in 1990: Advanced RISC Machines, Ltd. One brand was born, and another remade, ushering in sweeping change in mobile device leadership.

If ARM had been just another company with a cool idea for an embedded processor core, there would not be much more to add to the history – one that others have visited numerous times. Covering ARM from its stealthy origins as a few determined, creative people inside Acorn to today with over 50 billion processor cores shipped and counting is inspiring, but not the whole story.

In this book, we explore the origin story of ARM from an industry perspective, and the evolution of its processor technology that unleashed mobile devices.

Once the Acorn and Apple teams joined forces, sharing their early parallel experience that we open this book with, the bond between mobile devices and the ARM architecture formed. That bond is now nearly unassailable despite massive investments from competitors, mostly because its basis is more than a semiconductor company designing and selling parts to a segment of customers.

An entire ecosystem, in many ways more diverse and more powerful than the impressive PC community, has developed around the combination of mobile and ARM. It reaches across the entire supply chain, from EDA firms, foundries, semiconductor companies, software companies, mobile device manufacturers, carriers, application developers, and makers, who have rather recently joined in.

We will look at not just the processors and phones and tablets and other devices, but the business of mobile as it evolved along the lines drawn by each successive generation of ARM technology. We will have insights on the obvious names – Apple, Google, Qualcomm, and Samsung among them – and some not so prominent ones that played important roles building up to today. Perhaps most fun, we will wrap up with an analysis on where we see all this going in the future.

A journey of billions of processors and beyond begins with a single step. Now, we go back to the beginning of ARM, which on the surface had nothing to do with mobile but everything to do with creating a better processor core.

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On The Beauty Of Turkey Vultures

On The Beauty Of Turkey Vultures
by Bernard Murphy on 09-09-2015 at 12:00 pm
Categories: General

Now and again I like to switch from technical topics and write about something good for the soul. I’m involved with a wildlife rescue organization; we take orphaned and injured birds (generally found by members of the public), nurse them back to health and release them back into the wild. We have permits all the way up to the federal level, we get regular training, we’re a 501(c)(3) charity – it’s quite an operation.

Among the more interesting birds we’ve had recently were three turkey vultures. I’m willing to bet if you think about vultures at all, you think “ugly, eat dead stuff, yuck”. But there’s a lot more to them than that. The first of the three was an adult with fractures in the collarbone (coracoid) area, possibly flew into a car or maybe he hit a tree. This one was spotted out in the wilds by a couple of horseback riders. Then there was a juvenile, in generally good health but skinny and wandering around by the side of the road – called in by the Sheriff. Finally, we got a baby, found under a homeowner’s deck. Both the baby and the juvenile were dehydrated and were probably straying from home looking for a source of water (that darned drought).

You probably haven’t seen a baby turkey vulture before. They’re pretty cute – all white fluff with a black face.

They instinctively know they should threaten when approached but the execution is a little less than terrifying. This kid would stamp its feet and charge at us but – like any toddler learning to walk – would immediately fall flat on its face.

Once they had a plentiful supply of food and water both the baby and the juvenile recovered quickly. The adult also recovered but more slowly as broken bones knitted and he regained strength in flight muscles. Here are the three of them in a flight cage, the juvenile up top, the adult lower down and the growing baby at the bottom.

The adult was not happy that he wasn’t strong enough to fly to the top perch; this put him lower in the hierarchy than the juvenile and he was not about to be subservient to a teenager. As soon as he could make it to the top, they got into it. In a lot of species, dominance battles can be quite violent, but these guys were more civilized. They started with chest-butting; when that wasn’t going anywhere the adult switched tactics. Vultures indicate submissiveness by not making eye-contact with the leader, typically by hanging their heads when the boss is around. The adult realized if the pretender wouldn’t voluntarily look down, he could force the issue by standing on his head. Since vultures are fairly hefty birds the juvenile lost to simple mechanics. After a few rounds of this, he evidently concluded that a demotion was preferable to a vulture hat.

Vultures are very social birds. You commonly see large groups roosted in trees or power pylons, or circling an area looking for good eats. They’re not so keen on us though. An adult’s favored response to a perceived threat (a human approaching for example) is to vomit, which is a disgusting but very effective way of discouraging any would-be attacker, although the principal purpose seems to be to shed weight so they can take off quickly. Whenever we had to handle these three we were always very careful to wait until they had fully digested their previous meal. Not that they don’t still try to gross us out, like this guy.

After they all recovered we released the birds at a nearby park. Releases are the best part of what we do, so we get plenty of help, in this case from volunteers and a couple of park rangers. The adult flew straight to a tree where maybe 30 other vultures were already roosting, but the baby (now grown) and the juvenile took off and soared over the reservoir, just enjoying the thrill of flying free and catching thermals. Seeing that made it all worthwhile.

If you’ve read this far, I hope you feel you learned a little about vultures. Maybe these amazing birds can also offer something you can take back to your regular job. A group of vultures gathered together in a roost is often called a committee. When they’re feeding together, they’re called a wake. So next time you’re in a committee meeting and you feel you’re surrounded by vultures, you’ll know why. When lunch is brought in, you can share how much you’re enjoying the wake (I remember some working lunches that felt that way). And while I wouldn’t recommend vomiting as a debate tactic, when a committee member gets a little too aggressive, you can always try standing on their head.

More articles by Bernard…

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Explore Your Interconnect the ICScape Way

Explore Your Interconnect the ICScape Way
by Paul McLellan on 09-09-2015 at 7:00 am
Categories: EDA

One of the surprises at DAC for ICScape was to be listed on Gary Smith’s list of companies to see. Surprised, since ICScape had never presented their products to him. They were listed under design debug. They don’t have a single product that really falls under that description, but rather a family of tools under the ICExplorer family such as ClockExplorer.

Part of the family is a tool for interconnect analysis which is called RCExplorer. Although like any tool it can be used for many things (who hasn’t put in a screw using a hammer?) it is targeted at 3 main functions:

  • fast resistance/capacitance analysis which works with popular layout editing tools
  • post-extraction interconnect analysis
  • interconnect comparison of different versions of a design

RCExplorer works with popular layout editing tool environment, and is also tightly integrated into ICScape’s own chip finishing environment Skipper. It gives a way to do a quick analysis of interconnect during design, looking for high resistance paths that might lead to ESD problems, or to differential paths that should have the same resistance, and more. To do this does not require the user to run a time-consuming LVS and full extraction, RCExplorer does what is necessary under the hood starting from the layout itself. At its most basic the user can select two points on the layout and RCExplorer will display the resistance between them, giving the resistance by segment/layer/location. When used within the Skipper platform, which has fast net-tracing capability, RCExplorer can provide flexible point-to-point analysis for large nets, such as power and clock nets, completely or partially, for interactive usage.
The way it works is to extract the segment resistances of the whole net using patterns, add virtual current sources at the two specified points, compute voltage at points using a high-performance matrix solver and then get the equivalent resistance between the two points based on voltage/current values. It only performs extraction once per net, so it it fast to do resistance analysis for multiple points on the same net.
The next use-model is post extraction. Instead of doing its own layout analysis, RCExplorer reads in the DSPF parasitic file directly. It then reports:

  • pin-to-pin resistance
  • net capacitance, both total and coupling
  • pin-to-pin delay on the flattened design
  • it can run analysis on either selected nets, using filters, or on all nets
  • it can run analysis on a selected pin pair or on all pin pairs
  • it can handle the largest nets: power, ground, clocks etc

If the DSPF file contains layout information for the nodes and RC devices, RCExplorer can also do cross reference between layout-editing tool and the analysis result, very useful during post-layout debugging.

The final use model is to compare two versions of the same design at the DSPF level. The normal way to do this is to set some filter, and get RCExplorer to identify, for example, all nets that have changed by more than 5%. The same analysis can be used to compare two different extractions with different tools, looking for nets where the two extractors are off by more than a trivial amount. The error distribution can be displayed either graphically or in tabular format.

A tool like RCExplorer is only useful if it is accurate. Comparing its calculations to a “golden” HSPICE simulation over thousands of pin-pairs in a design shows the accuracy is 0.005% (so 0.00005 which has to be in the noise).

The analysis is also fast because the use of advanced matrix solver technology and reuse of analysis models. Analyzing a 343 net design (60K pin-pairs) with a 1GB DSPF took just 1 minute 38 seconds. Analyzing a design with 265K nets (21M pin-pairs) took 1h 33m from a reduced DSPF and 6h 12m from a non-reduced DSPF.

RCExplorer is in full-release. It is in use at several customers including a major flash-memory company. They haven’t given permission to use their name so you will have to make your own guess as to which one.

See also How Good Are Your Clocks?
See also What is Skipper?

The RCExplorer product page is here.

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Breakthrough Battery Life for Mobile Devices

Breakthrough Battery Life for Mobile Devices
by Daniel Payne on 09-08-2015 at 6:02 pm
Categories: Mobile

Battery life is a never-ending battle for me with all of my mobile devices: Laptop, Tablet, Smart phone, bike computer, Kindle Reader, Bluetooth headset, etc. It seems like I’m constantly having to charge up my battery at the most inconvenient times. When I think about the history of batteries for mobile devices I can recall all of the technology generations for mobile phones:

  • Nickel Cadmium (aka NiCad) – used in the 1980’s and 90’s, had a memory effect so make sure to let fully discharge before charging.
  • Nickel Metal Hydride (aka NiMH) – no memory effect, smaller, faster charging.
  • Lithium Poly Ion (aka LIB) – no memory, smallest, fastest charging, can catch fire or explode.

There’s an emerging battery replacement technology based on Hydrogen Fuel Cells that could be making its way to mobile devices soon, because astute followers of Apple have noted a recently awarded patent, “Fuel Cell System to Power a Portable Computing Device“. The benefit of using a fuel cell is that it would power your notebook or smart phone for days or possibly weeks between charging. Here’s a figure from the Apple patent showing all of the components:


US Patent #20150239280

In this particular patent they show a Mag Safe connector, something only used on the MacBook series of notebooks from Apple, although there’s a British company Intelligent Energy that has already developed a hydrogen fuel cell prototype for the iPhone 6. Since a fuel cell based on Hydrogen emits water vapor, they had to place vents on the rear of the iPhone 6.

The fuel cell system also has some electronics built-in control the DC voltage and communicate with the mobile device, shown in figure 1B below:

Some folks speculate that Intelligent Energy may be working with Apple on commercializing this technology for MacBook notebooks or future generations of iPhones. No matter how it comes to market with Apple or Intellgent Energy, it now appears that Hydrogen fuel cells are coming to our mobile devices with the immediate benefit of increased time between charges to days or weeks. I look forward to this improvement because it will simplify my busy life, plus I love trying new technologies.

Related reading – Fuel Cell Technology Total Game Changer

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Congratulations Dr. Walden C. Rhines!

Congratulations Dr. Walden C. Rhines!
by Daniel Nenni on 09-08-2015 at 1:00 pm
Categories: EDA, Siemens EDA

A funny thing happened at the Design Automation Conference last June in San Francisco. I was browsing the Kaufman award winner mug shots in the EDAC booth and noticed that Wally Rhines was NOT a winner. You can see them HERE. Immediately in disbelief I said to myself: Self, how can this be? Joe Costello, Aart de Geus, and some other guys I have never heard of are there but no Wally? I then said the same thing to Bob Smith, the new EDAC Executive Director. In fact everyone I mentioned it to was either shocked and/or in disbelief. How could EDAC overlook a man with this pedigree:

WALDEN C. RHINES is Chairman and Chief Executive Officer of Mentor Graphics, a leader in worldwide electronic design automation with revenue of $1.24 billion in 2014. During his tenure at Mentor Graphics, revenue has nearly quadrupled and Mentor has grown the industry’s number one market share solutions in three of the ten largest product segments of the EDA industry.

Prior to joining Mentor Graphics, Rhines was Executive Vice President of Texas Instruments’ Semiconductor Group, sharing responsibility for TI’s Components Sector, and having direct responsibility for the entire semiconductor business with more than $5 billion of revenue and over 30,000 people.

During his 21 years at TI, Rhines managed TI’s thrust into digital signal processing and supervised that business from inception with the TMS 320 family of DSP’s through growth to become the cornerstone of TI’s semiconductor technology. He also supervised the development of the first TI speech synthesis devices (used in “Speak & Spell”) and is co-inventor of the GaN blue-violet light emitting diode (now important for DVD players and low energy lighting). He was President of TI’s Data Systems Group and held numerous other semiconductor executive management positions.
Rhines has served five terms as Chairman of the Electronic Design Automation Consortium and is currently serving as a director. He is also a board member of the Semiconductor Research Corporation and First Growth Family & Children Charities. He has previously served as chairman of the Semiconductor Technical Advisory Committee of the Department of Commerce and as a board member of the Computer and Business Equipment Manufacturers’ Association (CBEMA), SEMI-Sematech/SISA, Electronic Design Automation Consortium (EDAC), University of Michigan National Advisory Council, Lewis and Clark College and SEMATECH.

Dr. Rhines holds a Bachelor of Science degree in metallurgical engineering from the University of Michigan, a Master of Science and Ph.D. in materials science and engineering from Stanford University, a master of business administration from Southern Methodist University and an Honorary Doctor of Technology degree from Nottingham Trent University.

When I asked Wally about it he mentioned that he had been nominated before so there was a nomination form on file but maybe he was considered more of a semiconductor versus an EDA veteran. Suffice to say he is definitely an EDA veteran now, absolutely!

The other thing you will notice is that there are no female Kaufman winners. My bet is that next year that will no longer be the case.

About the Phil Kaufman Award
Presented by the Electronic Design Automation Consortium and the IEEE Council on Electronic Design Automation, this award honors an individual who has had demonstrableIMPACTon electronic design through contributions in the field of Electronic Design Automation (EDA).

  • Business Impact
  • Industry Direction and Promotion Impact
  • Technology and Engineering Impact
  • Educational and Mentoring Impact

The 2015 Phil Kaufman Award will be presented on Thursday, Novmeber 12 [SUP]th[/SUP], 2015 in conjunction at the 4 [SUP]th[/SUP]Street Summit Center in San Jose. [ Additional Information]


Also Read: Wally’s Fireside Chat at #52DAC!

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How MunEDA Helps Solve the Difficulties of AMS/RF IP Reuse

How MunEDA Helps Solve the Difficulties of AMS/RF IP Reuse
by Tom Simon on 09-08-2015 at 12:00 pm
Categories: EDA, General, IP, MunEDA

Reusing design IP is crucial for competitiveness. The need for reuse occurs with new designs on the same process node as the original design, new designs at the same node but using a different PDK or foundry, or designs on a different process node – usually smaller. However, achieving effective IP reuse has always been a challenge.

Digital designs are often expressed in an HDL such as Verilog or VHDL. Because of the design flow used for HDL based designs, recreating gate level representations targeted at different libraries and process nodes is manageable. However, when it comes to AMS, full custom or RF designs, porting to new technologies becomes a much more difficult proposition.

These designs are most often represented with schematics. When switching to a new PDK, designers will need to convert the schematic so that it uses the cells available in the new library. Not only can the cell/symbol name change but there will be changes in the number and names of the pins, and more fundamentally there will be changes in design parameters that determine circuit performance. Probably no design task is more tedious and risky than manually porting a schematic.

I’ve written previously about MunEDA’s circuit optimization software, but they also have expertise in schematic porting. According to MunEDA, the challenges of schematic migration are:

  • Different device parameters (vth, etc.) require adjustment of biasing and small signal parameters
  • Needed W, L shrinking is not as simple as digital
  • Some devices (mimcaps, inductors, etc.) may or may not be available, or may be of a different type
  • Circuit topology may need modification
  • Layout shrinking in integrated technologies is insufficient

MunEDA suggests a 3 step process starting with updating the schematic with the new library symbols. As previously mentioned this is complicated by new symbol names, potentially different number of pins, and changes in parameter names. MunEDA offers their Schematic Porting Tool (SPT) that can significantly automate this process.

Once the symbol mapping information is entered for the two libraries, MunEDA SPT can replace 100’s or 1,000’s of symbols in seconds. MunEDA’s SPT is fully integrated into Cadence Virtuoso based custom and analog design flows. This includes properly handling SKILL context files, wrapper scripts and configuration scripts. The error prone manual alternative would take orders of magnitude longer. Here are some examples of the operations that SPT can perform.

The second step of the MunEDA flow involves assessment and topology changes in the schematic to accommodate the new PDK. Any desired topology changes can be made at this point to accommodate the new library. Once this is done, the design is ready for automated sizing and optimization.

The last and most important step is modification of the design parameters so the circuit operates properly. MunEDA SPT lets users create their own sizing strategy. It also supports multi-objective optimization, including power and noise minimization. Sizing can also can be done over multiple process corners.

The MunEDA website offers several papers on use of SPT by their customers, including examples submitted by the University of Dresden, STARC, Evatronix and others. Look here for the specifics.

Despite the usual difficulty automating custom, analog and RF design steps, it’s good to know there are options for dramatically improving the process of porting schematics to new PDK’s. MunEDA is able to do this by building on their clearly established expertise in custom circuit design optimization.

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"Night Gathers, and Now My Watch Begins"

"Night Gathers, and Now My Watch Begins"
by Paul McLellan on 09-08-2015 at 7:00 am
Categories: IoT, Mobile

What is going on in the watch world? And I don’t mean Game of Thrones‘ nights watch.

Lots, actually. Whether it will amount to a lot remains to be seen. I still think the usefulness versus the price isn’t there yet. Apple has sold 3.5M iWatches (or something close) which for anyone else would count as a runaway success but for them counts as lackluster. Even in silicon valley you don’t see iWatches on everyone’s wrists so I expect they are rare in middle America. Apple has a big event later this week on the 9th and it is possible that a new watch will be announced. But everyone else is rushing out new watches too since it is the IFA consumer electronics show this week in Berlin, . Here are some of them.

Caveat lector: I haven’t used any of these watches except the Pebble, I’m just doing the Semiwiki thing of following the industry so you don’t have to.

The Samsung Gear S2: This gets great reviews since it is light, the weight of a normal watch. It displays the time constantly, just like one of those old mechanical things that I suppose are dumb watches. It has rotating bezel which is how you control it. It has integrated 3G radio (so you don’t need to pair it with a phone, Samsung or otherwise). You can order Uber from your watch, for example.

Huawei Smartwatch: Available for pre-order and shipping September 17th with prices from $349 to $799 (there are 6 models). Another watch that looks like a watch with real hands. I’ve not seen any report by anyone who has used one, everyone seems to be just reporting on the press releases. Huawei is usually strongest in the China market but I find it hard to believe that the sort of people who have made Xiaomi #1 there are going to be buying a $799 watch at several times the price of their phone. A few technical specs:a 300mAh battery that promises to deliver up to two days of battery life. It also sports 4GB of internal memory, 512MB RAM, Android Wear 1.3, a built-in microphone, six-axis motion sensor and heart rate sensor.

LG Smartwatch: LG don’t even call it a smartwatch, they call it a “smartpiece”. A few specs: Android Wear running on a 1.2GHz quad-core Snapdragon 400 processor and 512MB of RAM, with a 1.3-inch P-OLED circular display with a 320 x 320 resolution and a 410 mAh.But if you really want to be ostentatious, it is available as the 23-karat gold Urbane Luxe, which will be priced at $1,200.

Sony Smartwatch: Only available in Japan for now. One reason is that its NFC payment interface only supports Japan. May eventually be available here but the one shown at IFA won’t even be available in Japan until March 2016. The intelligence is in the bracelet, not just the watch itself. Definitely at the vanguard of smartwatches that are trying to look like non-smartwatches, which at glance at most of the pictures here seems to be the current approach.

The latest version of one of the first smartwatches, the Kickstarter funded Pebble: unlike most watches, only buttons control the Pebble (no touch-screen). 5 day battery life. Cheaper and more utilitarian than most of the other watches here that are a cross between expensive jewellery and cool electronics.

Android Wear now works with the iPhone. I’ve not tried it but according to thisreview, don’t bother:The ability to pair an Android watch with an Apple phone is conceptually interesting but functionally, it’s a lose-lose proposition. Android Wear watches can’t do most of the things they can do when paired with Android phones, and your iPhone can’t be extended through an Android watch the way it can with the Apple Watch. It’s an experiment that may yield results one day, but that day isn’t today.

I still think watches are awaiting a killer app. If they could continuously monitor blood pressure, say, then I think they would fly off the shelves. But just moving notifications from your phone to your wrist and even being able to take calls doesn’t seem enough. I own a Pebble but I don’t bother to wear it. Given that I already paid for it, finding it useful enough to wear is a pretty low bar to clear.

“And now his watch has ended.”

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M&A Frenzy in the Chip Industry, the Growth of GaN, and Why It Matters

M&A Frenzy in the Chip Industry, the Growth of GaN, and Why It Matters
by Alex Lidow on 09-07-2015 at 12:00 pm
Categories: EDA

If expanding industries typically indicate vibrancy, a race to acquire and consolidate is generally reflective of the opposite – a period of slowed growth in mature, once high-flying categories. And while many industries experience a period of stardom, followed by a sharp and steady decline, we should be extremely worried when they occur in industries that are fundamentally central to our socio-economic vitality.

Enter the semiconductor industry, where in the past 24 months, there have been at least 10 significant mergers and acquisitions, including big name brands such as Avago’s acquisition of Broadcom, Intel’s purchase of Altera, and Infineon’s acquisition of International Rectifier .

Further, since the year 2000, the semiconductor industry as a whole has grown at a mere 5% annually, as compared with 22% in the 1980s (see figure 1). The semiconductor “go-go years” of the 80s have been replaced by the more sedate, incremental growth rate of a mature industry – with fewer and fewer bright lights from product innovation. But does a shrinking semiconductor industry indicate bigger problems for the technology industry as a whole?

End of Moore’s Law
It is not a coincidence that this race to consolidate has coincided with the end of Moore’s Law as we know it. Moore’s Law depends upon the continuous reduction in the size of a transistor to maintain positive momentum in both cost and performance. Today, the realization of this bold prediction made 50-years ago has become an either/or proposition – either deliver on better performance or a lower price.

The problem began to rear its ugly head about twenty years ago: as the size of transistors continued to shrink, the cost to produce them got bigger. Other costs, such as designing, packaging and testing have also escalated, and the overall bill to develop an advanced silicon-based device – now in the 10’s to 100’s of millions of dollars – has become unaffordable to all but the well-funded, established companies.

Why It Matters
New chips are the fuel for the semiconductor industry’s growth, and, as the costs escalate, the number of new semiconductors (and their innovation contribution) decreases. But it’s not just the chip companies that stand to lose from this new reality. Industry luminaries predict that the sputtering of Moore’s Law will likely hinder the innovation and advancement to which we have all become accustomed,putting in peril many of the devices and applications that businesses and consumers covet, including virtual reality glasses, wireless power, autonomous vehicles, 5G mobile communications and advanced medical devices to name a few.

The de-coupling of cost and performance is due to three underlying trends for silicon chips; (1) the slower growth in end markets for semiconductors in general, (2) the cost to develop a new chip, and (3) the capital investments needed to build factories to produce each new generation of product.

Knowing this, it becomes clear why there has been so much consolidation in the chip industry lately: for many of the large semiconductor players, it’s simply less risky to buy existing revenues than to invest in new products and factories to develop and introduce new products. The total market size of the industry “pie” is relatively fixed, so organic growth from technological innovation is high-risk, in addition to being very costly.

The original wellspring of innovation – the venture-funded startup in the chip space has all but disappeared, as there is little venture money available given the poor cost-to-risk ratio for new product development and the less vibrant growth prospects.

Unfortunately, this is not good news for consumers as startups are often the source of the technology industry’s greatest innovations. Given these metrics, advancements in the semiconductor industry will continue slowly, putting us farther and farther behind on the promise of Moore’s Law.

A Glimmer of Light – the Growth of #GaN
Some exceptions can be found, however. Alternatives to silicon, such as gallium nitride (GaN) and silicon carbide (SiC) offer the potential for a refreshing return to the financial metrics the semiconductor industry enjoyed in the 1970s and 1980s. GaN in particular, is facing a period of rapid growth. This growth is coming from both the replacement of lower performing silicon devices and from emerging applications that are enabled by GaN’s superior performance. These applications – from those that make our lives more convenient to those that have life-altering impacts – are critical for the technological advancement to which we have become accustomed.

Given worrisome events of the last two years, I say it’s time for the semiconductor industry and the venture community to come together to rally around innovation – not consolidation. With that in mind, we will be able to fuel product development and propel advancement at the speeds to which Gordon Moore predicted just five decades ago.

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Semiconductor Usage Revolves Around Asia

Semiconductor Usage Revolves Around Asia
by Pawan Fangaria on 09-07-2015 at 7:00 am
Categories: EDA, Foundries, IoT, IP, Mobile

I just read Daniel Nenni’s blog titled “Is Silicon Valley Gridlock a Good Sign for Semiconductors?” Dan, there is no definitive answer to this, I mean in terms of semiconductors. Let me call it Semiconductor Gridlock in Silicon Valley. Yes it’s good because Silicon Valley promotes research, brings up innovative technology and products, demonstrates to the world the use of those products by consuming those in Silicon Valley and USA, and then scales the production to make it affordable by the masses. Of course during scaling of production multiple players across the world join the game to further innovate, scale, adopt and make that technology or products ubiquitous across the world. And no, the Semiconductors cannot remain gridlocked into Silicon Valley forever. Smartphones are saturated in USA. Now, it’s time for other regions to manufacture Smartphones and consume for themselves. Similar is the scenario for other semiconductor products. I get my conviction towards this when I see a recent chart on IC usage across the world, published by IC Insights.


This clearly shows Asia-Pac region leading the pack with 58.9% of total IC sales across the world. If you look at the specific categories, the Asia-Pac region has largest share in communications; 24.2% out of a total of 38.3% sales in that category, arguably. The communications segment is followed by the computer segment with 22.4% sales in Asia-Pac region out of a total of 35.6% sale in that category, which is understandable why. Europe leads in the auto segment by a very narrow margin compared to Asia-Pac; that margin is expected to vanish going forward, once Chinese economy improves. The categories which are purely semiconductor driven, i.e. computer and communication, have the combined maximum share at 73.9% of total IC sales. And sales in these categories are heavily dominated by the Asia-Pac region this year.

Although, the chart shows it region wise, in my analysis I am seeing it according to human population in different regions. Out of more than 7 billion people around the world, the Americas have ~4.45%, Europe has slightly more than 10%, Japan has the least ~1.75%, and Asia-Pac has the largest ~55% of world population.

Now connect this with the semiconductor sales; Asia-Pac has the maximum semiconductor sales at 58.9% and Japan has minimum at 7.8%. Interestingly, Americas with 4.45% population contribute much more (22.9%) in semiconductor sales compared to Europe (10.4%) with a population more than 10%. This can be attributed to the effect of America being the initiator and consumption leader in the first place. We can also attribute it to the current financial crisis in Europe. However, the key point I see here is – as things become affordable, they start moving to more populous regions who can afford. Isn’t that the reason, why Xiaomi is entering PC/notebook segment even though that segment is expected to be in decline for next 2 years?

The 30+ years of semiconductors have given enough know-how, affordability, and consumption appetite to many regions around the world, even Africa to start with consumption. Today, Asia-Pac appears self sufficient in manufacturing and specifically dominating in consumption. Within Asia-Pac, China has more than 19% population and India has ~17.5% population. While China already has strong manufacturing, India has to catch up in manufacturing. India’s “Make in India” program is promoting foreign companies to start manufacturing in India, i.e. where the consumption is. There has been good progress – last month Intel opened its Maker Lab in India to provide innovation infrastructure around IoT (Internet of Things) to start-ups; several Smartphone companies including Samsung, Xiaomi, Lava, Karbonn, and others have started manufacturing base in India.

In my view, Asia-Pac region will continue to dominate in semiconductor sales for couple of years until any significant new break-through happens elsewhere in the world.

The IC Insights chart can be referred here.
Also read Daniel Nenni’s blog here.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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Improve SoC Front-end Design Productivity

Improve SoC Front-end Design Productivity
by Khan Kibria on 09-06-2015 at 4:00 pm
Categories: EDA

I have been involved in SoC developments for a long time. During this period I tried to learn what impacts the productivity and subsequently the market opportunity. Over the last year or so at SoCScape I have been involved designing solutions that can improve them. I have decided to post some of my thoughts here in a series of blogs from this experience and effort. I hope you participate and enlighten me on this topic more by providing your comments below.

Integrated circuits have been packing larger functionality due to tighter geometry to reduce total system cost. However, design cost for large chips is on the rise. There are multiple elements contributing to the cost to consider. I am not talking about the cost of simulation or synthesis of complex functionality here. Those are addressed by the multitude of -constantly improving EDA products and methodologies. I am addressing cost of preparing the RTL before hand-off.

The following three issues stand out the most:

Complexity
Cost due to the inherent complexity of functionality. It takes time to put them together in an SoC. Delivering the complete RTL to the simulation and synthesis team in a consistent manner is non trivial.

Lack of uniformity
The building blocks, commonly termed as intellectual properties (IPs), may come from different sources. These IPs are typically reused over multiple chips. The style, naming convention etc. are different depending on where they come from. The lack of uniformity in situations like this can increase resource needs and have a negative impact on cost.

Change in requirement
Today’s design practices present requirement changes based on market demand a few times through its life cycle. Adjusting to these changes incur cost since time to market often has a significant impact on product revenue.

A solution that controls cost by improving productivity in these areas is my primary interest. After all, experience suggests that SoCs are not becoming simpler and smaller! We need to make chips to make money without letting the market opportunity slide away. A great SoC delivered late to the market does not yield its full revenue potential.

Complexity
I would like to give a brief historical perspective. Remember when hardware description languages (HDL) were introduced? When HDLs were in their infancy, many designers were reluctant to adopt HDL because of the absence of robust synthesis tools. Although digital design at gate level was tedious, chips were simpler. It was still fun to craft new functions with gates. But then the complexity made gate level more mechanical and therefore the creative fun was not at the gate level any more. I started coding chips with Verilog and VHDL. Both have their great features and pains, but it started becoming fun to code at RTL level. I could cater to my creative side and I also got immediate productivity boost.

History is repeating itself again! I am encountering many proponents of high level synthesis (HLS) these days. This is a good thing. With HLS, designing logic that produces high level complex functions will not be as tedious.

So how does the complexity of today impact the designers?

Lots of signals to connect
I mean a lot! They are traversing up and down through the hierarchy. Hooking them up individually is error prone and time consuming. This is where the protocol based connections can help. So what is a protocol based connection?

They behave much like cables. They contain a collection of functionally related wires. When you connect them to a connector they all get connected at the same time, no need to connect them individually. Moreover, you cannot take one type of cable and connect it to another type of connector. Of course I am purposely ignoring the case where someone tries to use pure brute force!

It is possible to use HDL to apply such a paradigm. A VHDL record aggregates a collection of signals. A System Verilog struct also provides similar facilities. HLS methodology supports this paradigm as well.

However, in any given SoC or a chip design, we may have a number of IP. One could be designed using a different HDL than the next. The front-end designer of an SoC or chip has to deal with this mixed bag and that is where it starts becoming tedious. Fortunately, this is where automation comes to the rescue. To take advantage of the automation, an IP needs to provide meta-data describing all the protocol based connections. An EDA tool can use the information and connect everything on behalf of the designer. This type of automation presents a huge opportunity to improve productivity and reduce manual error.

The IP-XACT (IEEE 1685) standard provides an XML format to describe the meta-data. There are a growing number of EDA vendors providing support for IP-XACT. As a result, an increasing number of IP vendors are also delivering IP-XACT files with their IPs.

IP-XACT format is quite comprehensive and elaborate. It addresses a broad spectrum of needs above and beyond the protocol based connections. The XML format is intended to facilitate machine reading. Manually producing the IP-XACT files are not practical.

As a result, a particular EDA tool may support one or more additional mechanisms such as human readable meta-data description language, simpler meta-data format, APIs, or graphical user interface. These additional mechanisms allow the user to provide the meta-data for an IP that lacks a preexisting IP-XACT file. A designer should evaluate an EDA tool based on the simplicity of its additional mechanisms. Simplicity is a powerful contributor towards productivity.

Creation of glue logic
Designers will need to provide glue logic that realizes a multitude of functions while they are bolting the IPs to their SoC or chip. They spend quite a bit of time on the glue logic. This is what makes the SoC act as a single cohesive entity. Typically these are small pieces of logic, but they could be large as well. Complexity in SoC design increases the number of these pieces. Automation can improve productivity here too by introducing division of labor.

An EDA tool for this purpose should be able to provide facilities for the designer to dynamically introduce glue logic blobs inside different areas of an SoC as the designer needs. These blobs should not contain any actual logic. They simply should provide a placeholder for the designer’s need so that he can focus on integrating the rest of the IPs. The EDA tool should permit one to come back to these blobs and add logic later. This will allow us to take advantage of divide and conquer strategy. You can employ multiple designers to parallel process the task, some defining and creating the blobs while others filling up the blobs with actual logic.

Chip specific customized IP
There are quite a few pieces in an SoC which are to be customized per SoC basis. Clock/power management is a great example. It is indeed very complex in nature. There are other pieces such as padring, design for test (DFT) logic, etc. which also fall under customized IP category.

These pieces are challenging since change in SoC design impact them quite a bit. Additionally, their role also continue to evolve over time in terms of how they handle their designated tasks.

This is actually an interesting topic, which deserves its own space. I will go over this topic in my next post. Stay tuned! I appreciate you providing feedback, which allows me to refine my thoughts. Cheers!