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July 15, 2015

Internet of Things Bubble?

Internet of Things Bubble?
by Bill Jewell on 07-15-2015 at 10:00 pm
Categories: IoT

Speaking at the World Business Forum in Sydney, Australia in May, Steve Wonziak (cofounder of Apple) said about the Internet of Things : “I feel it’s kind of like a bubble, because there is a pace at which human beings can change the way they do things. There are tons of companies starting up.” According to market research firm Gartner, the Internet of Things (IoT) is “the network of physical objects that contain embedded technology to communicate and sense or interact with their internal states or the external environment.”

The obvious comparison to a potential IoT bubble is the Internet bubble in the 1990s. The bursting of the Internet bubble in 2000 put many marginal companies out of business and led to major declines in the stock market value of all Internet related companies. However it did not change the inevitable trend of the Internet becoming pervasive in our lives. The same is probably true of IoT. Some companies and technologies are overhyped and could crash and burn in a market correction. However the trend is inevitable – devices will increasingly communicate with the Internet, many without any human interaction.

How big will IoT be in the next few years? There is surprising agreement among forecasters.

The consulting and market research firms are closer in their projections for 2019-2020 (23 billion to 30 billion unit installed base) than they are in their estimates of 2014 (3 billion to 10 billion). My theorem about high technology markets is the forecasters are always closer to each other than they are to the final reality. This is not surprising since the companies are operating with the same general set of assumptions. Unforeseen events often drive the market higher or lower than the consensus forecast.

The IoT is made up of numerous devices across many applications. The media focuses on consumer purchased devices such as wearables and connected home devices. The hype was obvious at International CES 2015 in January. The top two categories for exhibitor press releases were wearables and connected home.

However most of the IoT is driven by business and government. Business Insider estimates in 2019 about 74% of the IoT installed base will be business and government applications and about 26% will be consumer applications. IDC expects digital signage will be the biggest IoT growth driver in 2015. Businesses and government can usually justify IoT investment with eventual cost savings. A utility company can rationalize the cost of installing smart electric meters at their customer sites will pay off with the savings in not sending human meter readers to each location every month.

Consumer IoT applications will continue to command most of the media attention. Business Insider project about one-third of the 6 billion unit IoT installed base among consumers will be connected home devices, including energy, security and appliances. Another key consumer IoT driver is wearable devices which can monitor health, fitness and activity. They can also be an interface to a smartphone. Wearable devices are primarily worn on the wrist – including smart watches and bands.

Prognosticators are also remarkably close in their projections for the wearable device market in four years. Estimates of the 2019 wearable device market are in a narrow range of 145 to 156 million units.

[TABLE] align=”center” border=”1″ style=”width: 527px”
|-
| colspan=”2″ style=”width: 421px; height: 15px; text-align: center” | Global Wearable Device Market, Millions of Units
|-
| style=”width: 289px; height: 16px” |
| style=”width: 131px; height: 16px; text-align: center” | 2019
|-
| style=”width: 289px; height: 15px” | Analysis Mason, Sep. 2014
| style=”width: 131px; height: 15px; text-align: center” | 145
|-
| style=”width: 289px; height: 15px” | Business Insider, May 2015
| style=”width: 131px; height: 15px; text-align: center” | 148
|-
| style=”width: 289px; height: 16px” | IDC, June 2015
| style=”width: 131px; height: 16px; text-align: center” | 156
|-

Two high profile wearable devices are the Apple Watch, launched on April 24, and the Fitbit Charge HR, launched on January 6 at CES. Fitbit is the global leader in wearable devices, with 34% share in first quarter 2015 according to IDC. The Apple Watch is being “watched” closely due to Apple’s success in redefining markets with its iPad and iPhone. Slice Intelligence estimates 3 million Apple watches were sold online in the U.S. in the three months from April 10 (the first day of pre-orders) through July 10. Slice Intelligence estimated Fitbit sold 850 thousand total devices in U.S. online sales in May, beating Apple Watch sales of 777 thousand devices. Apple Watch is expected to be a major factor in total year 2015 wearable devices sales, with estimated share of to 27% (CCS Insight) to 40% (Business Insider).

How will wearables affect the semiconductor market? IHS estimated the costs of the components in an Apple Watch Sport at $81. We at semiconductor Intelligence estimate the semiconductor portion of the cost at $50, 14% of the watch retail price of $349. IHS estimated the component costs of an iPhone 6 at $196. We estimate semiconductor content at $130 for the iPhone 6, 20% of the retail price of the phone.

Below are IDC’s recent projections of unit shipments of PCs, tablets/2-in1 devices, smartphones and wearables for 2019 compared to 2014. Smartphones will continue as the dominant device people use to connect to the Internet, with an expected 1.9 billion units shipped worldwide in 2019. The combined total for PCs and tablets in 2019 is 563 million units, a slight increase from 539 million in 2014. Wearable devices are forecast to show six-fold growth from 26 million units in 2014 to 156 million in 2019. Even with the strong growth, wearables shipments will be less than one-tenth of smartphones in 2019 and less than either PCs or tablets. The semiconductor content of wearables per device will continue to be significantly less than in the other devices.

Earlier this month Gartner forecast wearable devices will account for only one percent of the semiconductor market in 2019. The total IoT semiconductor market will be more significant, with Gartner data showing it could account for eight percent of the semiconductor market in 2019.

The Internet of Things may not be the “Next Big Thing” to drive the semiconductor market, but it does represent a meaningful growth opportunity. The key semiconductor products in IoT devices are sensors, microcontrollers, processors and communication & connectivity devices. IoT devices will also drive a market for systems and infrastructure to support the devices. If there is an IoT bubble, it is more likely to slowly deflate than burst. Many companies currently focusing on IoT will go out of business, but the remaining companies will have an opportunity to profit from a strong growth market.

July 15, 2015June 14, 2019

How Emulation Enables Complex Power Intent Modeling

How Emulation Enables Complex Power Intent Modeling
by Pawan Fangaria on 07-15-2015 at 12:00 pm
Categories: Cadence, EDA

As the number of CPU, GPU, and IP is growing in an SoC, power management is becoming more and more a complex task in itself. A single tool or methodology may not be enough for complete power management and verification of an SoC. In an SoC, there can be multiple modes of operations involving hardware and software interactions, different applications running, and complex dynamic power profiles of those applications. One key aspect is power intent modelling and verification. The power intent is described in CPF (Common Power Format) or UPF (Unified Power Format) files. The design has to honour the rules described in these files and work properly even when certain parts of the design are inactive or in sleep mode.

Broadly speaking, the UPF files contain descriptions about components such as switches, level shifters, isolation cells, and retention cells. These files can be best used by different verification tools including simulation and emulation under different situations. Emulation has been a unique verification method for real world testing. AMDhas been using In-Circuit Emulation (ICE) for its GPU (Graphics Processing Unit) and APU (AMD Accelerated Processing Unit) power modelling and verification. GPU is a simpler case in which the GPU resides inside Cadence’sPalladium system and is divided into multiple power domains. A test PC is connected to the GPU through a PCIe speed-bridge. The test PC is also connected to a debug PC through fire-wire. The switching of power domains is dynamically controlled by hardware and software. The main purpose is to keep the Power dissipation of the overall GPU low. The APU is more complex than GPU; an example is below.

Inside the emulator, the power domains are shown in orange color. There are many power domains in the Graphics & Multimedia Engine and other units which need extensive power management with many complex power scenarios to test. There are multiple CPU cores. There is a separate CPU for system management and security. There are power safe operations in I/O subsystem and system management units which need to be unified. The Operating System (OS) and test system are on a separate hard disk sitting outside the emulator and connected with it through SATA speed-bridge.

In such a scenario emulation is the most powerful method to test the APU in real world with real use-cases. The application and OS level testing is nearly impossible with the usual simulation method. Dynamic Frequency and Voltage Scaling (DFVS) is a powerful technique to reduce power dissipation by independently scaling frequency and voltage in each power domain. However it requires a significantly complex system management, because in larger and faster chips there can be multiple clock domains to propagate clock signals across the chips. Such a system can be best tested with emulation in real life scenario for best accuracy.

AMD uses UPF 2.0 with all construct level support and the latest UPF 2.1 with semantic level support in Palladium emulation system. Memory scrambling test has been automated with UPF directives which describe about the power domain where the scrambling takes place. With waveform support for objects one can see the states of power related objects. With SDL trigger support in UPF, Palladium can create dynamic triggers on any power related object in the design to put it on or off. This is a unique and powerful feature for power safe transitions.

AMD has a very balanced approach of selecting tests which needs to be run on simulation or emulation. Usually, long running directed tests and those that do not require complex testbench interaction are run on UPF enabled emulation. The pre-silicon emulation workloads comprise power management, BIOS, firmware, OS, and application level workloads. In emulation multiple passes of power sequences can be done as against a single pass in simulation. This enables complex interaction scenarios and repeated power state entry or exit with variable external stimulus.

The APU based testbench can be simplified by connecting a system model with the design in the Palladium system through transactors.

The system model can be in C++. The executing code communicates with the system model where a power event request can be sent to the system model and the system model responds accordingly. This scheme is configurable and aligns uniquely with AMD’s RTL simulation methodology.

This emulation methodology at AMD has proved to be very effective reducing long simulation runtimes drastically. Complex SoC power interactions and closer to real life workloads can be possible through emulation. The runtime failures can be detected through self checking stimulus and power based assertions instrumented into the emulation build.

Alex Starr from AMD presented in detail about this methodology at 52[SUP]nd[/SUP] DAC. The same presentation has been posted HERE with the title “Experiences with SoC Deployment of Hardware Emulation Based Power Intent Modeling”. There is no registration required.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

July 15, 2015

SEMICON Day 3: Leti, Intel Keynote, 450mm (Pic!) and Innovation Keynote

SEMICON Day 3: Leti, Intel Keynote, 450mm (Pic!) and Innovation Keynote
by Paul McLellan on 07-15-2015 at 11:59 am
Categories: ESD Alliance, Semiconductor Services

Let’s start with yesterday evening, so technically yesterday. It was July 14th, which is the equivalent of Independence Day in France. So the perfect day for Leti, based in Grenoble, to present a lot of the work that they are doing on 3D “more than Moore” type technologies, including photonics. Also, wafer-scale LED lighting. And some need micro tomography for looking at things like a single transistor or a single copper pillar.

I’ve lived in France and worked on European projects so I’ve always been a bit skeptical of these sort of funded research programs where the results are PhD theses and a lot of the funding seems to be vacuumed up by large companies. But Leti seems to aggressively move stuff out into startups when the technology looks viable. For example, the wafer scale LED lighting is going into production in 2016. Some of the 3D technology looks promising too, such as the CoolCube which is looking at some of the right issues namely how to build up vertically in a way that keeps the temperature low. One of the issues with semiconductor manufacture is that you need diffusion ovens in the FEOL and they are too hot for the metal stack in the BEOL.

Anyway, onto today. Doug Davis of Intel gave the keynote. He is the GM for IoT (which I was interested to hear includes Wind River which, in turn, includes Virtutech where I used to work. I guess if I’d stayed I’d be a “thing” too). His thesis is that the Internet of Things is a disruptive force. I’ve no doubt it is, and he quoted the 50B things by 2020 number. But as I discussed on Day 1, it is a high volume market where it is not clear the component suppliers make the money. When stuff gets up into the cloud, then obviously Intel has a play since they make a lot of money in the datacenter.

Doug started talking about a Swedish company Yanzi creating smart offices. Sensors on wastebins to know the are fill, washroom towels and soap, copier paper and toner. Cute, but not exactly that disruptive. He then moved onto four areas where he though there was lots of scope:

aging population: turning the home into a connected care center so that old people can age in place (by 2050 then 40% of us will be over 60)
environment: I think he cheated here since the example he used was improving an Intel factory in Malaysia by detecting imminent issues, reducing maintenance by 50% and spare parts by 20%
urban boom: which mostly means China and Asia since 46 of the worlds biggest cities in 2015 will be in China, and half in Asia. They have pilot programs going in London.
feed the planet: we waste a lot of food so we have enough, in fact agricultural productivity is rising faster than the population. His example was a program (using the much-mentioed “Intel IoT Gateway”) to automate water feed to Malaysian rice paddies which ended up saving 10% of water but, more significantly, increased production by 50% from 2 harvests per year to 3

Interestingly two of those, medical and agriculture, were ones that ARM called out two days ago as areas ripe for disruption by technology (and computer vision will probably be involved in some of these other areas too).

I can see how the service supplier and the system integrators make money. I still don’t see how a company like Intel makes serious money on low-margin products. Especially Intel, who have to keep their margins high because that’s what they do. They are not Atmel. I know they have smaller processors and stuff these days, like Quark, and Doug even showed us a module called Curie the size of a dime (incidentally, as he pointed out, the cost a car would be if they had obeyed Moore’s Law pricing for the last 50 years. They’d go fast too. Insert your own “blue screen of death” joke here).

Next was the annual G450C update. Three people presented and I may have their names wrong since they were not on any slides and the presentation was billed to be by someone else. Chris Borst, who is the fab operations director of the 450mm fab at SUNY, CC Chen, from TSMC, and Erin Fria of Intel.

Current status:

Excellent test results with 51 tools installed in Albany
The Nikon scanner arrived (previous scanning was done in Japan at Nikon)
Notchless wafers with 1.5mm edge is the SEMI standard
All partners are supporting equipment in NY through Q1 2017
40nm and 28nm process
73 wafers patterned to date

So bottom line:

>30% die cost advantage
Everything is still viable
HVM 1.5 to 2 years from the “go” signal, ready for intercept with 300mm at end of decade, currently targeting 10nm insertion

Proof: me holding a fully patterned copper BEOL flow (just one layer of metal for sure) 450mm notchless wafer!

So now the question is whether it truly makes sense from a business perspective. I don’t know how the 30% die cost advantage above was derived and what it assumes about the cost of all the equipment.

Next meeting was with Gary Patton and Subi Kengeri of GlobalFoundries about 22nm FD-SOI, including the schedule, PDK availability. I went to GlobalFoundries panel session coming on the 22nm FD-SOI ecosystem so I’ll blog about both of these together later, in a separate blog. Look for that Friday morning.

So last thing of the day was the end-of-event keynote for the Innovation Forum. It was by Steven Forrest of University of Michingan on Moving Innovation from the Lab to the Marketplace: the Critital Role of Academia in the Innovation Chain. He said the first part was 1000 things academics could do wrong and about 3 they could do right. He was at Bell Labs, where he invented the photodetector now found at the end of every fiber optic line in the world. Then he and his students invented the AMOLED (which is apparently 100% efficient due to some quantum effect so perfect for lighting once they get costs down) and more. Factoid he knows as a result: Samsung Galaxy phones are the most-owned electronic gadgets ever at 750M.

Issue #1 he said universities need to deal with is that they all have offices of technology transfer who think they are judged by how many royalties they bring in. Companies hate that attitude and run away. He told them that the only thing he cared about was how much technology got transferred. The royalties would take care of themselves.

In the US we have it lucky. The VC’s attitude to failure is “someone else paid for your lesson.” In the rest of the world it is (largely) not like that. But we have a huge political immigration problem (and I don’t mean illegal immigrants) because it turns out that most startups are started by immigrants. I remember my own experience a few years ago where I worked for a startup (that the board eventually gave me to run but that is another story) with an Israeli CEO and an Iranian CTO. That doesn’t happen in most of the world.

So what are his recommendations?

Building a company is done brick by brick, no shorcuts
Be prepared to “slay dragons”, they multiply fast
Use every resource, “doing it yourself” usually leads to disaster
Don’t worry about an exit strategy
Nobody’s technology is good enough to be “ahead of its time”
Inventors (professors) make lousy CEOs. Pick a single career
Hard lesson: companies and their founders’ interests eventually diverge so exit as gracefully as possible

He also studied Israel (also famous for innovation) and the US and looked at the challenges of those two ecosystems of innovation. I leave you with that slide. It’s been a long day.

Final conclusion, in the large post-industrial lab (think Bell Labs or Xerox PARC) post-Moore’s Law era, universities and governments have a shared destiny in the “globalized world of science.” We can’t succeed without each other.

This has been an experiment today. I have blogged each event immediately after it happened. Did anyone read any of it? Was it a good idea? Answers in the comments.

July 15, 2015

SEMICON Day 2: Outlook and Keynote Panel

SEMICON Day 2: Outlook and Keynote Panel
by Paul McLellan on 07-15-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

The second day of SEMICON West opened with a press conference. Since it was at 7.30 in the morning we all needed the coffee that they provided. For those of us that remember the glory days of DAC some of the statistics were depressing:

45th year (hey, we got them beat on at least one statistic)
692 exhibitors
136 new exhibitors (about the same as DAC total exhibitors this year)
1,220 booths

The show fills both halves of Moscone and the areas in between and has a colocated solar show that fills Moscone West.

The press conference always updates the 2015 semiconductor outlook. Currently semiconductor growth estimates from the various people who make them go from 8.0% (Semico Research, Semiconductor Intelligence) down to 3.4%. But everyone is fast bringing them down due to instability in the EU, weakening in the Chinese market, and the weaker yen (that affects forecasts made in dollars). So far this year silicon shipments are, indeed, up 8% year-on-year but that is slowing.

The SEMI forecast press release is here.

SEMI forecasts mostly for the equipment industry (SEMI actually is not just the first 4 letters of semiconductor but stands for Semiconductor Equipment and Materials International), although obviously a major input into how much equipment will be purchased is how much acreage of semiconductor will be built.

The numbers are all over the place. Jan to May this year versus last shows Europe up 17%, Japan up 50% (wow), North America down 22%, Korea up 23%, Taiwan down 26% and China down 20%. The weakness of the Japanese Yen (and the Euro) feed negatively into these numbers. Interesting there is a lot of ramping of 200mm capacity this year and next and, at least anectodally, used 200mm equipment pricing has firmed. SEMI is predicting 3 years of growth (although since of of those years is 2014 I’m not sure it counts as a prediction.

Then the show opened with a keynote panel about the challenges of getting to sub-14nm. It was moderated by Jo De Boeck of imec, Mike Campbell of Qualcomm, Shubhashish Mitra of Stanford, Calvin Cheung of ASE and Gary Patton. The events guide lists him as being at IBM but he is now the CTO of GlobalFoundries.

Gary reiterated what I’ve heard many others say. He is not afraid of the technical challenges of going to the next node, he is sure we will find ways to do that. The challenge is to keep the costs under control. He said he has 10nm and 7nm teams in Malta (New York). Since it is now not possible to get 35-40% cost reduction per transistor anymore there needs to be a focus on how to add more value: RF front-end modules, 3D and 2.5D technologies, and things like Micron’s HMC (where IBM made the logic slice).

Mike of Qualcomm said that it is necessary to take a more system approach and worry about system yield percentage. One challenge is changes due to stress when building 3D designs in tiny packages which affects yield and reliability. He also threw out a statistic that it takes 12-26 weeks to run the verification vectors prior to tapeout.

Shubhashish said similar things, pointing out that to get things like serious power reduction you have to start from computer architecture, system architecture, packaging. Get it all into a tiny space. It is not just the 7nm or 5nm transistor.

In fact there was general agreement that debugging issues and reducing variation (in the most general of senses) to reduce them occurring was really important. Especially with time to market constraints. There is no yield model across the while chain. In big systems it can be almost impossible to discover which chip is failing.

Calvin said that introducing a new packaging product would take 12-18 months and then a 6-month yield ramp. In the old days they would ramp just a few thousand so if they were bad the cost was manageable. Now a Qualcomm chip ramps instantly to millions. A missing piece of the puzzle is that in semiconductor there is a test key in the scribe so many problems can be detected in real time once they are introduced. There needs to be something for assembly since with ramps, millions of parts are lost if something is systematically wrong. With a new node every 12 months this is a huge problem for the OSATs.

Gary said they use PDF solutions to keep track of systematic yield detractors such as contact that never prints. There is nothing like that for assembly. Even with the front end all the tools speak different languages making it too hard to use data mining.

Jo finished by asking them their dreams:

Shubhashish: 1000X increase in energy efficiency, improved component technologies such as carbon nanobubes
Mike: 7nm in volume yielding with the same defects/cm2 as 28nm and the same production ramp. Debug too long
Gary wanted a brain. Or components like a brain, low power, resilient, redundant etc
I missed what Calvin said. He probably would like the luxury of slower ramps!

Oh, and at lunch I saw a 22nm FD-SOI wafer at the SOITEC lunch. Only a blank one (it has the insulating box etc all done though), maybe I get to see a real one when I meet GlobalFoundries tomorrow.

July 15, 2015June 14, 2019

Benefits of RTL Power Budgeting

Benefits of RTL Power Budgeting
by Daniel Payne on 07-15-2015 at 4:00 am
Categories: Ansys, Inc., EDA

Only one company at the recent DAC conference and exhibit had a set of four interacting disciplines: Fluids, Structures, Electronics and Systems. Did you guess that the company was ANSYS? I get so IC focused at times that I almost forget that chips plug into boards, that boards become systems, and that systems drive and control mechanical devices where fluid airflow is a design challenge. One presentation made by ANSYS at #52DAC was titled, “Driving Low-power Design with Physical-aware RTL Power Budgeting Methodology“, and it caught my attention because of the EDA focus. ANSYS acquired Apache back in 2011, so during the past four years their electronics software has continued to meet familiar challenges like:

Power Budgeting
SoC Analysis
IP Validation
ESD Protection
IC/System Co-design
IO DDR Design
Thermal Planning
Package/PCB Electrical
Mechanical Stress

The big idea behind managing power during the design phase is to focus on tools for RTL designers, where they can change their code even before logic synthesis and physical implementation in order to achieve the greatest power reduction. With this mindset you then want a design for power environment where it’s possible to:

Trade-off power, performance and area
Perform voltage and power domain planning
Use block-level clock and data gating techniques
Eliminate redundant activity

With the ANSYS approach there are six steps that lead to a design that is optimized for low-power:

Perform Design Trade-offs at RTL
It’s easiest at the RTL level to look at implementing hardware in various approaches like creating an IFFT as pipelined, combinational or folded architecture. While at RTL you can quickly estimate power dissipation for each approach and choose the one that meets your power, performance and area goals.

Profile Design Activity
Using a tool like PowerArtist an RTL designer can actually profile design activity to identify power-critical windows, qualify vectors per mode, and identify any wasted activity.

Check Power versus Budget, Early
During RTL coding you should be looking at power in all of its forms: Average, Peak, Waveforms. This kind of early feedback enables an engineer to decide on a package type, decoupling capacitors, and grid design. Understanding the early power numbers across the hierarchy, by category (function, static or dynamic), by power mode will help identify all contributions to total power dissipation.

Early RTL power numbers can be within 15% of implementation values by using PowerArtist in conjunction with PACE models. In one case study NVIDIA compared RTL power numbers versus gate-level and saw results within 15%, while the RTL power numbers were calculated about 30X faster than gate-level values.

Identify and Debug Power Hotspots
There are a couple of approaches to debugging power hotspots: Graphic or Tcl-based. With the graphical approach you can spot anomalies in power by browsing for absolute power values, relative power values, cross-probing RTL to schematics, or using power metrics.

With the Tcl language a designer can get quick access to both power and design properties. Power metrics can be listed on each block of your design hierarchy, or by clock domains, or even down to the flop and latch levels.

Reduce Power Early at RTL
Two power reduction techniques that restructure your RTL are block-level clock gating and block-level data gating. There are even some built-in automation with PowerArtist that identify logic for clock gating, memory subsytem optimization, and reports on eliminating redundant activity.

Track Power via Regressions
Software development teams have used the concept of regression testing to improve code quality, and the same approach also improves the power reduction methodology so that your team can visually monitor power usage throughout the entire development cycle. You can run daily block-level power regressions, weekly chip-level power regressions, in order track your power change and track reduction opportunities.

Summary
The proof in any EDA methodology for electronics design is customer adoption, and at the DAC show there were plenty of ANSYS customers at hand, such as: Avago, Cavium, ClariPhy, Emulex, Freescale, Infineon, Intel, Mediatek, Microsoft, Qualcomm, Samsung and Tesla.

July 14, 2015

SEMICON Day 1: IoT Everywhere…and China

SEMICON Day 1: IoT Everywhere…and China
by Paul McLellan on 07-14-2015 at 5:00 pm
Categories: ESD Alliance, Semiconductor Services

The first day of SEMICON West for me is usually imec day. They have a full day of presentations. But I saw the most interesting ones in Brussels recently so I decided to go to the SEMI/Gartner day instead. They run in parallel ballrooms in the Marriot on 4th street.

To me there were two big themes. One was the unavoidable internet of things (IoT) although mostly wearables and automotive. Ian Ferguson of ARM touched on a zillion things in his whirlwind tour of the future (including his personal favorites to watch which are computer vision, medical and agriculture, all of which he thinks technology will change a lot).

Michele Reitz of Gartner took a stab at wearables to answer two big questions:

What is the semiconductor revenue potential in wearables through 2019?
Which semiconductor vendors are gaining share?

They had access to lots of teardowns and analyzed different market segments, so it was a rather more informed guess than just throwing out some number like 50 billion units.

So let’s start with the good news. The market should grow to 500M units by 2019, 2.5 times what it was in 2014.

But unfortunately there is bad news too: wearables are a high volume low profit opportunity. By 2019 the semiconductor revenue will grow to $4.2B by 2019 (but remember that is for 500 units so each one costs less than $10 on average). But $4.2 billion sounds a lot but is actually less than 1% of semiconductor revenue.

And which companies are benefiting? Freescale (soon to be acquired by NXP), TI, STMicroelectronics, Atmel, Intel. Intel is giving the keynote tomorrow morning so we might find out more then. But then, remember this is Intel, so we might not find out much.

The second big theme was China. Allen Lu had a great overview. China is an enormous semiconductor market. Because they manufacture so much electronics but don’t build that many chips, they import a lot. In fact, I was surprised to know, semiconductor imports are larger than oil imports. Of course they re-export quite a bit but they keep a lot too since they are also the largest market for mobile, for example, in units at least).

China has strategically decided that they want to build their own semiconductor industry and are making a lot of money available and putting a lot of pressure on making partnerships with global experts such as Intel and Qualcomm to make that happen.

There are lots of challenges and lots of opportunities. First, Allen’s challenges:

Global industry consolidation creates higher entry-barrier for new-comers (such as Chinese companies)
China semiconductor industry started late, lack of scale & core competencies
Advanced IC manufacturing requires huge funding
Technology, talent, market, supply-chain all global for Semiconductor industry
Chinese companies’ capability (or not) to go global (technology, marketing, business practice, decision process, …)
Reliance on government initiatives and funding hinders competitiveness
Need to establish solid business model & core competencies, avoid competing on price only

And the opportunities:

Government resolve and resources to scale up China’s IC manufacturing
Semiconductor industry entering mature phase with narrower margin. Electronic device
manufacturing continue to transfer to Asia from US, Japan and Europe
Semiconductor no longer favored by investors in US. Almost NO US VC funding to equipment and
materials companies in the last 10 years
China’s economy scaled up: capital and talent no longer the “show-stoppers”.
Electronic product eco-system established in China: products increasingly being defined and
developed in China (especially in mobile and consumer sectors)
Culture, language, eco-systems, of the application market increasingly replace cost and become
new advantages
Abundant engineer & science graduates coming to industry
Cost advantage still exists

When I was in Brussels recently they announced a joint venture with SMIC (majority owner), imec, Huawei, Qualcomm to collaborate on developing a 14nm process by 2020. There is other joint stuff going on.

And then, before we’d even go to the end of Allen’s Q&A, an audience member announced that Tsinghua Unigroup made a bid for Micron. If Allen had wanted a better way to convince any skeptics that the Chinese market is big, can’t be ignored, and the Chinese government is serious, then it would be hard to think of one.

July 14, 2015August 22, 2024

Angela Merkel Visits GlobalFoundries in Dresden!

Angela Merkel Visits GlobalFoundries in Dresden!
by Daniel Nenni on 07-14-2015 at 2:00 pm
Categories: Foundries, GlobalFoundries

The Chancellor of Germany visited Fab 1 in Dresden today. I did not get to speak with her personally so I will send her a message here. The fabless semiconductor industry is a force of nature. You can either harness the power or be overwhelmed by it. The United States, Taiwan, China, and South Korea have certainly figured this out. Hopefully Europe will be the next superpower to step up and make semiconductors a National Charter.

In my opinion one of the most important components of a country is their infrastructure and today that means semiconductors. Without a say in the semiconductors that control your infrastructure you have no security, simple as that.

While these words would be wasted on most politicians, Chancellor Merkel has her Doctorate in physical chemistry and is married to a quantum chemist professor. If I were to pick one semiconductor executive to convince the Chancellor to invest in the fabless semiconductor ecosystem it would definitely be Dr. Sanjay Jha, CEO of GlobalFoundries. Sanjay has spent his entire career in the fabless semiconductor industry including 20+ years at Qualcomm and pulling off the exit of the decade selling Motorola Mobility to Google. As CEO of GlobalFoundries Sanjay closed another historic deal acquiring the IBM Semiconductor Division.

Also Read: GLOBALFOUNDRIES Enables Next Generation of Connected Devices with Industry-first Technology Platform

“Fab 1 has a proud history of delivering leading-edge semiconductor technologies that have changed the world,” said Sanjay Jha. “Today, we are here to celebrate the launch of another technology innovation that will drive the next wave of the digital revolution.”

“22nm FD-SOI is a technology made and manufactured in Europe for world markets’, said Rutger Wijburg. “It is the culmination of ground-breaking work done in the French cluster and will strengthen the European SC supply chain.”

“The fabless semiconductor industry is a force of nature” said Daniel Nenni. “You can either harness the power or be overwhelmed by it.”

The only disappointment for me yesterday was the lack of European IP support. 90% of being successful in business is showing up. That is why I drive to Silicon Valley every week. That is why I fly to Taiwan every month. That is why I am in Dresden today. And that is why SemiWiki.com is the most successful semiconductor design portal, because we show up! Two of the largest IP companies are based in the UK. Is that not part of Europe? Who will gain more from having the lowest cost – lowest power process ramp up here in Germany? ARM and Imagination Technologies that’s who. Emailing quotes for a press release doesn’t cut it. You have to show up, absolutely!

And where is Qualcomm on FD-SOI? If they are serious about mobile business in China and other cost and power sensitive markets they had better start showing up for FD-SOI. Just my opinion of course but seriously, QCOM putting all of their eggs in the FinFET basket makes no sense whatsoever. This is the risk adverse company that invented second, third, and even fourth semiconductor manufacturing sourcing. By the way, QCOM is also the company that pushed TSMC and UMC into the incredibly successful 28nm polysilicon process business. Why? Because it was the lowest cost and lowest power that’s why.

July 14, 2015

VC For Semiconductor: Dead or Alive?

VC For Semiconductor: Dead or Alive?
by Paul McLellan on 07-14-2015 at 7:00 am
Categories: IP, Kilopass Technology

By Charlie Cheng, CEO of Kilopass.

Six years ago, I left my Entrepreneur-In-Residence (EIR) role at a venture capital firm to join Kilopass as an “interim CEO”, thinking the venture world will eventually forget about semiconductor as an industry as it matures. So it’s interesting to me how, six years later, the venture investment in the semiconductor industry has evolved, at least from what Kilopass has been exposed to lately.
By way of background, Kilopass isn’t looking for venture capital. With a strong cash balance, no debt, and high growth, the goal is to strengthen the management team, expand the product line, and win the heart of our customers and partners. As such, we’ve looked at, at least three acquisitions, and contemplated the Chinese capital market, recent volatility notwithstanding. It’s through these encounters that I get to see different visions and operations of VCs all around the world. It’s fascinating.

Let’s start first at North America, Europe, & Israel. Plenty of VCs have shut their doors on semiconductors, and the weak ones are basically just winding down the portfolios. But the surprising thing is the number of deals that are being closed in semiconductor industry. There seems to be a flood of talents coming out of industry consolidation, many with great product ideas, betting the giants will be too busy with operational efficiency and lose sight of roadmap innovation. The VCs, at the same time, are backing off from the frenzy of the mobile chase a bit, and diversifying BACK into the semiconductor industry. Two of these, in fabless model, have become our licensees and we expect to see more start-ups again!

Turning to perhaps the most surprising region, start-ups are being spun out of the carnage of a messy semiconductor consolidation in Japan. INCJ, a VC-PE firm in Japan and main investor of Renesas has spun out Floadia, a non-volatile memory IP company. Fujitsu has also spun the SOC business into Socionext. All of these new companies start with enviable assets not seen in North American start-ups, proven technologies or existing business. Unfortunately, they also start with much of the large company culture and business practice that they were running away from. Nonetheless, it’s refreshing to land in the Haneda Airport again, because the ”Semiconductor Renaissance” is hopefully just around the corner.

Taiwan is a worrying spot from venture investment perspective. Kilopass was approached by a very promising start-up looking to be acquired. The fit isn’t perfect, but I was shocked that it hasn’t been picked up already, either by a VC or a publicly held fabless or foundry. It seems the investors are obsessed with the public market volatility and arbitrage, and not enough time to foster the next generation blockbuster semiconductor giants.

Saving China for last, it is a fascinating nimble country despite its heft. After years of investing mostly in business expansion stages, the semiconductor investment appetite has now expanded to include some seed funding, but more importantly restructuring. The Chinese government is investing to reduce its dependency on semiconductor import, which in 2014 was higher than oil import. This simple but powerful vision is mixed in with government’s strategy of using the equity market to support the economic growth target. The end-result is a flurry of semiconductor companies going from NASDAC to Shanghai, at least until very recently, essentially profiting from the jump in the P/E multiple. I suspect there will also be acquisitions of international semiconductor companies by Chinese private equity firms. Both of these essentially change the domicile of the company because of the China nexus (management team, market, supply chain, etc.), and meet the Chinese aspiration to have domestic supply of semiconductor. The question in my mind is, whether these are enough to fundamentally change the semiconductor ecosystem, and if so, how fast. Nonetheless, the flurry of interest to gain access to the frothy Chinese equity market sure makes semiconductor an attractive business to be in again.

UPDATE: And right on cue, Tsinghua Unigroup (Chinese state-owned-enterprise, also Intel partially owned) made a $23B bid for Micron.

July 13, 2015

Improve RTL Physically for Design Quality & Convergence

Improve RTL Physically for Design Quality & Convergence
by Pawan Fangaria on 07-13-2015 at 12:00 pm
Categories: EDA

The SoC design teams are usually divided between front-end and back-end specialties. It is neither practical nor advisable to combine the two teams in order to better tackle the back-end issues upfront during the front-end design. However, a common problem is that the issues at the layout stage have very little scope for resolution unless the design team is ready to overhaul the design again from front-to-back. The net result is – either live with unworthy work-arounds in the layout or extend the design window which may be risky from the perspective of losing business. What if we had an automated way to let the front-end engineers know about the physical quality of a design, issues to be addressed, and tools to fix and debug at the RTL stage? Without needing intensive back-end design expertise, they should be able to fix the physical issues in the RTL. Better quality RTL will flow smoothly through the back-end tools such as physical synthesis and place & route without any severe issues to be addressed at the layout stage. The created layout can be much better quality the first time. Naturally, the end result will be a faster design closure with better quality of the design. Let’s look at an example:

Multiplexers (Mux) are very common in designs. A wide mux can contain a large number of inputs and a single output whereas a deep mux can contain a large number of select lines. The complexity created by a wide and deep mux can have severe implications in routability down the stream which in-turn can cause several issues including layout congestion, signal integrity and timing. A back-end designer will run through several P&R iterations and still will not be able to fix such issues satisfactorily at the layout stage. This needs to be better handled architecturally at the RTL stage, provided such implications downstream can be provided at the RTL stage.

I was impressed with Atrenta’s“Physical Lint” methodology where they have a large number of expert physical rules that can be applied to the RTL code of a design to understand its quality from the physical perspective. The checks against these rules can flag complexity issues beyond particular thresholds for complex structures such as a large mux as discussed above and others like large logic cones, cell pin densities, and so on. Having awareness about such physical implications at the RTL stage, the front-end engineers can easily fix such issues in the RTL code and do light-weight trials at the RTL stage.

To assist the front-end engineers, SpyGlass Physical has an excellent GUI for physical rule analysis and debug. The complex structures can be automatically inferred and their complexity scores listed in an ordered list, along with their references in the source code. The RTL source code can be cross probed with the schematic. The front-end engineers can take corrective actions to simplify complex structures and re-run physical rule analysis to lower the complexity scores. For example, in case of the mux as depicted in the picture above, the mux traffic can be distributed or spread more efficiently across the design. By using this method, the front-end engineers can easily comprehend the impact of complex structures on downstream tools and improve quality of the RTL to be handed over to the back-end team.

It has been observed that the design utilization can be improved significantly by resolving logic structure violations in the RTL. In the above design examples, priority was given to resolve the highest scored items, leaving remaining violations unresolved. The methodology and effort to be put on resolving the structural issues before signing off the RTL is left to the discretion of the design teams.

The RTL improvement through resolution of complex logic structures leads to faster and predictable design convergence with better quality metrics of the design. More information about the SpyGlass Physical Lint methodology can be obtained from the customer support team at Atrenta.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

July 13, 2015August 22, 2024

Silicon Saxony!

Silicon Saxony!
by Daniel Nenni on 07-13-2015 at 8:00 am
Categories: Foundries, GlobalFoundries

The “Saxony” reference comes from the Holy Roman era which is now the tenth largest of Germany’s sixteen states and is divided into ten districts. The “Silicon” comes from the microchip makers in the Dresden area which is district #2. The largest of said chip makers is now GlobalFoundries so in the same vein that California has Silicon Valley, which is where I’m from, Germany has Silicon Saxony, which is where I am today.

The first major semiconductor chip manufacturing started here when AMD arrived in the 1990s. Over a 10 year period AMD invested more than $6B in the “AMD Saxony” location here in Dresden. Production began using 200mm wafers at 180nm and 130nm bulk CMOS. The AMD SOI revolution started at 90nm extending down to 32nm using 300mm wafers. GlobalFoundries is now continuing that tradition with 22nm FD-SOI which you have probably already read about on SemiWiki.

Rumors of 22nm FD-SOI had been circulating Silicon Valley for months. The first official leak sprung at the Advanced Semiconductor Manufacturing Conference last May which resulted in this blog:

ASMC 2015: GlobalFoundries 22nm SOI plans and more!

“During the question and answer session I asked Dr. Caulfield about GlobalFoundries SOI plans. He replied that they are developing a 22nm process in Malta for manufacturing in Dresden. The goal is 14nm FinFET performance at 28nm costs.”

There is also quite a spirited discussion in the comments section that should be well worth your time. The second leak came from an FD-SOI workshop:

GlobalFoundries Endorse ST/LETI FD-SOI 22nm!

This is why SemiWiki Bloggers attend live events whenever possible because you can’t always believe everything you read, even sometimes by the vendors themselves! :rolleyes:

Paul wrote about the formal announcement HEREand you can see the announcement slide deck HERE. Paul will do live briefings during SEMICON in San Francisco while I get briefed here in Dresden. It will certainly be an interesting week. Paul and I will compare notes when I return and synthesize what we feel the real significance is. Your comments help so please chime in whenever possible, semiconductor crowdsourcing at its finest, absolutely.

And for your entertainment here are quotes from the official press release:

“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance, and cost,” saidSanjay Jha, chief executive officer of GLOBALFOUNDRIES. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration in connectivity applications, the platform delivers the highest frequency, lowest variability, and best energy efficiency.”

“GLOBALFOUNDRIES’ FD-SOI offering, using an advanced FD-SOI transistor architecture developed through our long-standing research partnership, confirms and strengthens the momentum on this technology by expanding the ecosystem and assuring another source of high-volume supply,” Jean-Marc Chery, chief operating officer of STMicroelectronics. “FD-SOI is an ideal process technology to meet the unique always-on, low-power requirements of IoT and other power-sensitive devices worldwide.”

“Freescale’s® next-generation i.MX series of applications processors is leveraging the benefits of FD-SOI to achieve industry leading ultra-low power performance-on-demand solutions for automotive, industrial and consumer applications,” said Ron Martino vice president of applications processors and advanced technology adoption for Freescale’s MCU group. “GLOBALFOUNDRIES’ 22FDX platform is a great addition to the industry which provides a high volume manufacturing extension of FD-SOI beyond 28nm by continuing to scale down for cost and extend capability for power-performance optimization.”

“The connected world of mobile and IoT devices depend on SoCs that are optimized for performance, power and cost,” said Will Abbey, general manager, physical design group, ARM. “We are collaborating closely with GLOBALFOUNDRIES to deliver the physical IP needed for customers to benefit from the unique value of 22FDX technology.”

“FD-SOI can deliver significant improvements in performance and power savings, while minimizing adjustments to existing design-and-manufacturing methodologies,” said CEA-Leti CEO Marie Noëlle Semeria. “Together, we can collectively deliver proven, well-understood design-and-manufacturing techniques for the successful production of GLOBALFOUNDRIES 22FD-SOI for connected technologies.”

“GLOBALFOUNDRIES’ announcement is a key milestone for enabling the next generation of low-power electronics,” said Paul Boudre, CEO of Soitec. “We are pleased to be GLOBALFOUNDRIES’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FD-SOI technology.”