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GPS Chronicle: When Phone Met Location

GPS Chronicle: When Phone Met Location
by Majeed Ahmad on 08-10-2015 at 12:00 pm
Categories: Mobile

Benefon, one of the GSM pioneers, was the first handset maker to marry cellular with GPS in response to the European Union’s Mobile Rescue Phone (MORE) project during the mid-1990s. The result of this ambitious effort was the launch of the Benefon Esc! phone in late 1999 and Benefon Track device in 2000.

The Esc! phone was splash-proof and featured a large, grayscale LCD. It allowed users to load maps onto the phone to trace their position and movement, and even to call or send their coordinates via SMS to a list of set numbers by setting an “Emergency Key.” Interestingly, it also featured a “Friend Find” service, whereby users with Esc! handsets could track each other’s locations directly on their handset display.


The first GPS phone launched in 1999

It was evident by the late 1990s that by harnessing the power of location services in wireless handsets, GPS could radically alter the smartphone makeup. However, for that to actually happen, the industry had to overcome a few major stumbling blocks. For a start, GPS was a line-of-sight satellite technology while cellular was not. Then there were problems regarding indoor reception of GPS signals, which was inherent in satellite communications. A user couldn’t rely on the phone’s GPS to get around inside buildings.

Handset manufacturers like Ericsson and Nokia were initially reluctant to embed GPS circuitry into mobile phones, citing time-to-market issues and the added cost. A more crucial challenge related to lowering power consumption in the GPS circuitry in order to integrate it into mobile devices. The complexity and footprint of GPS chip, as well as the need for a separate antenna, further complicated a successful integration onto the mobile phone platform.

Then, there came this marvel of system integration that crystallized a new direction for cellular networks’ liaison with server-assisted location services. In May 2000, J-Phone, the first wireless operator to release a phone with a built-in camera, launched the world’s first location-based mapping service that displayed interactive maps within a web micro-browser. GPS met location met mobile Internet!


J-Phone’s J-Navi service was a pioneering effort to merge GPS into the handset

Japan’s second-largest mobile phone operator launched the J-Navi service, letting users in Tokyo enter a phone number, address or landmark, and then search the area within a 500-meter radius. This made it possible to find the subway station nearest to a particular shop, or a particular kind of restaurant within walking distance of an office building.

Most important, users of the service could download a full-color map. At the time of its launch, J-Navi was expected to handle around 100,000 hits per day, but on its third day of operation, it already had 1.6 million users. Searching was free, but users paid for the data transport costs, so in practice, it cost about 4 cents for a location search.

In the meantime, specialized chipmakers continued to improve the accuracy and availability of the GPS technology. The new circuitry was also able to gradually trim the GPS power for use in cellular phones. By late 2000s, smartphones had GPS systems on-board, and with location-aware Internet services, they were helping people to get from point A to point B.


Smartphone opened the floodgates of location-centric innovation

Google’s initiative of free turn-by-turn navigation for smartphones brought a lot of momentum to the smartphone industry. When used with a smartphone, the software sends coordinates to a server over the phone’s wireless Internet connection to grab mapping data. Maps are also stored on the handset’s SD memory card in some cases.

That way, directions keep coming when a user can’t get cellular reception, so long as he or she is still getting a GPS signal. Google’s Navigation app was probably one of the best in the lot; it took up almost no space on the phone because everything was in the cloud.

Also read:

GPS Chronicle: The Early History

GPS Chronicle: The Beginning of the Commercial Era

Content of this article is based on excerpts from the book Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronics.

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The Magnificent Seven of International IP Management

The Magnificent Seven of International IP Management
by Paul McLellan on 08-10-2015 at 7:00 am
Categories: EDA, Perforce

Almost all large projects these days are distributed across multiple geographic locations. As the world rotates underneath the sun, the focus of activity moves too: Europe, US, China, India, back to Europe. For this to work effectively requires a collaborative platform designed for multi-site design efforts, a platform that communicates the current state of the design, planned changes, history, and delivers what each site requires with minimal user intervention and maximum efficiency.

There is a famous aphorism, attributed to Willem van der Pohl, that there are only three numbers in computer science: 0, 1 and infinity. When providing a service like IP data management, there are some things that you want to be centralized (only one of them) and otherwise you want an unrestricted number of them (sites, IPs, projects, bugs…). This gives you the best mixture of integrity and efficiency, giving the illusion of a single central repository without the obvious efficiency issues of actually keeping all the data at a single central site.

Here are The Magnificent Seven of multi-site collaboration (or The Seven Samurai if you are more into Japanese cinema, Or 七人の侍 if you are really into Japanese cinema):
[LIST=1]

  • Centrally Defined Configuration Management: ProjectIC has the PiServer central database of IP and project metadata including the hierarchical resource tree for each project collected from user workspaces.
  • IP-centric Bug Tracking: Off-the-shelf bug-tracking tools such as Jira and Bugzilla don’t work well in an IP context since each IP is usually considered a separate “project” in the bug-tracking database. With hundreds of IPs in a typical SoC and perhaps thousands in a large semiconductor company this is impractical to use directly. ProjectIC will query the bug database for bugs associated with each IP version and present a consolidated hierarchical view of bugs found for the whole SoC.
  • Centralized IP Catalog: there needs to be a centrally defined database to discover the existing IP in the company, including its quality, the location of the files in the data management system, all the available versions of the IP, which versions are recommended for use by the IP owner, which projects are using these versions and so on. The ProjectIC PiWeb catalog has an easy to query searchable database with multiple levels of metadata for organizing IPs including labels, custom properties, project based etc. This catalog is auto-updating and self-regulating so that when IPs and IP versions are introduced to the system from with within a project they are automatically added to the catalog (this is important: if manual update is required then it can be guaranteed that the data is stale if not plain wrong).
  • Multi-Site Data Replication: Although the IP metadata needs to be centralized, the data management repositories themselves need to be replicated to reduce the time to deliver files to user workspaces. For example, one underlying data management environment is Perforce (with its Edge and Replica servers) where metadata queries, commits and syncs can happen locally without the need for WAN access, all without any user interaction.
  • Decentralized Data Management: Another method for reducing multi-site data latencies is to maintain the master Subversion or Perforce repository at the remote site if that is where the majority of the development activity is taking place. ProjectIC allows the repository location to be defined on a pre-IP basis so that workspace creation will query the local server and reduce WAN delays
  • Multi-site IP caches: An important part of the Methodics multi-site solution is the use of IP Caches to maintain local read-only versions of popular IPs for consumption at remote sites. These are updated and propagated automatically as part of the IP release process and mean that users who only need read access to a particular IP can set that IP to “refer” in their workspace configuration and ProjectIC will manage the reference automatically.
  • Large Dataset Block-level Replication: A slightly different technique for reducing multi-site delays is to use Warpstor to maintain master versions of the important project workspaces and deliver changes multi-site between these masters incrementally at the file-system block level, as new releases are made. This reduces the need for large DM checkouts into a workspace since the user workspaces can use lightweight clones using these replicated masters.

    See also WarpStor, the Data Tardis: Small on the Outside, Large on the Inside


    The white paper Methodics—Architected for Multi-Site Collaboration is here.

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    Virtual Reality is Ready to Rocket

    Virtual Reality is Ready to Rocket
    by Daniel Payne on 08-09-2015 at 7:00 am
    Categories: General, Mobile

    Virtual Reality (VR) is such a hot technology concept right now that the topic has made the cover of Time, Wired and Forbes magazines this year, along with countless online articles. What really captured my attention was that moment in 2014 when Facebook acquired VR startup Oculus for $2B, yes that is billions of dollars. The last time that I saw this much excitement was the advent of personal computers back in the late 1970’s.


    Palmer Luckey, founder of Oculus VR

    To make VR work you need several components:

    • A headset to immerse viewers with 3D content
    • A video processing engine capable of quickly rendering 3D content
    • 3D content that is compelling for entertainment, education or exploration

    There are a few dozen companies all clamoring for position in this brave, new, 3D, VR world. VR headsets can range from a simple, folded piece of cardboard like Google Cardboard that uses your existing cell phone, to commercial headsets with integrated headphones.


    Google Cardboard

    Video processing may be supplied by your cellphone, tablet, laptop, desktop or dedicated hardware. If you visit the local BestBuy store, the only VR product for sale are headsets that use either the Samsung Galaxy S6 or Samsung Galaxy Note 4cell phones as the video processing and software from Oculus:


    Samsung Gear VR

    Let’s take a quick survey of other VR headsets that have been announced to get a feel for the variety to choose from:

    [TABLE] style=”width: 500px”
    |-
    | Product
    | Features
    |-
    | Oculus Rift
    |

    • Crowd-funded on Kickstarter, owned now by Facebook
    • Both audio and video, wired
    • Available Q1 2016


    |-
    | Project StarVR
    |

    • Hardware by InfinitEyes
    • Software by Starbreeze
    • Dual Quad HD screens
    • Still in development


    |-
    | AirVR
    |

    • iOS devices only
    • Kickstarter funded
    • In development


    |-
    | Avegant Glyph
    |

    • Audio and Video
    • 120 Hz refresh rate
    • In development


    |-
    | Cmoar
    |

    • Powered by Android or iOS devices
    • Includes Augmented Reality
    • Kickstarter funded


    |-
    | Dior Eyes VR
    |

    • Dior fashion brand
    • Uses Samsung Galaxy Note 4 device
    • Fashion viewing market


    |-
    | Emax X1
    |

    • Compatible with Oculus Rift
    • Made in China
    • Soon to launch


    |-
    | Fove
    |

    • Eye-tracking technology
    • Full 360 degree experience
    • Kickstarter funded


    |-
    | Google Cardboard
    |

    • Use most any smart phone
    • Lowest price
    • Available now


    |-
    | Homiod
    |

    • Smart phone powered
    • Wireless
    • 69.99 Euros


    |-
    | HTC Vive
    |

    • HTC and Valve team
    • Available end of 2015
    • Content from HBO, Lionsgate, Google


    |-
    | ImmersiON BlueSky Pro
    |

    • Dual 1920 x 1080 displays
    • Multiple game engine support
    • From Silicon Valley and Spain


    |-
    | Impression PI
    |

    • Senses hand gestures
    • Versions for smart phones and stand-alone
    • Kickstarter funded


    |-
    | MindMaze NeuroGoggles
    |

    • Brainwave controlled
    • Tracks hand motions
    • From China


    |-
    | Pinch VR
    |

    • Uses your smart phone
    • Includes finger sensors
    • From Canada


    |-
    | Razer OSVR
    |

    • Software is Open Source
    • Well-known gaming company
    • Coming soon


    |-
    | Samsung Gear VR
    |

    • Available at BestBuy
    • Uses Samsung Galaxy Note 4 or S6 devices
    • $199.00


    |-

    Source: Virtual Reality Times

    What an amazing array of VR devices that are soon to be unleashed into the consumer and commercial marketplace. If I were to guess which of these VR headsets are still around in 18 months it would: Oculus Rift, Samsung Gear VR and Razer OSVR. Let’s see what Facebook does with their Oculus brand and if Samsung can create early interest in VR. I was surprised to see some 114 favorable product reviews on BestBuy about the Samsung Gear VR device, yielding a 4.5 out of 5 star rating.

    Economically speaking, I think that the real winners are the 3D content creators, because they should command bigger revenues than just the hardware providers of VR. It’s the same business model as Game Consoles, sell the console for a low or subsidized price, then make all of your revenue and profits on each new gaming title.

    Who knows, there may even be some use of VR for EDA companies as IC designers may benefit from taking a 3D tour of their FinFET chips, packages and boards.

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    Never Imagined So Easy Class-based Testbench Debugging

    Never Imagined So Easy Class-based Testbench Debugging
    by Pawan Fangaria on 08-09-2015 at 7:00 am
    Categories: EDA, Siemens EDA

    When it comes to debugging a design testbench organized in object-oriented style with objects, component hierarchies, macros, transactions and so on, it becomes an onerous, tasteless, and thankless task for RTL verification engineers who generally lag in software expertise. Moreover, class-based debugging tools have lagged simulators ability to simulate these testbenches. However, modern testbenches are most likely to be class-based using object-oriented programming concepts. They are generally developed using SystemVerilog and UVM. In such a situation, how about having an automated, GUI driven, post-simulation debugging environment which becomes a fun to operate with for RTL verification engineers without needing software expertise? Yes, such class-based debugging tools and environment have come up to make debugging of SoC design testbenches easy, interesting and productive.


    Mentor’sVisualizer along with Questa simulation provides an excellent class-based debugging environment. In the above diagram, there is a simple UVM schematic with a DUT and four interfaces. Each interface is connected to an agent. Traversing down the hierarchy, we can see that each agent has a sequencer, a driver, and a monitor. Although the UVM-based testbench can always be explored through schematics, a faster and convenient approach for debugging large circuits can be to debug directly through objects in the testbench.

    The UVM component hierarchy can be traversed to any level. Any object selected in the component hierarchy window will have its corresponding source code displayed in the source code window. In the source code, the value of any member variable inside an instance of an object can be displayed by just hovering over the variable. In the post-simulation mode, all objects that existed during simulation and recorded by Questa are accessible for investigation into their class member variables. Similarly virtual interfaces of the objects can be explored. For post-simulation exploration, there are easier ways to display all member variables of an object at once at any instance of time.


    By pressing the right-mouse-button in the source code of an object, selecting ‘Browse This’, and then selecting ‘t’, one can see the complete object pointed to by ‘t’ at the current time. The ‘t’ points at the object ‘@sequence_item_A@4841’ in the above example. A still shorter way to see the object could be by selecting ‘t’, pressing right-mouse-button, and then selecting ‘Browse (t)’.


    By pressing the right-mouse-button and selecting ‘Add ‘this’ To Wave’, one can add the current object to the waveform window and display all the transactions that the object has created. That’s really powerful.

    The Class Instance Window provides another way of exploration for UVM testbenches. It is organized by base class. By expanding and selecting particular objects we can change the current context to a required object. The creation times of different objects are displayed in this window. A search can be created to find objects created between two times. Also, instances can be searched based on a regular expression.


    In the above window, a search is created based on any object ending in ‘4839’. The regular expression “*4839” has been entered in the search field. A selection of the first sequence_item_A has also displayed the source code for that object. Hovering over the ‘addr’ field shows the address for that transaction (that sequence item). Similarly, the other sequence_item_A objects can be investigated.

    Also, the expressions can be created on particular address values for checking transactions on those addresses.


    A StripeViewer is opened above and expression ‘32’h000006eb’ entered in the ‘addr’ field. A search then shows the above transactions.


    On a click on ‘Add to Wave’, the transaction stream enters the wave window. A selection of any transaction in the StripeViewer highlights the same in the wave window. For example, the transaction selected, as shown in green in the StripeViewer, moves the cursor to the particular transaction in the wave window as shown above.

    This kind of post-simulation class-based debugging brings a new dimension to modern SoC verification and debugging. The designers can have full visibility into the design with little effort and RTL verification engineers can easily debug the design. Read a whitepaperwritten by Rich Edelman at Mentor Graphics for a detailed and interesting tour over these methods. They have applied this approach for debugging real customer designs with great success!

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com

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    Is 7nm Coming to the TSMC OIP Ecosystem Forum?

    Is 7nm Coming to the TSMC OIP Ecosystem Forum?
    by Daniel Nenni on 08-07-2015 at 4:00 pm
    Categories: FinFET, Foundries, TSMC

    This is the 5[SUP]th[/SUP] TSMC Open Innovation Platform Ecosystem Forum and it is not to be missed. Please note that the location has moved from the San Jose Convention Center to the Santa Clara Convention Center which is literally right across the street from the new Levi’s Stadium. If you haven’t been to the new stadium you really should take a tour and stop by the SF 49ers Museum. Public tours run between 10am and 6pm and yes they have WiFi.

    The new location will increase attendance significantly this year (my opinion) so you had better register now because space is limited. In addition to networking with 1,000+ semiconductor professionals you will get to hear from TSMC’s executives on what is new and improved for the different processes and surrounding ecosystem: 28nm, 16nm, 10nm, and I would bet 7nm will also be mentioned if not formally announced.

    You may also get to hear from one of TSMC’s leading customers. At the TSMC Technology Symposium last April the guest speaker was Avago CEO Hock Tan. Since then Hock has engineered the acquisition of Broadcom for $37B. Previously he acquired LSI Logic for $6.6B so I would definitely like to hear a semiconductor industry update from an executive of his caliber, absolutely.

    The event starts at 9am on Thursday, September 17[SUP]th[/SUP]. After the ninety minute executive presentations there are 30 technical papers divided into three tracks for EDA, IP, and Services. The paper abstracts are now up on the OIP website. And of course there will be a vendor expo with 80 vendors bearing gifts and the latest news on design enablement. Rumor has it Solido Design will be giving away the elite SemiWiki.com stylus penlights so you may want to go there first.


    Click HEREfor the event overview, agenda and registration

    [TABLE] cellpadding=”4″ style=”width: 100%”
    |-
    | align=”center” style=”width: 15%” |
    | align=”center” style=”width: 27%” | EDA Track

    | align=”center” style=”width: 29%” | IP Track
    | align=”center” style=”width: 29%” | EDA/IP/Services Track
    |-
    | 11:00 – 11:30
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Tackling coloring, cell pin access and variation at TSMC 10nm
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Low power SERDES to concurrently enable HMCPCIe in 16FF
    |-
    | align=”center” valign=”top” | Analog Bits

    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Ultra Low Power OTP Design for Smart Connected Universe Applications

    |-
    | align=”center” valign=”top” | Sidense
    |-

    |-
    | 11:30 – 12:00
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Exploring Custom Metal Stacks for Advanced Node IC Design Using Early StarRC Extraction
    |-
    | align=”center” valign=”top” | Synopsys
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Migrating ARM Cortex-A53 designs From 28HPM to 28HPC+ – Getting Two Designs Out of a Single Implementation
    |-
    | align=”center” valign=”top” | ARM
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Timing Closure Strategy with Massive Scenarios in Advanced Node
    |-
    | align=”center” valign=”top” | Dorado Design Automation
    |-

    |-
    | 12:00 – 13:00
    | colspan=”3″ align=”center” valign=”top” | Lunch
    |-
    | 13:00 – 13:30
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Thermal and Color-aware Reliability Verification for Sub-16nm FinFET Designs
    |-
    | align=”center” valign=”top” | Ansys Inc.
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Complexities in developing a high performance DDR subsystem at 3200 Mbps on 16FF+10FF
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | High-Speed SerDes Design in Advanced TSMC Process: Architecture Implementation
    |-
    | align=”center” valign=”top” | GUC
    |-

    |-
    | 13:30 – 14:00
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Custom Device Array- Place, Route, Simulate Prior to Layout
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Implementing a Dual Modulation 56G SerDes IP platform in TSMC 16FF
    |-
    | align=”center” valign=”top” | Semtech Corporation – Snowbush IP
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Device Aging Simulation Considering Self-Heating Effect using TSMC N16 FinFET Process
    |-
    | align=”center” valign=”top” | Synopsys
    |-

    |-
    | 14:00 – 14:30
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Hierarchical Fill Methodology for Advanced Nodes
    |-
    | align=”center” valign=”top” | Mentor Graphics
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Ultra-Low Power IoT Platforms from Silicon to Software
    |-
    | align=”center” valign=”top” | Synopsys
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | M31 Low-power IP Platform
    |-
    | align=”center” valign=”top” | M31 Technology
    |-

    |-
    | 14:30 – 15:00
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | IC Packaging centric approach to design fanout-out WLCSP (InFO) designs
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Rapid Implementation of IoT end-point sensor devices using ARM and TSMC IP
    |-
    | align=”center” valign=”top” | ARM
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | How to avoid blindness about power consumption during low-power SoC design?
    |-
    | align=”center” valign=”top” | Dolphin Integration
    |-

    |-
    | 15:00 – 15:30
    | colspan=”3″ align=”center” | Coffee Break
    |-
    | 15:30 – 16:00
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | 2-5X productivity improvement in converging to a DRC-clean cell design—Qualcomm’s experience with Calibre RealTime
    |-
    | align=”center” valign=”top” | Mentor Graphics
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Design of an integrated wireless 4K video camera SoC IP platform
    |-
    | align=”center” valign=”top” | Imagination Technologies
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Advanced Bump Routing Methodology for SoC Designs with flip chip
    |-
    | align=”center” valign=”top” | Open-Silicon
    |-

    |-
    | 16:00 – 16:30
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Synopsys’ PrimeTime POCV Improve Productivity and PPA in FinFET Designs – NVIDIA Experience

    |-
    | align=”center” valign=”top” | Synopsys
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Resolving 10G Bandwidth Issues for High Performance Analog Circuits on TSMC 10FF
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | A New Solution to Sensing Scheme Issues Revealed
    |-
    | align=”center” valign=”top” | Kilopass
    |-

    |-
    | 16:30 – 17:00
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | TSMC Advanced Node EMIR analysis
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Meeting IP Requirements of Next-Generation Automotive SoCs on FinFET Processes
    |-
    | align=”center” valign=”top” | Synopsys
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Extend trustworthy logic NVM solutions from 8″ to 12″ process nodes for various IoT applications
    |-
    | align=”center” valign=”top” | eMemory
    |-

    |-
    | 17:00 – 17:30
    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | IC Compiler II key in accelerating time-to-market for HiSilicon’s next-generation 10-nm advanced SoC’s
    |-
    | align=”center” valign=”top” | Synopsys
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Building Silicon IPs
    Sub-systems for Automotive Infotainment ADAS Applications
    |-
    | align=”center” valign=”top” | Cadence
    |-

    | align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
    |-
    | align=”center” valign=”top” | Accelerating IP To IP Sub systems and Moore
    |-
    | align=”center” valign=”top” | Synopsys
    |-

    |-
    | 17:30– 18:30
    | colspan=”3″ align=”center” | Social Hour
    |-

    The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practices in TSMC’s design ecosystem will highlight the event.

    More than 90% of last year’s attendees said that “the forum helped them better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

    This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!

    This year, the forum is a day-long conference kicking-off withtrend-setting addresses and announcements from TSMC and premier IC design company executives.

    The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion feature up to 80 member companies showcasing their products and services.

    Click HERE for the event overview, agenda and registration
    Posted on

    ClioSoft SOS v7.0: Faster, Smarter and Stronger

    ClioSoft SOS v7.0: Faster, Smarter and Stronger
    by Majeed Ahmad on 08-07-2015 at 12:00 pm
    Categories: Cliosoft, EDA

    System-on-chips (SoCs) are now everywhere, whether they are processors, microcontrollers or FPGAs, and what matters more these days is how quickly these large and complex chips adapt to the specific needs of the OEM application or the “system.” So time-to-market window is shrinking, and conversely, the use of IP tools is increasing in order to efficiently manage the rising complexity and time-to-market requirements of SoC designs.

    One of these IP tools is ClioSoft Inc.’s SOS, a design data management solution for analog, RF, digital and mixed-signal designs. The ClioSoft SOS design collaboration platform—which has an 18-year history of being tightly integrated with traditional EDA flows—allows chip engineers to use tools from different vendors to design digital, analog and RF design modules.

    Now ClioSoft has released version 7 of its SOS design collaboration tool, which it claims is faster, smarter and stronger. The SOS v7.0 is upward compatible with earlier SOS versions and provides SoC designers with all the features of previous versions of the design data management tool.

    In SOS v7.0, ClioSoft has added the bandwidth spice to its multi-site architecture. That’s a significant improvement because managing progress at each design site is crucial in getting the chip to the market in time. The speed factor enhances the ability of SOS data management tool to manage design data from concept through GDSII and mitigate the possibility of design re-spins because of incorrect configurations.


    SOS7 tool uses HSDT technology for bandwidth boost

    ClioSoft has over 150 customers—ranging from large foundries to small design shops—that use the SOS configurable IP platform. So how does SOS v7.0 differ from previous versions? Below is the recap of the three salient features of the SOS v7.0 design data and enterprise IP management platform.

    Faster Data Management

    ClioSoft claims that SOS7 is up to 30 times faster than previous versions of its SoC design collaboration platform. The data management tool supplier is using hyper streaming data transport (HSDT) technology to enable faster queries and caching operations.

    The use of HSDT technology allows SOS7 to ensure data compactness and thus create smaller repositories. Moreover, remote design centers can efficiently keep synch with each other and to the central repository by making use of the faster and more efficient communications links.


    SOS7 provides faster access to design data at multiple sites

    Smarter Data Management

    Remote design centers are becoming a mainstay in the SoC design environment because design tasks are now divided among several subsets of a large design team. That allows several tasks to be completed simultaneously and thus reduce the time it takes to transition into the physical design stage and tapeout.

    So the new version of SOS accommodates more remote sites through greater scalability and thus supports more users and data traffic. ClioSoft has managed to enhance the scalability by allowing SoC design teams to create work areas more quickly. Moreover, SOS7 boasts a better reporting infrastructure to streamline design workflow.


    ClioSoft’s distributed architecture is inherently more suitable for multi-site SoC design

    More Reliable Data Management

    As mentioned earlier, the SoC designs are increasingly becoming complex, so they require appropriate levels of error resilience and security. ClioSoft’s SOS7 version further improves reliability with new features such as repository hot backup and balancing of the load to accommodate more users.

    That’s on top of the existing SOS featureslike release and derivative management, integrated revision control, and issue tracking interfaces to commonly-used bug tracking systems. ClioSoft claims that SOS is the only design management platform that supports all types of designs: digital, analog, RF and mixed-signal.

    Also read:

    Starvision and SOS, a Perfect Match

    Why Design Data Management: A View from CERN

    ClioSoft Celebrates 2014 with 30% Revenue Growth!

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    Just One Month to SEMICON Taiwan

    Just One Month to SEMICON Taiwan
    by Paul McLellan on 08-07-2015 at 7:00 am
    Categories: ESD Alliance, Semiconductor Services

    SEMICON Taiwan is the first week of September in the Taipei Nangang Exhibition Center. To be precise it is September 2nd to 4th. Last year there over 26,000 people attended. This year it is the 20th anniversary show. SEMICON Taiwan attracts the world’s leading technology companies who design, develop, manufacture, and supply the technologies to manufacture the microelectronics that drive today’s most sophisticated consumer and commercial electronic products. So if you attend, you can connect with the companies, people, products and information shaping the future of design and manufacturing for semiconductors, nanoelectronics, MEMS, Photovoltaics and related advanced electronics.

    For equipment manufacturers, there is no more important market than Taiwan. With new manufacturing technologies such as 450mm and EUV in development and with the continued growth of emerging and adjacent microelectronics markets (including high-brightness LEDs, MEMS, 3D IC, and plastic electronics), 2015 is already shaping up to be an important year for the global microelectronics supply chain. Taiwan is expected to invest over US$10 billion in 2015, which make Taiwan the single largest semiconductor equipment market in the world, ahead of the US and Korea.

    Here are some of the things that will be taking place this year:

    • Opening Ceremony: 9/2 from 9.30 to 10.30 including ribbon cutting, awards, and VIP tour
    • Gala Dinner: an annual festival of Taiwan’s Hi-tech/Semiconductor/LED community with more than 400 industry leaders from around the world
    • Technology programs

      • Day 1: Semiconductor materials forum, sustainable manufacturing forum, advanced packaging technology symposium, plus (all day), MEMS forum and (all day) TechXPOT on the main stage in the exhibit hall
      • Day 2: (all or half day events running in parallel) High-tech facility international forum, eMDC forum, SIP global summit: 3DIC , IoT, TechXPOT
      • Day 3: (all or half day events running in parallel) SIP global summit: wafer level packaging, CMP forum, IoT, automotive design, TechXPOT
    • Business programs

      • Day 1 (1pm to 5pm) Executive summit
      • Day 2 (8am-12pm) Market trends forum, (1pm to 5pm) CFO summit
      • Day 3 (10am-5pm) Memory summit
    • National pavilions for Japan, Korea, Holland, Belgium, Germany, Russia and Cross-strait (I guess that is a tactful way of saying China)
    • Smart manufacturing pavilion, AOI (Automated Optical Inspection) pavilion, materials pavilion, precision machinery pavilion, hi-tech pavilion, secondary market pavilion, CMP pavilion, MIRDC (Metal Industries Research & Development Centre) pavilion, SICA (Silicon Carbide) pavilion
    • Job fair

    If you are thinking of exhibiting, SEMICON Taiwan attracts a highly influential audience from every segment and sector of the European microelectronics industries, including semiconductors, solar/PV, LEDs, MEMS, printed/organic/flexible, and other adjacent markets. Above is the breakdown of visitors from 2014.

    So join Jing-Jing, SEMCON Taiwan’s mascot, in September. Who is he? A baby born in a semiconductor plant, knows the movement of world’s semiconductor industry. With the radar on his head, Jing-Jing can forecast the market trends and connect the industry supply chain. He even has a Facebook page here.

    Full details are here(English) and here(中文). Registration is here.

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    Foolproof Your IP before it Stumbles in Higher-up Design

    Foolproof Your IP before it Stumbles in Higher-up Design
    by Pawan Fangaria on 08-06-2015 at 4:00 pm
    Categories: EDA, Fractal Technologies

    SoC designs are increasingly becoming assemblies of a large number of IP blocks. A well integrated assembly can lead to a successful PPA (Power, Performance and Area) optimized design. However, it is equally important that each IP block is optimized, robust, and integrable in the design. The complexity of an IP and its integration can be so high that any kind of re-work can prove to be very costly. This issue has been recognized by the SoC design industry; otherwise we wouldn’t have seen the emergence of IP cataloging for choosing the best IP for a particular function in an SoC. A semiconductor services company, eSilicon has gone much beyond cataloging by providing “Try IP Before You Buy” kind of services where you can check whether your chosen IP fits well in your SoC environment or not.

    The point is, in the current IP and SoC market one cannot afford to lose on design time and miss occasionally available, small time-to-market window. Before using an IP for integration, a quick check on its quality and suitability for integration can save a substantial amount of rework down the SoC integration and verification flow. This can also enable you to better predict your SoC design and verification schedule. This is explained very well in a graph provided by Fractal Technologies which depicts how repair time during SoC integration after IP shipment starts increasing exponentially, thus destabilizing overall design schedule.

    Fractal’s Crossfire has more than 200 checks to assess the quality and suitability of an IP for integration into an SoC. It has automated and integrated viewing, debugging, and reporting capability. Also, it provides user-induced waiving for particular rules to prevent unwanted checks, thus accelerating the consistency validation of an IP. The Crossfire also provides APIs for users to create their own custom checks for particular IPs.

    Checking IPs is not as simple as it appears to be. A typical problem faced by designers is to maintain consistency among various formats encompassing different IPs and their integration into an SoC. The complexity of SoCs, IPs in various forms from third party suppliers across the world, and different levels of design abstractions and validations have led to significant increase in the number of formats to be supported at each level in the design flow. It’s essential that the consistency between these formats is maintained to avoid unnecessary iterations in the design flows. Consider the diagram below which represents several aspects of an IP, each represented in multiple formats and databases.


    TheCrossfire supports each of these formats and checks for consistency between different aspects of an IP to ensure its integrity at all levels. The sheer number of views including functional representation, netlist, timing, power, reliability, layout, and test makes it really a difficult task to check the consistency at each level. It needs automated tool like Crossfire. The deep sub-micron processes have introduced another level of complexity to manage manufacturing variability at the design level, adding a few more formats to represent variability in the design flow.

    The Crossfire ensures that the information represented across these views is consistent and does not contain any anomaly. In case of any mismatches or even modeling errors, Crossfire promptly reports it. A timely correction of such errors saves a lot of debugging and rework later during SoC integration. The Crossfire has a very easy-to-use GUI with graphical debugging, filtering, viewing and several other features for quick investigation into a design. There is automatic setup for batch runs as well. The existing customer scripts can be easily integrated into Crossfire environment. Also, there are APIs for creating database independent checks.

    As it is evident, in today’s SoC and IP environment new formats keep evolving. The Crossfire has a robust methodology for adding new format support in its IP validation scheme. The detail about this methodology is given in a whitepaper at Fractal website. In the first half of this year, Fractal had added support for several new formats including APL, UPF, CTL, and AOCVM into Crossfire for IP validation. Most recently, it has added support for Spice v2lvs variant.

    Along with the new format addition, Crossfire keeps adding a number of new rule checks with respect to the new format as well as existing formats as the checks are discovered internally at Fractal or during various IP checks at customer sites.

    A tool like Crossfire can be relied upon for checking the quality and consistency of an IP before its integration into an SoC, thus shortening the overall SoC design schedule. Also, by using this tool the SoC integration schedule can be made more predictable.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com

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    How to prevent execution surprises for Cortex-M7 MCU?

    How to prevent execution surprises for Cortex-M7 MCU?
    by Eric Esteve on 08-06-2015 at 11:00 am
    Categories: Arm, Foundries, IP

    ARM Cortex-A series processor core (A57, A53) are well known in the high performance market segments, like Application Processor for smartphone, Set-Top-Box or networking. If you look at the electronic market you realize that multiple applications are cost sensitive and doesn’t need such high performance processor core. We may call it the embedded market, even if this definition is vague. The ARM Cortex-M family has been developed to address these numerous market segments, starting with the Cortex-M0 for lowest cost, the Cortex-M3 for best power/performance balance, and the Cortex-M4 for applications requiring digital signal processing (DSP) capabilities.

    For the audio, voice control, object recognition, and complex sensor fusion of automotive and higher-end Internet of Things (IoT) sensing, where complex algorithms for audio and video are needed for rich audio and visual capabilities, Cortex-M7 is required. ARM Ltd. offers the processor core as well as the Tightly Coupled Memory (TCM) architecture, but ARM licensee like Atmel has to implement memories in such a way that the user can take full benefit from the M-7 core to meet system performance and latency goals.

    In a 65nm embedded Flash process device, the Cortex-M7 can achieve a 1500 CoreMark score while running at 300 MHz, offering top class DSP performance: double-precision floating-point unit and a double-issue instruction pipeline. But algorithms like FIR, FFT or Biquad need to run as deterministically as possible for real-time response or seamless audio and video performance. How to best select and implement the memories needed to support such performance? If you select Flash, this will require caching (as Flash is too slow) leading to cache miss risk. SRAM technology is a better choice as it can be easily embedded on-chip and permit random access at the speed of processor.

    Peripheral data buffers implemented in general-purpose system SRAM are typically loaded by DMA transfers from system peripherals.

    The ability to load from a number of possible sources, however, raises the possibility of unnecessary delays and conflicts by multiple DMAs trying to access the memory at the same time. In a typical example, we might have three different entities vying for DMA access to the SRAM: the processor (64-bit access, requesting 128 bits for this example) and two separate peripheral DMA requests (DMA0 and DMA1, 32-bit access each). Atmel has get round this issue by organizing the SRAM into several banks as described in this picture:

    For chip maker designing microcontroller, licensing ARM Cortex-M processor core provides numerous advantages. The very first is ubiquity of ARM core architecture, being adopted in multiple market segments to support variety of applications. If this chip maker wants to design-in a new customer, the probability that such OEM has already used ARM based microcontroller is very high, and it’s very important for this OEM to be able to reuse existing code (we know the heavy weight linked with software development, in the 60% to 70% of the overall project cost). But this ubiquity generates a challenge: how to differentiate from the competition when competitors can license exactly the same processor core?

    Selecting a more aggressive technology node, providing better performance at lower cost is one option, but we understand that this advantage can disappear as soon as the competition also move to this node. Integrating larger amount of Flash is another option, very efficient if the product is designed on a technology allowing to keep the pricing low enough.

    If the chip maker has designed on an aggressive technology node, allowing providing higher performance and offering larger amount of Flash than the competition, it may be enough differentiation. Completing with the design of a smarter memory architecture unencumbered by cache misses, interrupts, context swaps, and other execution surprises that work against deterministic timing allow bringing strong differentiation.

    If you want to more completely understand how Atmel has designed this SMART memory architecture for the Cortex-M7, I encourage you to read this white paper from Jacko Wilbrink and Lionel Perdigon “Run Blazingly Fast Algorithms with Cortex-M7 Tightly Coupled Memories”. (You will have to register).

    This paper describe MCUs integrating an SRAM organized into four banks that can be used as general SRAM and for TCM, showing one example of a Cortex-M7 MCU being implemented in the Atmel® | SMART SAM S70, SAM E70, and SAM V70/1 families.

    By Eric Esteve from IPNEST

    More products and design kit on Atmel Sales portal:


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    Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?

    Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?
    by Paul McLellan on 08-06-2015 at 7:00 am
    Categories: CLK Design Automation, EDA

    During synthesis and static timing the main figure of merit is “slack”. If a signal arrives with time to spare before it is needed (often measured against the setup time before a clock changes at a register) then the slack is positive. Positive slack is generally a good thing, although it can indicate over-design if it is large. If a signal arrives late then the slack is negative. Obviously, the goal for signoff is to have all slack positive or zero.

    Signal timing is actually measured against timing constraints. These come from two sources. One is the user who can specify things like the clock frequency or timing limits at output pins. These basically let the user express the desired behavior of the design. The other source is the cell library where the characterization data is captured. Particularly important are the setup and hold times for flipflops and latches. A further complication is that these checks need to be performed at several process “corners”, traditional ones such as FF and SS but for a modern process, at many other temperature, voltage and process conditions too.

    Measuring slack for ultra-low voltage operation—below 0.7V—brings additional challenges, especially process variance. Paths that appear to pass timing within a corner may fail when process variance is included. Even at older process nodes such as 55nm or 65nm, process variance within a PVT corner can show up when the threshold voltage is severely reduced.

    The set-up and hold timing checks that are pre-characterized for flip-flops, latches and registers in a cell library are especially vulnerable to variation. Process variance has as much impact on the timing constraints as it does on delay variation. In fact, the corner timing constraints for lower voltages may be extremely optimistic and hide timing violations. They are overstating the timing slack in the design.

    During the medieval ages of chip design the solution was always to trade off any lack of accuracy with pessimism. How bad can it be? Use that number. But in a modern process, that doesn’t work. Often it will prove impossible to close timing with “that number” because there isn’t enough timing headroom to waste a lot of it on pessimism. Plus “that number” varies depending on corner, temperature, load, slew-rate and so on. Lack of accuracy has to be fixed by increasing accuracy.

    The Liberty Variation Format (LVF) supports an approach known as constraint uncertainty. This adjusts the timing constraints to reflect the impact of process variation on a very granular basis: each slew/slew constraint condition gets a unique value. Constraint uncertainty makes sure that margin gets added in exactly the right places, and with the level of conservatism the user specifies to protect against critical set-up and hold violations. By combining constraint uncertainty with arc/load/slew specific delay variance (also supported by LVF) engineers can close timing with much higher confidence and precision. There are other approaches, such as adding values direct to the .lib timing library, but they suffer from various limitations.

    Timing constraints, like the delay tables for the libraries, have traditionally been characterized at the process corners: SS and FF. They do not use the global corners SSG/FFG and then add in local on-die variance. However, process variation can affect the transistors inside of a flip-flop or latch just as much as they do the gates along a data or clock path. Engineers are often shocked to see that delay can swing by as much as 2X or more on a cell because of process variation.

    For example, the diagram above shows the setup constraint for a 20nm flipflop measured at 1V (in green). It also shows the constraint measured at the SS corner (one of the places where cells are normally characterized) versus SSG+3σ (the red vertical dashed lines). There is considerable pushout, the constraint is optimistic. Turning to the 0.65V characterization (in blue) there is an even larger pushout (to the red dotted line). The constraint is very optimistic and so will overstate slack. What looks like a reassuring positive slack may well be negative slack, a recipe for a chip that doesn’t work.

    There are two approaches to generating constraint uncertainty values: Monte Carlo (MC) SPICE or CLKDA’s Variance FX. All of the MC SPICE based approaches depend on sampling. Simulating a flip-flop is time consuming at best; simulating it 100’s of times or 1000’s of times for accuracy at low voltage, can be prohibitively slow. Variance FX, the industry leading solution for variation characterization can be hundreds of times faster than MC SPICE. The FX model and simulator solve for variance without any sampling and are typically within ± 2% of MC SPICE for nominal ± 3σ. Variance FX supports the classic approaches for constraint uncertainty, and has multiple options for characterizing constraints efficiently.

    The bottom line: traditional corner based constraints are very optimistic, and will overstate timing slack. Paths that appear to be passing may be failing, and by a lot. Positive slack may be negative. Working chips may…not.

    The CLKDA white paper The Impact of Process Variance on Timing Constraints and Slack at Ultra Low Voltage is here.