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Reusable HW/SW Interface for Portable Stimulus

Reusable HW/SW Interface for Portable Stimulus
by Pawan Fangaria on 06-03-2016 at 7:00 am
Categories: EDA, Events

Although semiconductor community has ushered into the era of SoCs, the verification of SoCs is still broken. There is no single methodology or engine to verify a complete SoC; this results in duplication of efforts and resources for test creation and verification at multiple stages in the SoC development, albeit with different verification engines. Considering the breadth and depth of verification required for an SoC, there does not seem any other alternative than going through the rigorous process of verifying the SoC with multiple engines in different situations.

Does that leave us spending exponentially in testing and verification of ever growing SoCs forever? It’s time we find innovative ways to curtail duplication at various levels of testing activities. What if the test-case generation is automated and reused across various SoC stages and verification engines? We would need automated and reusable hardware-software interfaces for actual execution of those test-cases too. So, where do we stand? The good news is that things in this direction are progressing more rapidly than I could anticipate.

One of the goals of Accellera’s Portable Stimulus initiative is deploying software driven verification by enabling specification of test scenarios that are verification platform agnostic. The generation of test-cases from different scenarios can be automated and mapped to different verification platforms. This methodology seems promising for reuse of test scenarios at block, IP, and SoC level as well.

A key consideration and complexity in the software driven verification methodology comes when a driver has to be implemented for actual execution of a test on a desired verification platform. This part of the hardware-software interface (HSI) development has remained largely manual. One can imagine the amount of resources, time, and effort being spent in this activity, duplicated for every environment as shown in the figure below:


Vayavya Labshas proposed a novel methodology for automating the driver development. This methodology revolves around capturing the hardware-software interface specificationsand run-time specifications in standard formats and generating the drivers for multiple operating environments through automated tools. Automatic driver generation meets a critical need in ensuring the generated test cases run on different verification platforms seamlessly.

Vayavya’s HSI technology is already in use in the electronic and the semiconductor verification industry. Customers have adopted Vayavya’s methodology in their flow where they transform their device specifications to Vayavya’s standard DPS (Device Programming Sequence) format. And by specifying run-time environment in a standard RTS (Runtime Specification) format and using Vayavya’s DDGen (a versatile tool for device driver generation) they can generate drivers for any operating environment such as SystemVerilog driver for verification, BareMetal C driver for validation, and SystemC driver for virtual platform. The generated SystemVerilog drivers are interoperable with UVM (Universal Verification Methodology). Customers treat the HSI specification as a golden specification without leaving any ambiguity in communication between various stakeholders in the team including architects, designers, verification and validation engineers, software engineers and so on.

Also, the HSI methodology is being adopted in larger semiconductor ecosystem of software driven verification tools. While a standard representation enables specification of reusable test scenarios, HSI would additionally enable specification of reusable drivers, thus ensuring the execution of test on any desired verification platform. Vayavya is an active contributing member and is leading standardization of HSI in Portable Stimulus Working Group (PSWG) setup by Accellera.

Cadenceis a leading player in the semiconductor EDA industry for software driven verification tools and methodology at system level. Perspec[SUP]TM[/SUP]System Verifier is a major contribution from Cadence for software driven verification. It provides a complete environment for generating system level test-cases from use-case specification.


In the Perspec flow, actions of design components typically consist of an “exec body” that makes calls to driver APIs for test execution. Before Vayavya’s technology, users had to separately provide the driver implementation for different verification platforms. Vayavya introduced DDGen which takes programmer’s view of the device as input in DPS format and a few lines of code to define run-time environment in RTS format, and automatically generates drivers for different platforms.

One can imagine how this level of automation for test-case generation and execution on multiple verification and validation platforms can enhance verification productivity by an order of magnitude. The DDGen integration with Perspec makes it easy and efficient to deploy for system level verification of SoCs. The Perspec – DDGen integrated solution for system level test-case generation and execution has been verified in a post-silicon environment on Zedboard consisting of Xilinx Zynq 7000 SoC.

The Perspec – DDGen integration will be presented by Vayavya at 53[SUP]rd[/SUP] DAC in Cadence Theatre. Attend the following session to know more about Perspec System Verifier, DDGen and the new methodology for software driven verification –

Date/Time: 7[SUP]th[/SUP] June 2016, 2 PM
Venue: Cadence Theatre in 53[SUP]rd[/SUP] DAC at Austin, TX
Topic: Software-Driven Validation: Using Perspec System Verifier and DDGen

More Articles by Pawan

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IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward

IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward
by Scotten Jones on 06-02-2016 at 4:00 pm
Categories: Events, FD-SOI, FinFET, Foundries, GlobalFoundries

IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.

Gary Patton is the Chief Technical Officer and Senior Vice President of Worldwide R&D at Global Foundries. Gary was part of a panel discussion during the “Scaling is dead. Long live scaling” session, he then delivered a keynote presentation entitled Moving the Electronics Industry Forward: Technology Enablers for the Next Wave of Growth and finally I had the opportunity to interview him. In this blog I will discuss Gary’s presentation and my follow up interview. I will blog about the panel discussion separately. I will start with Gary’s keynote and then discuss our interview which gave me an opportunity to follow up on some of the points from his talk and also touch base on Global Foundries progress since I last interviewed him in November 2015.

My blog on our November 2015 interview is available here.

Technology Enablers paper:
Traditional growth drivers are flat, PCs are down and mobile growth has slowed. The semiconductor industry has gone through many transitions in the past. Corporate computing, military and telecommunications drove the industry from 1965 to 1985, from 1985 to 1995 it was the PC/smart client, from 1995 to 2005 we saw internet, gaming consoles and e-commerce, and from 2005 to 2015 we saw mobile as a driver. What will be the next driver? We have also seen technology transitions from bipolar to CMOS, the introduction of high-k metal gates (HKMG) and strain and then FinFETs have carried us for a few years and will carry us for a few more years.

He thinks 5G will be as disruptive to mobile as data was. Mobile with 5G allows massive connectivity and video download and upload. Internet Of Things (IOT) wearables nearly doubled this year, it will fuel connectivity and 5G. Autonomous cars are coming, there is $350 of semiconductors in a car today, that will grow substantially. Autonomous cars can reduce the number of required cars and urban parking lots. IOT is projected to be $50 to $75 billion dollars in the 2019-2020 time frames. All of those devices will generate data that has to go into the cloud. Data volumes are increasing 25% per year and data centers double every three years.

There is a need for innovation. It used to be that when you scaled down you got cost, performance and power but today you don’t get all that. You can still drive down cost but it is getting exponentially more expensive to develop. Most key technologies were in development for at least ten years. FinFET electrostatics are limited and will likely transition to nanowires and vertical FETs with FDSOI as an option for low power applications. Highly integrated optics will be needed for shorter copper lines.

The transition to fully depleted FinFETs gave us lots of drive current for large chips, FDSOI is an option for low power. We need to optimize the power/cost trade off. A 14nm FinFET design is 2.5x the cost of a 28nm planar design. FDSOI gives a lower cost design option that you can forward bias for performance or reverse bias for power. You can dynamically control the bias with software and FDSOI provides easy integration of analog and RF.

Photonics has moved from 180nm with integrated photonics to 90nm this year and 65nm interposers with integrated photonics are in the works.

EUV will be in manufacturing by 2020 or sooner. Better power (200 watts has been shown), better photoresist sensitivity and pellicles, Gary expects 7nm to be a long lived node and EUV will be inserted when ready. I will discuss this more in the blog on the panel discussion but Gary noted that we may not take full advantage of the technology at least initially. Inserting EUV can reduce 30 masks to 10 masks and at 1.5 days per mask layer save 30 days of cycle time.

He thinks packaging is a big opportunity. Over the time that silicon has improved by 1000x package sizes have been reduced by 3x.

Collaboration will be key, Global Foundries is engaged with CNSE, IMEC, IBM, EDA and Universities. They have FDSOI, MRAM, RF-SOI and SiGe, FinFETs, Advanced Packaging and ASICs. They also have 5 manufacturing centers on 3 continents.

Later the same day I got to sit down with Gary for a follow-up interview.

As we discussed at our previous meeting in November 2015, Gary discussed that execution had been an issue in the past and they are really pushing hard on that. They have implemented a technology council to break down barriers, they also do milestone reviews where they bring in experts from around the company to do technology deep dives and that is really paying off. 22 FDSOI has hit all of its milestones and is ahead on yield. Full production is expected in 2017 with risk production at the end of 2016. 14nm is also hitting all of its milestones, yields are good and there are a ton of tape-outs. 14nm went into production earlier this year.

They are working on 10nm but focused on 7nm. They haven’t announced whether they will do 10nm. He did mention that some customers have told them they will skip 10nm for 7nm. My understanding is that 10nm is a kind of intermediate node mostly targeted at Cell Phones Applications Processors. That isn’t a big segment for Global Foundries so personally I wouldn’t be surprised if they skipped 10nm and went right to 7nm, but Gary wouldn’t comment on this yet.

One comment I found really interesting is they are using EUV for non-transistor layers to save development time by avoiding all the processing for multi-patterning. Cycle time is coming up a lot in discussions lately because of all of the process complexity we are seeing. He also noted that the bar is getting lower for EUV because you can take out so many multi-patterning cut/block masks with a single EUV exposure. He thinks EUV will be used at contact and via first and for block masks on metal layers. They are currently doing an 80 watt upgrade on the Albany EUV tool.

The RF business is doing well and they are putting a lot of money into it. Gary just sent one of his best RF experts to Dresden to support RF on the 22FDx process. RF is very hard to do with FinFET because you can only add fins in discrete increments. They are working on a next generation FDSOI technology but haven’t put a number on it. He thinks 22nm FDSOI design costs are similar to 28nm design costs (versus 2.5x for 14nm FinFETs as mentioned above). FDSOI has lower capacitance than FinFETs and small IOT chips are capacitance dominated. They are getting a lot of interest. They are building up IP working with Invecas and ARM is really starting to focus on FDSOI.

Their ASIC business is leveraging their 14LLP process and getting a lot of traction. 5G will touch many sites and will use a wide range of technologies, including 7nm.

Global Foundries will do FinFETs for 7nm but he doesn’t think you can do FinFETs beyond 7nm. He thinks horizontal nanowires are next. There may be a “shrink” of 7nm FinFETs but the dimensions won’t shrink much, it may just be implementing EUV.

Also read: IMEC Technology Forum (ITF) – EUV When, Not If

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iDRM – A Complete Design Rule Development System

iDRM – A Complete Design Rule Development System
by Daniel Nenni on 06-02-2016 at 12:00 pm
Categories: EDA, Sage DA

Design rules are at the heart of the interface between the foundry and semiconductor designers, which makes them so critical. Traditionally, design rules and DRC decks have been developed manually with no or little automation. Design rule definitions are written using WORD or other general purpose office tools, and DRC decks are programmed in an attempt to match that text definitions. This state of affairs leaves many challenges, such as:

  • How do you verify that the DRM (design rule manual) rule definition accurately represents the rule intent?
  • How do you ensure the definition is complete and unambiguous?
  • How do you verify that the DRC code exactly matches the DRM definition?

So far, there have not been good solutions to these challenges, which resulted in a host of issues ranging from baffled designers, through delayed product ramps and all the way to product yield catastrophes.

iDRM from Sage-DA
Sage made its mission to tackle that problem and introduce automation to all stages of design rule development. This year at #53DAC they will demonstrate a complete system that connects all these dots: starting with design rule capture by the process integration team and delivering a compiled and verified DRC deck that accurately matches and represents the design rule intent.


The iDRM system consists of:
1. Design rule capture: GUI based rule entry tool which supports drawings, logic expressions, tables, etc.. Captured rules are executable and can check design examples right away to test the definitions and make sure they accurately express the intent.

2. DRC reference: Once the rules are captured, iDRM becomes the reference checker for DRC deck developers and early access PDK users. The iDRM rule-set accurately represents the design rule intent. It becomes the executable reference for the development and verification of DRC decks.

3. Electronic DRM: Once a set of rules has been captured, the user can view them in the form of an Electronic DRM, or use the tool to publish a traditional DRM copy. The design rule definitions in this DRM are formal, clear, unambiguous and complete.

4. Compiled DRC deck: iDRM enables automatic generation of DRC code by associating DRC code snippets with template rule definitions. For each design rule, iDRM generates the corresponding DRC code using the correct information such as, conditions, layer definitions and all other details. This eliminates errors and ensures consistency between the DRC deck and the DRM.

5. DRC deck verification and coverage: For each rule, the system automatically generates a set of passing and failing layout test cases. These test cases are used to test DRC code. iDRM also provides coverage metrics for these test cases.


Additional functionality:
6. Design Rule Extraction from existing layout: iDRM can extract design rules from a GDS data file and automatically create a design rule manual and DRC check for technologies that do not have proper design rule documentation.

7. Pattern extraction and classification: iDRM can now scan an entire design and extract all existing patterns, sort them and build a complete pattern library for every layer or combination of layers. Using this pattern library, iDRM can then scan any new design and indicate unknown patterns that are not in the pattern library.

Sign up for a demo at #53DAC and meet the Sage-DA team: http://www.sage-da.com/dac-2016.html

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Layout Pattern Matching for DRC, DFM, and Yield Improvement

Layout Pattern Matching for DRC, DFM, and Yield Improvement
by Tom Dillinger on 06-01-2016 at 12:00 pm
Categories: EDA, Samsung Foundry, Siemens EDA

It is truly amazing to consider the advances in microelectronic process development, using 193i photolithography. The figure below is a stark reminder of the difference between the illuminating wavelength and the final imaged geometries. This technology evolution has been enabled by continued investment in mask data generation (including multipatterning decomposition) and exposure optimizations, generally known as computational lithography.
Continue reading “Layout Pattern Matching for DRC, DFM, and Yield Improvement”

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Go Native – With Methodics at DAC in Austin

Go Native – With Methodics at DAC in Austin
by Tom Simon on 06-01-2016 at 7:00 am
Categories: EDA, Events, Perforce

DAC is often a yearly reflection point for the companies that exhibit and attend. For the innovators it is an opportunity to look back and see a year of progress and development. Fortunately, this is the case for Methodics, which has had a strong year both in terms of business and technical development. Though, we easily see how these two things will frequently go hand-in-hand.

Recently my former colleague Michael Munsey joined Methodics as VP of Business Development and Strategic Accounts. He shared with me some of the main points that Methoidics will be highlighting at DAC in Austin the week of June 6[SUP]th[/SUP]. As you know I have been writing about Methodics since last year, and during this time I have had a number of engaging conversations with their CEO Simon Butler. So most of what they are featuring this year may not come as a surprise.

However, Methodics is leading this year by breaking the tedium of the ubiquitous DAC technical pitches with twice daily Hawaiian dance performances at their booth. Yes, of course there is an underlying message. Unlike the other vendors in the IP and data management space they rely on native integrations with the underlying revision control system. Their tagline is ”Go Native.” They are betting that it will help you remember that theirs is not a proprietary integration that locks in design data.

To help them emphasize this message, they will also have representatives from Perforce with them in their booth at DAC. So this will be a good opportunity to learn more about adopting native Perforce.

For IP lifecycle management Methodics offers ProjectIC, which I have written about recently. At DAC this year they will be announcing a new version, ProjectIC 2.0, with many new features and capabilities. The focus of this release is Platform Based Design. Along with this there is a performance speed up and richer API’s for enhancing the integration of ProjectIC into your design environment. Look at their website for a white paper that goes into greater detail on how ProjectIC 2.0 facilitates Platform Based Design.

For heavy duty data and IP management needs, Methodics offers WarpStor, which is an unusual offering for a company in this space. WarpStor is a hardware appliance that optimizes access to the design data through the IP and data management system. The beauty of it is that it is transparent to the OS and uses the data already stored on existing file servers. At DAC this year Methodics will be talking at length about WarpStor and how it is used to optimize workspace size, bandwidth and overall storage needs.

The other big news that Methodics will be talking about at DAC is their recent partnership with Magillum. The team at Magillum are experts on IP-XACT, otherwise known as IEEE 1685. IP-XACT is a concrete and standardized method of managing IP so that it can be stored, integrated and qualified systematically and in a way that makes it interoperable across different tool chains. IP-XACT is an excellent example of the application of XML to the semiconductor design space. Because Methodics focuses on IP lifecycle management, this partnership looks very synergistic.

If you want to learn more about any of the topics mentioned above, or if you just want to get away from the humdrum of technology pitches and would rather see traditional Hawaiian dances, be sure to swing by the Methodics DAC booth during the week of June 6[SUP]th[/SUP] in Austin. Methodics talks further about their DAC offering and demos here on their website.

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TSMC Update at #53DAC!

TSMC Update at #53DAC!
by Daniel Nenni on 05-31-2016 at 4:00 pm
Categories: Events, FinFET, Foundries, TSMC

TSMC is having an interesting year for sure. I was at the TSMC Symposium in Hsinchu last week and everyone was talking about the new 16FFC process. Silicon is out and it is exceeding expectations leading some people (me included) to believe that TSMC 16FFC will be the next TSMC 28nm in regards to popularity. To be clear, 16FFC is currently the “BEST” process node in regards to PPPA (price, performance, power, and area) available today, absolutely.

The proof is in the pudding of course and that pudding will arrive via the iPhone 7 this fall and yes, I am buying an iPhone 7 Pro to match my iPad Pro which I use every day. Netflixing on an iPad Pro at 30,000+ feet, priceless! It should have a “TSMC Inside” sticker on it for sure.

Speaking of FinFETs, we have published 64 FinFET related blogs thus far starting with Tom Dillinger’s three part Introduction to FinFET Technology series. The total views for the SemiWiki FinFET blogs exceeds 500k which is a lot of reading. FinFET blogs also have low bounce rates and high time-on-page numbers which means they are very engaging. Designing with FinFETs is still a hot topic so there are certainly more blogs to come.

At DAC, TSMC pioneered the partner theater allowing the fabless semiconductor ecosystem to shine, and this year it will be no different. You can see the latest TSMC Theater schedule HERE. If you are looking for me on the DAC exhibit floor that would be a good place to start. Or wherever there is free food.

Speaking of free food, TSMC is also very busy with other DAC activities that should be of interest. You can see the agenda HERE and please note that it includes breakfast, lunch, and dinner presentations so you can also find me there enjoying the free food.

As a pre #53DAC “Designing with FinFET” primer you should catch the TSMC and Solido Collaborate for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes webinar on Wed, June 1st, 2016 10:00 AM – 11:00 AM PDT. If the time does not work for you, sign up anyway and they will send you a link to the replay:

“Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule.

This webinar will discuss how TSMC and Solido collaborate to offer variation-aware design techniques for memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.”

And don’t forget that SemiWiki will again be hosting a DAC Networking reception on Wednesday night from 6:00pm to 7:00pm in the Trinity Street Foyer. This year we will be giving away copies of our new book “Prototypical”. My beautiful wife and I hope to see you there!

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Bringing Human-Like Intelligent Vision Processing to Low-Power Embedded Systems

Bringing Human-Like Intelligent Vision Processing to Low-Power Embedded Systems
by Daniel Nenni on 05-31-2016 at 12:00 pm
Categories: Ceva, IP

Semiconductor IP has always been one of the most interesting topics on SemiWiki. Since going online in January of 2011 there have been a total of 592 IP related blogs that have been viewed 2,581,118 times. 79 of those blogs have been about CEVA, the number one licensor of digital signal processing (DSP) IP for a wide range of power-efficient, intelligent, and connected devices for Mobile, consumer, automotive, industrial and IoT applications. You can see the full list of SemiWiki Semiconductor IP blogs HERE and CEVA blogs HERE. CEVA specific traffic on SemiWiki is second only to ARM in our IP category. CEVA is also very good at Infographics!

Bringing Human-Like Intelligent Vision Processing to Low-Power Embedded Systems

As you probably know, one of my strange hobbies is listening to quarterly investor calls of companies that I have intimate knowledge of. As an insider it is interesting to see if what I know matches up to what the company says publicly. Which brings us to CEVA, one of my favorite companies to watch because what they say actually matches what I know, absolutely.

CEVA had a great 2015 with:

  • Quarterly revenues of $16.1 million, up 16% year-over-year
  • Strong adoption of imaging & vision; five agreements for CEVA-XM4
  • Annual revenue growth of 17% year-over-year
  • Annual non-GAAP EPS growth of 51% year-over-year

Gideon Wertheizer, Chief Executive Officer, stated: “We are extremely pleased with our strong finish for the year, as both licensing and royalty revenues delivered year-over-year growth. In licensing, the adoption of our CEVA-XM4 imaging and vision DSP by five licensees during the quarter expands our footprint in the growing use of advanced camera processing in automotives, drones and smartphones. In royalties, our quarterly royalty revenues reached its highest total since 2012, driven by record CEVA-powered smartphone shipments of more than 92 million units.”

In Q1 2016 the CEVA success continues:

  • All time-high revenues of $16.5 million, up 19% year-over-year
  • GAAP and non-GAAP EPS growth of 350% and 113% year-over-year
  • Quarterly record of 35 million CEVA-powered LTE devices shipped

Yaniv Arieli, Chief Financial Officer of CEVA, stated: “In addition to another strong licensing quarter, our market share expansion in LTE continues, with a record thirty five million shipped units reported in the quarter, resulting in 31% year-over-year royalty revenue growth. Reflecting our confidence in our business, we repurchased approximately 180,000 shares of our common stock during the quarter for an aggregate consideration of approximately $3.4 million. At the end of the quarter, our cash balance, marketable securities and bank deposits totaled $137 million.”

You can meet with CEVA at the Design Automation Conference next week where they will be demonstrating in the BRITE Semiconductor booth (#1520). CEVA will show a new and exciting Deep Neural Network demo running on CEVA’s award winning Imaging Processor (CEVA-XM4). Hope to see you there!

About CEVA, Inc.
CEVA is the leading licensor of signal processing IP for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, industrial and IoT. Our ultra-low-power IPs for vision, audio, communications and connectivity include comprehensive DSP-based platforms for LTE/LTE-A/5G baseband processing in handsets, infrastructure and machine-to-machine devices, computer vision and computational photography for any camera-enabled device, audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For connectivity, we offer the industry’s most widely adopted IPs for Bluetooth (BLE and Dual Mode), Wi-Fi (802.11a/b/g/n/ac up to 4×4) and serial storage (SATA and SAS). Visit us at www.ceva-dsp.com and follow us on Twitter, YouTube and LinkedIn.

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Why USB 3.1 Certification is a “Must Have”?

Why USB 3.1 Certification is a “Must Have”?
by Eric Esteve on 05-31-2016 at 7:00 am
Categories: IP, Synopsys

USB 3 protocol is now height years old, but USB 3.1 is much more recent (2014). The adoption behavior for USB protocol is unique, as USB 2.0 bandwidth (480 Mbps) is largely enough for certain applications. Nevertheless we have seen the sales for USB 3 IP passing the USB 2 in value during 2014, and the total USB IP segment becoming the largest of interfaces segment in 2015.

USB 3.x IP sales are constantly growing and we can expect applications relying on USB 3.0 (5 Gbps) to upgrade to USB 3.1 (10 Gbps). When deciding to integrate complex interface IP running at 10 Gbps, the first question coming in the selection process is: has this IP passed the qualification? Because we are talking about interface IP, you a priori don’t know the quality of the USB IP your chip will interface with. The only way to make sure that both function will smoothly communicate is the qualification process, supported by USB-IF. Synopsys has announced that their DesignWare USB 3.1 controller and PHY passed all protocol, electrical and interoperability tests to become the first IP to achieve USB-IF certification. As we will see in this paper, this long process is all but an easy trip.

USB 3.1 Gen 2 significantly increases the effective data rate to 10 Gbps for the ubiquitous USB protocol, while maintaining backward compatibility with USB 3.0 and 2.0. USB 3.1, in combination with USB Type-C and Power Delivery. We have to keep it mind that a modern (interface) IP is no more a simple bunch of source code RTL: complete USB 3.1 solution includes controller, PHY, verification IP, IP subsystems, IP prototyping kits and IP software development kits.

Controller: The preparation for compliance testing starts together with the project schedule definition, and will apply to every phase of the controller development, helping to drive the schedule and collaboration process with the engineering teams involved in deliverables such as the PHY, simulation verification IP (VIP) models and software drivers. The ASIC design engineers task become a compliance-driven design approach.

PHY: The PHY testchip silicon will be exhaustively verified within Synopsys laboratories before going to certification, thanks to the PHY architecture which allows for the transmitter (TX) and receiver (RX) of the PHY to be operated standalone, with pattern generators and pattern matchers incorporated into the PHY itself.

Verification IP (VIP): The verification phase of a complex protocol such as USB 3.1 Gen 2 represents a paramount effort where constrained random regression approaches can take considerable time to go through thousands upon thousands of coverage points. Parallel efforts focused on direct test scenarios that address compliance test simulation environments are actively sought after to improve the process. For example, the link layer compliance test is a perfect candidate for writing direct test cases.

IP Prototyping Kit: FPGA-based prototyping provides cycle-accurate, high-performance execution and real-world interface connectivity. When the controller has been integrated in FPGA, the PHY Testchip has been mounted on the same board, the full IP Prototyping Kit, pre-compliance testing can begin.

Although the Synopsys methodology minimizes roadblocks and accelerates processes, it is Synopsys’ array of industry-tested tools and prototyping environments, along with its experienced team, that results in IP validation, verification, and compliance (see above Figure). Synopsys has proven its methodology by being the first IP companies to achieve certification for USB 3.1 Gen2.

The DesignWare USB 3.1 Controller IP implements power management features, including standard USB power savings modes and controller hibernation. DesignWare USB 3.1 PHYs consume less than 50 mW power at 10 Gbps speeds in 14/16-nm FinFET process technologies. The IP supports the IEEE 1801 standard Unified Power Format (UPF) for low-power SoC design flows. The controllers are backward-compatible with DesignWare USB 3.0 software stacks and device class protocols. No doubt that the complete USB 3.1 solution from Synopsys will allow the company to keep his leading position in USB IP segment with more than 80% market share in 2015!

– See more about Synopsys certification strategy and process at: http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-challenges-usb-certification-2016q2.aspx#sthash.j0wOVnaV.dpuf
– Synopsys PR about sertification: Synopsys’ 10 Gbps USB 3.1 IP First to Pass USB-IF Certification

From Eric Esteve from IPNEST