Bronco Webinar 800x100 1
Semiconductor Expert Forum

Posted on

OpenPOWER Keeps On Truckin’ At Annual Development Summit

OpenPOWER Keeps On Truckin’ At Annual Development Summit
by Patrick Moorhead on 06-06-2016 at 4:00 pm
Categories: EDA, Events

The OpenPOWER Foundation, a collection of companies that have coalesced around IBM’s POWER architecture recently had their OpenPOWER Summit in San Jose, California. OpenPOWER was founded by IBM, Google, Tyan and Mellanox to coalesce around IBM’s approach towards opening up the POWER architecture to anyone that wishes to license it or build their IP into it. IBM provided the CPU, memory and accelerator architecture and all of the other founding members provided some other component of HPC that was needed to create a complete solution.

IBM holds their OpenPOWER Summit every year in San Jose California alongside their partner NVIDIA in the same convention center with some overlap between the two. The OpenPOWER Foundation keeps making progress, year after year, and at this year’s OpenPOWER Summit, they moved even more steps closer to the deployment of complete OpenPOWER systems. IBM, Google, Rackspace (Rackspace Hosting) and others offered even more support, products and R&D towards the cause.


IBM’s VP of HPC and Data Analytics Sumit Gupta talks about what POWER brings to cognitive and data scene (Credit: Patrick Moorhead)

Google delivers on last year’s promises but doesn’t commit to deployment
At this year’s OpenPOWER Summit, one of the biggest moves forward came from Google in terms of an increased commitment and involvement compared to previous years. Google had previously announced motherboards using OpenPOWER and that they would port software. This year they announced that this porting was nearly complete with a “majority” ported to date. However, Google would not commit to deploying these systems en masse. Google’s decision on what compute they decide to use in their datacenter is purely based upon what Google’s Maira Mahony calls, “performance per TCO dollar.” According to Mahoney, for many of Google’s employees enabling POWER systems is merely a configuration change and doesn’t put too much of a burden on them to change.


Google’s Maira Mahony talks through what they have accomplished with OpenPOWER (Credit: YouTube)

Google also announced that they are developing a next-generation OpenPOWER and Open Compute Project form factor server. Google is working with Rackspace to co-develop an open server specification based on the new IBM POWER9 architecture and the two companies will submit a candidate server design to the Open Compute Project.

It’s not in Google’s best interest to do full deployment commit as it gives them better negotiation leverage with both Intel and OpenPOWER members.

Rackspace Hosting moving POWER8 to the data center and creates POWER9 server with Google
Rackspace announced that their ‘Barreleye’ OpenPOWER/Open Compute Project server has now moved from the “lab to the data center”. Rackspace anticipates that ‘Barreleye’ will move into broader availability throughout the rest of the year, with the first applications on what they call the “Rackspace Public Cloud powered by OpenStack”. Rackspace and IBM collectivity contributed the ‘Barreleye’ specifications to the Open Compute Project in January, 2016. The specifications were formally accepted by the Open Computer Project in February 2016.

This progress shows how many companies are working together to make OpenPOWER work in more than just a theoretical capacity, but in a truly competitive manner that could give the competition a run for their money. Rackspace’s own manage cloud computing platform could really stand to benefit from the increased performance from the OpenPOWER platform and added acceleration from a whole host of accelerators, be their CAPI-based accelerators or NVIDIA accelerators using NVLink. More performance per dollar could be better for a company like Rackspace who wants to deliver the best performance per dollar to their customers.

IBM doubles down with new LC servers
Added support from Google and Rackspace is extremely valuable to OpenPOWER but IBM’s contributions have been the most critical to OpenPOWER’s success since its founding. IBM, in collaboration with NVIDIA and Wistron, plans to release its second-generation of OpenPOWER HPC server, which includes NVIDIA’s Tesla P100 compute co-processors and NVLink interconnects as well as IBM’s POWER8 processors connected directly through NVLink. These systems will be available in Q4 2016. IBM also announced that they plan to add systems to their line of LC servers. IBM is planning on adding Open Compute Project-compliant systems to their POWER Systems LC portfolio for cognitive and big data applications. IBM’s plans are in addition to three other OpenPOWER Foundation members also announcing that they have plans for Open POWER-based Open Computer Project-complaint systems like Mark III Systems, Penguin Computing and Stack Velocity.

50 new OpenPOWER infrastructure announcements
In addition to the increased involvement from some of OpenPOWER’s biggest members, there were 50 new OpenPOWER infrastructure announcements from a broad range of members and partners. Bittware, IBM, Mellanox and Xilinx announced more than a dozen new Coherent Accelerator Processor Interface (CAPI) solutions. Alpha Data unveiled a new Xilinix-based FPGA CAPI hardware card at the summit as well. Edico’s DRAGEN processor which was developed in collaboration with Xilinx and IBM is based on Xilinx’s FPGA running on IBM’s POWER Systems LC class. Supermicro is also currently developing two new POWER-based servers for IBM which are based on the company’s ‘Ultra’ architecture and IBM intends to add them to their LC server line. Last but not least was Tyan, who announced their own POWER8-based server solution that is designed to fit into a 1U formfactor with planned availability in April, 2016.

Wrapping up
The OpenPOWER Foundation and their members have shown once again that the movement that OpenPOWER is continuing to gain steam and in many respects has eclipsed the ARM-based server initiative. The increased commitment from Google, Rackspace Hosting, IBM, NVIDIA and others clearly show that OpenPOWER is here to stay and that we are really starting to get close to a complete ecosystem built around OpenPOWER.

More announced products are showing that companies are investing real moneyinto developing products that they think will actually sell and not just for experimental purposes. Rackspace Hosting has said they will deploy their solutions into production, while Google hasn’t said they would but also hasn’t said that they wouldn’t and if the “percentage per TCO dollar” is better than Intel, then they say they will. Intel has many levers to pull, though and are masters at this game and don’t assume that any of this is “all or nothing”.

Things are really starting to get interesting for OpenPOWER and it will be interesting to see what further announcements we’ll see throughout the year.

More from Moor Insights and Strategy

Posted on

The chilling effect Peter Thiel’s battle with Gawker could have on Silicon Valley journalism

The chilling effect Peter Thiel’s battle with Gawker could have on Silicon Valley journalism
by Vivek Wadhwa on 06-06-2016 at 12:00 pm
Categories: General

Gawker infringes on privacy and publishes tabloid-like stories that damage reputations. It is one of the most sensationalist and objectionable media outlets in the country. It also has not been kind to me. So it’s not a company that I would expect to be defending. But I worry that the battle that billionaire Peter Thiel has clandestinely been waging against it will be damaging to Silicon Valley by furthering distrust of its motives.

For better or worse, Gawker is entitled to the same freedom as any other news outlet. If it crosses the line, as it likely did with wrestler Hulk Hogan, the courts should deal with it. Silicon Valley’s power brokers should not get involved because they have access to resources that rival those of governments. They can outspend any other entity and manipulate public opinion.

Silicon Valley has more than an unfair advantage; its technologies exceed anything that the titans of the industrial age had. These technologies were built on the trust of the public — and that is needed for an industry that asks customers to share with them with literally every part of their lives. This enormous influence should come with restraint and an understanding that those with power will be scrutinized — sometimes unfairly and unjustly.

What some may find particularly troubling is that Peter Thiel is on the board of Facebook — which has become the world’s most influential media platform. Facebook decides what news a billion people will see and controls a significant portion of the traffic to leading news websites. Publications’ entire businesses can be wiped out based on a change in its algorithm. Thiel is also chairman of the board of security firm Palantir Technologies, which provides intelligence data to the CIA and FBI, and an investor in many other powerful technology firms.

There is almost no chance that any of Thiel’s companies will use their technology to target his opponents and dissenters. But Thiel’s activism only increases concerns at a time when Facebook is under fire for having a perceived liberal bias. And there is only a temporary hiatus in the battles between the FBI and Apple over security and privacy. Silicon Valley doesn’t need another dark cloud hanging over it, yet one seems to be developing.

It’s not just journalists who are affected, the culture of the technology industry is at stake too. Silicon Valley prides itself on openness, diversity, and freedom of thought and expression. You can be competing one day and cooperating on another. Criticism is accepted and dissent is expected. It’s rare to read a story such as this where a prominent figure went to great lengths to silence an adversarial voice.

Other than Gawker’s tech website, Valleywag, which was shut down this year, there are few publications in Silicon Valley that will confront its tech moguls and overhyped start-ups. Witness the ethical breaches committed by Theranos; lives were put at risk. Yet it took an exposé by John Carreyrou of the Wall Street Journal to uncover its corruption. And he had to withstand ugly threats by the company’s lawyers.

Technology businesses should be focused on their credibility and building trust by making their executives more accessible to journalists, not battling media organizations.

As Nick Bilton wrote in Vanity Fair, the valley’s system “has been molded to effectively prevent reporters from asking tough questions. It’s a game of access, and if you don’t play it carefully, you may pay sorely. Outlets that write negatively about gadgets often don’t get prerelease versions of the next gadget.

Writers who ask probing questions may not get to interview the CEO next time he or she is doing the rounds. If you comply with these rules, you’re rewarded with page views and praise in the tech blogosphere. And then there’s the fact that many of these tech outlets rely so heavily on tech conferences.” Investor Jason Calacanis added, “If you look at most tech publications, they have major conferences as their revenue. If you hit too hard, you lose keynotes, ticket buyers, and support in the tech space.”

Technology is the industry of disruption — and that makes people wary. There is growing anxiety everywhere over what will be next to change. As it becomes a greater part of the economy, checks and balances are needed more than ever. The risk is that Thiel’s attempt to quash a reprehensible publication will only weaken what little exists.

For more, visit my website: www.wadhwa.com and follow me on Twitter: @wadhwa

Posted on

Intel’s New Strategy Is The Right One For The Company

Intel’s New Strategy Is The Right One For The Company
by Patrick Moorhead on 06-06-2016 at 7:00 am
Categories: Foundries, Intel Foundry

Intel has been the focus of a lot of attention in the last week due to the company’s major restructuring announcement which came on the heels of Intel’s most recent earnings announcement. The majority of analyses that immediately followed the company’s announcement focused singularly on the layoffs, which amount to 11% of the workforce or 12,000 employees, insinuated that Intel is walking away from the PC and asked questions about what this means for the future of the Intel. I know I did. I didn’t have to wait long for an answer.

CEO Brian Krzanich followed up within the week with a blog further clarifying the strategy. It was a clear attempt to give a layman’s explanation of what Intel is trying to do. I still wanted more information so I followed up with a conversation today with Intel’s most senior management and got even more clarity about the company’s future, including its commitment to the PC market and how mobility fits into its new strategy.

Here’s my revised take on Intel’s restructuring and new strategy following that conversation. Intel believes its future lies within the coregrowth areas of cloud and data center, IoT (Internet of Things), memory and programmable solutions. These growth areas shouldn’t be confused with business segments, however. That’s what tripped me up at first – and why at first blush others may be asking “where’s the PC?” in Intel’s new strategy. I personally thought the growth areas were the company’s priorities, and took data center, for instance as the #1 priority. That wording, I believe, may have been misunderstood as Intel pivoting away from the PC market.

Intel’s PC division, its biggest revenue and profit dollar division, is now managed by Murthy Renduchintala, who was brought in late last year to align the design, engineering, software enabling and focus Intel’s strategy and execution across the company’s client (Intel speak for PC and mobile devices), communications, device and IoT segments. In combining these divisions under one roof, Intel’s wants continued and aggressive innovation in its PC business to drive innovation across the fast-growing IoT category. Krzanich called the PC a connected “thing” in his strategy blog. This actually makes sense to me since the PCs was one of the first smart and connected devices that is now foundational to make up the burgeoning category of the IoT. There are a big variety now of compute-connected “things”.

It’s important to understand that the PC business is still the bedrockthat Intel is based on and currently determines how much of the company’s core IP and innovations evolve and drive significant fab scale. Ultimately, without the innovations and scale in the PC space, many of Intel’s most profitable technologies today simply wouldn’t be possible. That was true before and that’s true now.

The size of the PC market has been flat to decreasing, but Intel has maintained more than solid profitability in that sector, contrary to many others in the PC sector. In fact, Intel sees certain segments of the PC as valuable places to invest further like 2 in 1s and gaming, which are experiencing explosive growth. Right now as “things” stand, Intel’s biggest revenue base and profit base both come from the PC sector. To abandon that makes no sense.

Make no mistake – the company is also taking a bullish focus on the cloud and data center. That’s just a smart move. Intel’s cloud growth focus is based on the idea of supporting the expansion of virtualization and analytics which are driving major data center and cloud growth. Intel’s memory and programmable solutions are also a huge growth potential for the company as many people recognize. With technologies like FPGAs, Rack Scale Architecture and 3D XPoint memory technologies, they all offer both short term and long term growth as the industry starts to move toward more accelerated computing models that utilize faster storage and co-processors. It also increases to market basket for Intel. These innovations also have a lot of potential to help Intel to continue to push forward in the cloud and data center and are very complementary across nearly all of Intel’s other core growth areas. Intel will still need to figure out how to counter the growth in GPU-based accelerators in areas such as the DNN (deep neural network) space.

Mobility is also still critical to Intel’s growth – and what we see is the chip giant reprioritizing and reallocating manpower and resources in order to further push into areas that make sense, like their long term 5G initiatives and connectivity strategy. Intel is doing this as a part of the restructuring and as they had mentioned before, they would be looking at certain projects and evaluating their feasibility. I have participated in these excruciating reviews at former employers and they’re like cough syrup… it tastes horrible going down, but it needs to be done. My favorite “endearing” term that my teams used were ‘hairball.” We had to figure out the giant “hairball”.

As a result of these reviews, I learned today that Intel’s senior management has determined that they will be ending their SoFIA projects (specifically 3Gx, LTE, LTE2) as well as their Broxton SoC for smartphones and tablets. The cancellation of these projects is intended to free up Intel’s resources to refocus their brainpower on their modem technology and 5G efforts. Intel has been showing some serious commitments to 5G deployment and penetration in the future, and they clearly believe that 5G is their opportunity to carve out a competitive advantage for themselves end to end in the future of mobility and in connecting the growing number of smart and connected ‘things’ to the cloud. From my vantage point, Intel has a better chance in 5G than they do in low-end 4G mobile devices. While I would have more confidence in this strategy if they had significant 4G installations, I also know Intel is much further ahead on 5G than they were with 4G at Infineon which, frankly, I believe led to Infineon losing the Apple 4G business years ago.

With Intel’s refocused efforts on 5G and commitments to profitable segments of the PC and its continued development, I think we are going to start to see a very different Intel.

Intel’s new strategy is the right strategy for the company, and I don’t take those words lightly. My perspective comes from over 25 years of engagement with them, as their largest customer in the 90′s, competitor in the 00′s, and now researching them and their ecosystem as an analyst in the 10′s. Some of the decisions that arise from the new strategy are hard and have a human cost, and for that reason, I’m sad about things like this. I can personally attest to these hard experiences. Net-net, the company is seriously betting a lot of its resources and manpower on what it calls the virtuous cycle of growth and things like 5G and they needed to make trade-offs in order to make accelerated development, and some programs had to be cancelled to free up capital. Now it’s up to Intel to execute.

More from Moor Insights and Strategy

Posted on

Highlights of the 28nm FD-SOI San Jose Presentations

Highlights of the 28nm FD-SOI San Jose Presentations
by Adele Hars on 06-05-2016 at 8:00 pm
Categories: FD-SOI, Foundries, Samsung Foundry

Samsung FDSOI productionstatus SanJose16c

Most of the presentations from the FD-SOI Symposium in San Jose last month (April 2016) are now available on the SOI Consortium website (click here to see the full list — if they’re posted, you can download them freely from there). If you don’t have time to wade through them all, here are some of the highlights. (Plus since I was there I’ll also cover some that aren’t posted.)

Since there’s so much to cover, I’ll break this into two parts. This is Part 1, focusing on presentations related to some of the products hitting the market using 28nm FD-SOI. Part 2 will focus on the presentations related to 22nm FD-SOI.

Samsung – in 28FDS mass production
Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing in his presentation “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits”. They’ve already done 12 tape-outs, and are working on 10 more now for various applications: application processor, networking, STB, game, connectivity…) and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:


Samsung’s foundry began commercial production of 28nm FD-SOI in 1Q2016.

As you see, the production PDK with the RF add-on will be available this summer. Also, check out the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, as well as Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog — get it here).


At the San Jose symposium, ST showed once again the enormous advantages FD-SOI provides in analog design.


NXP – integration, differentiation and passion
Ron Martino gave a talk full of energy and passion entitled, “Smart Technology Choices and Leadership Application Processors”.

If you read Ṙon’s terrific posts here on Semiwiki recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.

As he noted there, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s. (They’ve now posted an awesome i.MX 8 demo from FTF2016 on Twitter — see it here.)

In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:


(Courtesy: NXP and SOI Consortium)

For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER[SUP]*[/SUP]by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”

Sony – GPS (with 1/10th the power!) now sampling
You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).

In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.

Analog Bits – Lowest Power SERDES IP
SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.


With the port to 28nm FD-SOI, Analog Bits now has the industry’s lowest power SERDES.

In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”

Stanford – FD-SOI for the Fog
Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC.

Next in part 2, we’ll look at the 22nm FD-SOI presentations in San Jose.

Posted on

Facebook and Deep Reasoning with Memory

Facebook and Deep Reasoning with Memory
by Bernard Murphy on 06-05-2016 at 4:00 pm
Categories: General

Neural nets as described in many recent articles are very capable at recognizing objects and written and spoken text. But like anything we can build, or even imagine, they have limitations. One problem is that after training, the neural nets we usually encounter are essentially stateless. They can recognize static patterns but not pattern sequences and they can’t advance their learning without being retrained.

Time sequence patterns are important because that’s where semantic understanding has to start. You cannot claim a system has understanding unless it can make inferences from previously-supplied information. For example, given “Bilbo took the ring. Bilbo went back to the Shire. Bilbo left the ring there”, then answer “Where is the ring?”.

One way to address this limitation is to use recurrent neural nets (RNNs) in which perceptrons support feedback. These can make learning part of the training process, so what is memorized is embedded in the net itself, but RNNs tend to have limited and, in simpler implementations, very short-term memory. Another way is to use Memory Neural Networks (MemoryNN’s) which use associative memory in combination with a neural net. Facebook is very active in research and publications in this area (which may come as a surprise to those of you who think Facebook mostly worries about optimizing cat videos).

The MemoryNN approach at Facebook isn’t quite as simple as storing previous sentences. What is stored is a reduced vector of characteristics to enable and simplify comparisons on essential features. A lookup is then a closest match comparison on a requested feature set. FB calls these feature sets “feature vectors”. (I would imagine deciding what are the best essential features and how to grade object features on those scales then becomes a major topic its own right.)

There are several interesting challenges in modelling and matching feature vectors. One is that even with associative memories, we tend to think of exact matches per feature, but it is often more useful to also allow close matches (e.g. synonyms in text). A second interesting dimension is when in the timeline the information was stored. If, following the Lord of the Rings example above, Frodo subsequently picked up the ring, went to Mount Doom and dropped the ring there, the (current) answer to “where is the ring?” should be Mount Doom. But an answer to “Where did Bilbo leave the ring?” would still be the Shire.

A third challenge is to model unknown words, often (but not necessarily) proper names. One way Facebook deals with this is to model the context in which the word appears, determine what known words appear in that context and assume the new word is similar to those words (e.g. it is inferred to be a noun). The Facebook paper below talks about methods to address each of these needs.

MemoryNN’s are not restricted to text-based tasks. They can be useful in any objective where learning-on-the-fly can improve accuracy. For pictures, Visual Q&A (another Facebook capability; they have a demo – check it out) can answer questions about what is in a picture. You could imagine this being very useful in text/voice-based feature searches on image libraries (maybe find all pictures containing a dog). And MemoryNN’s can be particularly helpful in self-training. AlphaGo (the Google Go-player) uses MemoryNN’s to self-train on reasonable next moves from the current position in Go. Self-training is a very active area of research given the often high level of investment required in human-directed training for neural nets.

MemoryNN’s look like a major evolution in deep reasoning. Certainly Yann LeCun who runs Facebook AI Research thinks so. It’s also interesting to think about what is driving AI at Facebook and Google. They’re working on very similar areas and very similar goals – this competition should drive rapid advances in what we will be able to do. You can go through Yann’s slides on this topic and more HERE and you can read a Facebook paper on Memory Neural Networks HERE.

More articles by Bernard…

Posted on

Free Webinar: Designing Low-Power IoT Systems

Free Webinar: Designing Low-Power IoT Systems
by Daniel Nenni on 06-05-2016 at 7:00 am
Categories: Ansys, Inc., EDA, Events, IoT

As I have written before, IoT looks to be a key driver for design starts and future semiconductor revenue growth which is why we wrote “PROTOTYPICAL” and included a field guide to FPGA Prototyping. If you want to get funding for your new IoT chip project, having a working prototype is a good thing, absolutely. If you want to take a look at the latest IoT articles on SemiWiki just click “IoT” in the navigation bar above, right between ARM and Automotive.

I don’t want to scare you but for the past ten years smartphones have been driving the semiconductor industry. In fact, today semiconductor growth depends on it. Unfortunately, a recent report by IDC predicts a sharp reduction in smartphone shipments from 10%+ in 2015 to 3% in 2016. Ouch!

So let’s get some IoT designs started and the key to IoT design is of course low power, and when you mention low power design ANSYS should come to mind, which brings us to the webinar in question:

Designing Low-Power IoT Systems
The Internet of Things (IoT) is a vast network of interconnected devices that communicate with each other wirelessly or over the internet to monitor systems, transmit data and change states of devices. It is already improving our lifestyles, healthcare methods, industrial productivity, and business models. The technologies involved in the design of products and services include smart and autonomous sensor systems, cloud infrastructure, big data analytics, wireless communications and cybersecurity.

Date: June 9, 2016
Time: 11:00 AM – 12:00 PM (EDT)
REGISTER

Attend this webinar to learn how ANSYS engineering simulations can help you to meet the challenges of the IoT. Discover how to validate and even improve the power consumption, lifespan, reliability and overall integrity of this new generation of sensors. The key is maximizing the efficiency/cost ratio and optimizing the productivity of relatively simple, inexpensive systems for a very attractive market.

And the nice thing about webinars is that, even if you can’t make the programmed time, if you register in advance you will get a friendly reminder when the replay is up. And here is a special offer: If you attend this webinar I will send you a free PDF copy of “PROTOTYPICAL”. Such a deal!

The first half of “PROTOTYPICAL” is a concise history of FPGA-based prototyping. The second half of “PROTOTYPICAL” is an all-new Field Guide titled “Implementing an FPGA Prototyping Methodology” authored by the teams at S2C. It looks at when design teams need an FPGA-based prototyping solution, how to choose one, and how to be sure the platform is scalable including a look at the latest cloud-based implementations. It then dives into the methodology: setting up a prototype, partitioning, interconnect, debugging, and exercising a design. It’s a practical view of the questions teams have and the issues they run into, and how to solve them.


Posted on

My #53DAC Must See List!

My #53DAC Must See List!
by Daniel Nenni on 06-04-2016 at 7:00 am
Categories: Events

It may be hard to believe but this happens to be my thirty third Design Automation Conference. Where does the time go? Three of my kids are out of college and the last one is getting close. That is where my time has gone. The conference itself started in 1964 but my first one was in 1984 in Albuquerque, New Mexico. In fact, that was the year DAC went to the dark side and allowed sales and marketing people with booths, demos, and giveaways. The rest as they say is history, and a very colorful history indeed!

While some misinformed people say that this year there is nothing new in EDA, I seriously disagree. This year we have a disruptive technology that will change the way semiconductors are designed, absolutely!


SeaScape Platform!
This year brings big data to EDA and I say it’s about time! I sat through one of the pre-DAC briefings and it was quite exciting. All power point slides, but ANSYS assured me that they have customers that will present real usage data. You can read more about it here from Bernard Murphy and Tom Dillinger:

Rebooting EDA

“Re-Inventing” Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis

And you can speak directly to ANSYS and early customers:

To get a live update and an opportunity to question the experts on what next-generation EDA products can do for you, register for Ansys suite sessions at DAC (in-design and best practices, kicking off June 6[SUP]th[/SUP] in Austin) HERE. This will be the hottest ticket at #53DAC so reserve yours now.

Samsung Open Collaboration Theater
Samsung again has made a big investment in DAC featuring 36 different presentations for the 3 days (Mon-Wed). Details of presentations can be found at the Samsung DAC page. I gave the Samsung Theater “Best of Show” last year and I expect nothing less this year.

Samsung is also an active DAC presenter:

[LIST=1]

  • Monday 11:30am, Mentor Closed-Loop DFM Luncheon. KK Lin is presenting alongside with others
  • Tues 7:15am, SNPS breakfast event. Kelvin Low is presenting alongside with others (10nm focused)
  • Tues 1130am, SNPS Luncheon. Bonhyuck Koo (from Korea) will be presenting updates on Custom Compiler work.
  • Tues 3:30pm, ARM panel. Our packaging expert, Max Min will be on the panel
  • Tues 4pm, Mentor IoT panel. Kelvin Low will be on the panel
  • Wed 10:30am, SNPS Thought-leader sessions. Jay Um will be pesenting 28FDSOI for Automotive and IoT.
  • Wed 3:30pm, ARM panel. Kelvin Low will be on the panel on “IP re-use discussions”

    Silicon/Technology Art Show
    This is a new event at DAC and one which I think will be very entertaining. Entertaining because I am one of the judges and I’m color blind. Fortunately, my beautiful wife will be with me and she has a trained eye for colors and artsy stuff.

    The DAC Silicon/Technology Art Show will feature stunning images submitted by DAC attendees that demonstrate the beauty of everyday work in this industry. Submitted pieces will be judged in various categories and the winners for each category will be announced Wednesday, June 8 at 9:00am in Ballroom A. Awards include:

    • Best Visualization
    • Best Silicon Photo
    • Most Inspiring
    • Most Insightful
    • Most Artistic
    • Grand Prize- Best piece out of all categories

    Free “Prototypical” Book Giveaway!
    Don Dingee and I, in collaboration with S2C Inc., will be promoting our recently published book on FPGA Prototyping. This is SemiWiki’s third book in as many years and there will be more to come. Why FPGA Prototyping you ask? Simple, the semiconductor ecosystem is all about enabling design starts. As we all know it is much easier to raise money for your chip start-up if you have a working prototype and collaborating with experts will get you closer to working silicon for a minimum upfront investment.

    On Monday at 1:30pm I’ll join Don Dingee in the S2C booth #1928 for the debut of our new SemiWiki book “PROTOTYPICAL: The Emergence of FPGA-Based Prototyping for SoC Design”. We’ll be signing copies of the book (provided by S2C) and networking with attendees for a couple hours along with Mon-Ren Chene who penned the foreword.

    On Wednesday night SemiWiki will again host a book signing at the 6pm DAC reception in the Trinity Foyer. In addition to FREE food and FREE drinks, there will be FREE books (provided by S2C). The SemiWiki bloggers and my beautiful wife will be there, it would be a pleasure to meet you.

    “Mobile Unleashed” Book Giveaway!
    Solido Design Automation (booth #611) will be giving away copies of our book on the origin and evolution of ARM processors in our devices. The foreword is by Sir Robin Saxby and it currently has a 5 star rating on Amazon.com. There is a limited supply so only people who meet privately with Solido will get a signed copy. Rumor has it there will also be a copy of Mobile Unleashed in the Silvaco (booth #649) goody bag.

    Bottom line:     Hundreds of books will be given away for the greater good of the semiconductor ecosystem and we would be happy to sign them for you.

    • Posted on

    Blue Pearl adds RTL project transparency at #53DAC

    Blue Pearl adds RTL project transparency at #53DAC
    by Don Dingee on 06-03-2016 at 4:00 pm
    Categories: Blue Pearl Software, EDA, Events

    You’re an RTL pro. You know what’s inside your code, and how many bugs you’ve tracked down and exterminated along the development path, and how much work remains. So, why did the meeting notice that just popped up asking for a monthly management project review presentation ruin your day? Continue reading “Blue Pearl adds RTL project transparency at #53DAC”

    Posted on

    A Shot in the ARM for IoT

    A Shot in the ARM for IoT
    by Randy Smith on 06-03-2016 at 12:00 pm
    Categories: Arm, Events, IoT, IP

    I recently attended the IoT Developers Conference in Santa Clara, CA. There were clearly two major themes in the talks – security and low power. The volume market in IoT is in the edge node devices. These devices have two important characteristics. They acquire data which needs to be transmitted and they typically are battery-driven or even harvest their own energy. The need for security is clear if the data is sensitive (e.g., vehicle to vehicle communications, medical information, etc.) though not all applications require much security. The need for low power is also obvious for mobile or remote devices which are not plugged into a power outlet.

    A common paradigm for these edge node devices is to collect data through their sensors, store it, and then send it in packets either on demand or at some regular interval to a hub device. Of course there may also be a need for code storage, error logging, and still other storage requirements. Clearly these devices will need access to non-volatile memory. The catch is to use a memory device that also doesn’t eat up the entire power budget. Calls for such a solution, a low power non-volatile/flash memory device, have come from such industry leaders as ARM (ARM CEO Simon Segars quoted in EETimes) and Freescale (White Paper: What the Internet of Things (IoT) Needs to Become a Reality) .

    Adesto Technologies recently introduced its Ultra-Low Power Moneta™ Non-volatile Serial Memory (RM3000). This new product would seem to dramatically improve the situation for IoT system designers. The RM3000 series makes use of Adesto’s conductive bridging RAM (CBRAM) technology. They claim several advantages from using this technology amongst them, unlike flash memory there is no pre-erase requirement, it has much faster write operations (I saw a demo of this at IoT Dev Con), and it uses a much lower write voltages. Simplifying this it is faster and cheaper on the energy budget.

    This technology will start shipping as a packaged part in July 2016 in four densities – 32Kbit, 64Kbit, 128Kbit, and 256Kbit. Of course with my semiconductor IP background I had to ask if this would be coming in an IP form as well. Unfortunately, that is out on the more distant horizon. We need to keep in mind that these resistive RAMs require two extra masks which would complicate the delivery of such an IP. However, an aggressive fab might want to help accelerate the availability of this IP in its production processes. That might give significant advantage over their competition when it comes to an IoT offering.

    By now you must be wondering… how low-power is it? Really, really low. Here is what Adesto published with the new product announcement (Click on the picture below to enlarge it):

    The range of applications enabled by this technology is large but certainly would include a large range of medical devices, environment and security monitoring devices, data logging applications, and probably any device using harvested energy. In fact, I think the ultra-low power level made possible by these devices will enable applications we have not yet thought of, and that is really exciting. For emphasis, the ultra-deep power down state can go as low as 0.05 µW, with read power at 10 µW, and write power at 7.6 µW – that is quite low.

    Randy Smith is an advisor at Brown Venture Associates (BVA). Randy and BVA are experienced masters of team building. As a former EDA and semiconductor IP executive, Randy has repeatedly built winning teams. BVA has been doing the same for more than 20 years while building a proprietary recruiting methodology that is geared for the modern recruiting environment. BVA also has invested in 50+ companies with 20+ liquidity events – the teams they build, win.