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November 16, 2016June 14, 2019

Improving on EMACS for VHDL Creation

Improving on EMACS for VHDL Creation
by Bernard Murphy on 11-16-2016 at 7:00 am
Categories: EDA, Sigasi

OK – I admit I titled this piece as clickbait. There is a core of designers for whom belief in the supremacy of EMACS for RTL creation comes close to religion. Some will read only the title and jump immediately to penning searing comments questioning my intelligence, experience, parenthood and ability to tie my own shoes. Some, I hope, will read on if only to more precisely craft their rebuttal. A few may actually find some ideas of interest in this piece and especially in the links at the end.

I should admit upfront I am not an EMACS user, though I have worked with many fans. I rely instead for my information on the views of a group of folks at Sigasi who have been and remain very dedicated users but have come to realize that EMACS isn’t perfect for RTL (particularly VHDL) creation and that it is possible to conceive of better solutions without sacrificing your immortal soul. To give you a sense that these guys truly are among the EMACS faithful, one of their pieces is titled “Why Emacs VHDL mode is so Great. And Why We Want to Beat it”.

Let’s start with an obvious point. A major premise of VHDL (springing from its foundation in ADA) is to be correct by construction, as least as far as possible, so it is intended that you spend much more time getting to a compilable piece of code that you would in other more flexible languages. As getting to a successful compile gets harder, it is natural to want to simplify the task. VHDL-mode for EMACS was created over 20 years ago to address this need and has evolved into a truly great VHDL-aware editor. It provides great macros, a design hierarchy browser and a code formatter, which includes vertical alignment. And it has code fixing such as updating sensitivity lists to avoid latches. Plus, and this is important, it’s free. You don’t have to argue with your manager to have a part of the EDA budget carved out for an editor.

So why, the Sigasi folks themselves observe, would any EMACS fan in their right mind want to switch to a GUI-based editor for which they are going to have to pay? First, fans will respond that they see no value in a GUI. This part is as much religion as utility. EMACS (and Vi) has a GUI, it’s just less self-consciously “pretty” than modern GUIs. But the utility part is important – while you don’t want to pay for more pretty, you might pay for more utility. Utility of this type can become a requirement for ease of use; in the (production) software world, this battle was over a long time ago. No-one would work for a software company that offered only basic text editors for development.

That meaningful added utility is possible should not be surprising. Macro functions in any general-purpose text editor are necessarily limited to whatever can be accomplished with a shallow understanding of the text, since that is all they can build using regular expression matching. Within those limits they can still do some pretty useful things, but they can never be as capable as a special-purpose editor tuned to a deep understanding of a language, or if they try to do so, macros become unusably slow. For example, VHDL configurations can have significant impact on understanding chip hierarchy, but EMACS VHDL-mode does not look at configurations, presumably because this would be very slow.

Sigasi have summarized their view of differences particularly between EMACS capabilities and those in their Sigasi Pro editor. You’ll see that they give high marks to EMACS, but they note several significant areas where that approach falls short. These aren’t “pretty” GUI features. They are functional features that, if you like what VHDL-mode does for you, you might also reasonably want to have but you may never see in EMACS macro packages.

Finally, Sigasi acknowledge that EMACS diehards will not be won over easily. By raw metrics, EMACS will be faster, run in a smaller footprint, be user-customizable and easily run on a remote terminal. But are raw metrics the right metrics? Should you be measuring how quickly you can do an edit or how quickly you can get to a functioning simulation? And on remote operation – really? We should all know how to run remote X-terms these days. Preferences in an editor will always be somewhat religious, but it does seem that carrying those same preferences to their logical limit inevitably leads to editors like Sigasi Pro. You can learn more about Sigasi’s attempt to convert the EMACS faithful HERE.

Let the apoplectic comments begin…

5 of the Top 20 Semiconductor Suppliers to Show Double-Digit Gains in 2016!

5 of the Top 20 Semiconductor Suppliers to Show Double-Digit Gains in 2016!
by Daniel Nenni on 11-15-2016 at 4:00 pm
Categories: FinFET, Foundries, TSMC

Semiconductor Market Researcher IC Insights released an update to the 2016 semiconductor sales forecast which is interesting on many different levels. It really has been an exciting year for the semiconductor industry, absolutely. Two of the stars of this year’s report happen to be two of my favorite fabless companies, Nvidia and MediaTek, who will post record gains of 35% and 29% respectively.

The fastest growing top-20 company this year is forecast to be U.S.-based Nvidia, which is expected to post a huge 35% year-over-year increase in sales. The company is riding a surge of demand for its graphics processor devices (GPUs) and Tegra processors with its year-over-year sales in its latest quarter (ended October 30, 2016) up 63% for gaming, 193% for data center, and 61% for automotive applications.

The second-fastest growing top-20 company in 2016 is expected to be Taiwan-based MediaTek, which is forecast to post a strong 29% increase in sales this year. Although worldwide smartphone unit volume sales are expected to increase by only 4% this year, MediaTek’s application processor shipments to the fast-growing China-based smartphone suppliers (e.g., Oppo and Vivo), are forecast to help drive its stellar 2016 increase.

Nvidia and MediaTek serve different markets but they have two important things in common: VERY strong leadership and a VERY strong foundry partnership with TSMC.

Nvidia CEO Jen-Hsun Huang and MediaTek CEO Tsai Ming-Kai could not be two more different CEOs. Jen-Hsun is loud and arrogant while Tsai is quiet and humble. The traits they do share are vision and a laser like focus on market opportunity. They both also have Dr. Morris Chang Exemplary Leadership Awards from the Global Semiconductor Association in recognition of “exceptional contributions to driving the development, innovation, growth and long-term opportunities of the fabless semiconductor industry”.

On the foundry side, Nvidia and TSMC are collaborating on a cost effective HPC specific 7nm process to be introduced in Q4 2017. MediaTek is also collaborating with TSMC on an SoC version of 7nm but more importantly will be TSMC’s top customer for the 16FFC fab in China due to go online in 2018. Right now the China SoC market is 28nm centric but that will change in 2018. Mediatek will also use TSMC InFO technology for added cost reduction and performance improvement distancing themselves from the other 14nm SoC offerings for China and other emerging SoC markets (India).

The interesting thing to note about Nvidia’s Q3 2016 results is the surge in data center and automotive business (which is what I mean by vision and market opportunity focus). Given their success in two of the hottest semiconductor market segments, one might predict that Nvidia is a prime acquisition target. In fact, I had wrongly predicted that QCOM would buy Nvidia instead of NXP and I still think they should have but I digress…

My feeling today is that Nvidia should be the one doing the acquiring so I’m working on a shopping list for Jen-Hsun. Please post your suggestions in the comment section and I will make sure he gets them.

You can get a PDF version of the IC Insights research bulletin HERE.

November 15, 2016

IoT Standardization and Implementation Challenges

IoT Standardization and Implementation Challenges
by Ahmed Banafa on 11-15-2016 at 12:00 pm
Categories: IoT

The rapid evolution of the #IoT market has caused an explosion in the number and variety of IoT solutions. Additionally, large amounts of funding are being deployed at IoT startups. Consequently, the focus of the industry has been on manufacturing and producing the right types of hardware to enable those solutions. In current model, most IoT solution providers have been building all components of the stack, from the hardware devices to the relevant cloud services or as they would like to name it as “IoT solutions”, as a result, there is a lack of consistency and standards across the cloud services used by the different IoT solutions.

As the industry evolves, the need for a standard model to perform common IoT backend tasks, such as processing, storage, and firmware updates, is becoming more relevant. In that new model, we are likely to see different IoT solutions work with common backend services, which will guarantee levels of interoperability, portability and manageability that are almost impossible to achieve with the current generation of IoT solutions.

Creating that model will never be an easy task by any level of imagination, there are hurdles and challenges facing the standardization and implementation of IoT solutions and that model needs to overcome all of them.
IoT standardization
The hurdles facing IoT standardization can be divided into 4 categories; Platform, Connectivity, Business Model and Killer Applications:

Platform:This part includes the form and design of the products (UI/UX), analytics tools used to deal with the massive data streaming from all products in a secure way, and scalability which means wide adoption of protocols like IPv6 in all vertical and horizontal markets is needed.
Connectivity:This phase includes all parts of the consumer’s day and night routine, from using wearables, smart cars, smart homes, and in the big scheme, smart cities. From the business prospective we have connectivity using IIoT (Industrial Internet of Things) where M2M communications dominating the field.
Business Model:The bottom line is a big motivation for starting, investing in, and operating any business, without a sound and solid business models for IoT we will have another bubble , this model must satisfied all the requirements for all kinds of e-commerce; vertical markets, horizontal markets and consumer markets. But this category is always a victim of regulatory and legal scrutiny.
Killer Applications: In this category there are three functions needed to have killer applications: control “things”, collect “data”, and analyze “data”. IoT needs killer applications to drive the business model using a unified platform.

All four categories are inter-related, you need all them to make all them work. Missing one will break that model and stall the standardization process. A lot of work needed in this process, and many companies are involved in each of one of the categories, bringing them to the table to agree on a unifying model will be daunting task.

IoT implementation
The second part of the model is IoT implementations; implementing IoT is not an easy process by any measure for many reasons including the complex nature of the different components of the ecosystem of IoT. To understand the gravity of this process, we will explore all the five components of IoT Implementation: Sensors, Networks, Standards, Intelligent Analysis, and Intelligent Actions.

Sensors
There two types of sensors: active sensors & passive sensors. The driving forces for using sensors in IoT today are new trends in technology that made sensors cheaper,smarter and smaller. But the challenges facing IoT sensors are:power consumption, security, and interoperability.

Networks
The second component of IoT implantation is to transmit the signals collected by sensors over networks with all the different components of a typical network including routers, bridges in different topologies. Connecting the different parts of networks to the sensors can be done by different technologies including Wi-Fi, Bluetooth, Low Power Wi-Fi , Wi-Max, regular Ethernet , Long Term Evolution (LTE) and the recent promising technology of Li-Fi (using light as a medium of communication between the different parts of a typical network including sensors).

The driving forces for wide spread network adoption in IoT are high data rate, low prices of data usage, virtualization (X – Defined Network trends), XaaS concept (SaaS, PaaS, and IaaS), and IPv6 deployment. But the challenges facing network implementation in IoT are the enormous growth in number of connected devices, availability of networks coverage, security, and power consumption.

Standards
The third stage in the implementation process includes the sum of all activities of handling, processing and storing the data collected from the sensors. This aggregation increases the value of data by increasing, the scale, scope, and frequency of data available for analysis but aggregation only achieved through the use of various standards depending on the IoT application in used.

There are two types of standards relevant for the aggregation process; technology standards (including network protocols, communication protocols, and data-aggregation standards) and regulatory standards (related to security and privacy of data, among other issues). Challenges facing the adoptions of standards within IoT are:standard for handling unstructured data, security and privacy issuesin addition to regulatory standards for data markets.

Intelligent Analysis
The fourth stage in IoT implementation is extracting insight from data for analysis. IoT analysis is driven by cognitive technologies and the accompanying models that facilitate the use of cognitive technologies. With advances in cognitive technologies’ the ability to process varied forms of information, vision and voice have also become usable, and open the doors for in-depth understanding of the none-stop streams of real-time data. Factors driving adoption intelligent analytics within the IoT; artificial intelligence models, growth in crowdsourcing and open- source analytics software, real-time data processing and analysis. Challenges facing the adoption of analytics within IoT; Inaccurate analysis due to flaws in the data and/or model, legacy systems’ ability to analyzeunstructured data, and legacy systems’ ability to manage real- time data

Intelligent Actions
Intelligent actions can be expressed as #M2M (Machine to Machine) and M2H (Machine to Human) interfaces for example with all the advancement in UI and UX technologies. Factors driving adoption of intelligent actions within the IoT;lower machine prices, improved machine functionality, machines “influencing” human actions through behavioral-science rationale, and deep Learning tools. Challenges facing the adoption of intelligent actions within IoT : machines’ actions in unpredictable situations, information security and privacy, machine interoperability, mean-reverting human behaviors, and slow adoption of new technologies

The Road Ahead
The Internet of Things (IoT) is an ecosystem of ever-increasing complexity; it’s the next weave of innovation that will humanize every object in our life, it is the next level to automating every object in our life and convergence of technologies will make IoT implementation much easier and faster, which in turn will improve many aspects of our life at home and at work and in between. From refrigerators to parking spaces to houses, IoT is bringing more and more things into the digital fold every day, which will likely make IoT a multi-trillion dollar industry in the near future. One possible outcome of successful standardization of IoT is the implementation of “IoT as a Service” technology , if that service offered and used the same way we use other flavors of “as a service” technologies today the possibilities of applications in real life will be unlimited. But we have a long way to achieve that dream; we need to overcome many obstacles and barriers at two fronts, consumers and businesses before we can harvest the fruits of such technology.

Article published on #IEEE-IoT : http://iot.ieee.org/newsletter/july-2016/iot-standardization-and-implementation-challenges

References:
http://www.dbta.com/BigDataQuarterly/Articles/10-Predictions-for-the-Future-of-IoT-109996.aspx
https://campustechnology.com/articles/2016/02/25/security-tops-list-of-trends-that-will-impact-the-internet-of-things.aspx
http://dupress.com/
https://www.linkedin.com/pulse/iot-implementation-challenges-ahmed-banafa?trk=mp-author-card
https://www.linkedin.com/pulse/what-next-iot-ahmed-banafa?trk=mp-author-card
Figures Credit: https://pixabay.com/en/binary-code-man-face-board-trace-1327503/ and Ahmed Banafa

Ahmed Banafa Named No. 1 Top VoiceTo Follow in Tech by LinkedIn in 2016

November 15, 2016June 14, 2019

Quality in Hard IP

Quality in Hard IP
by Bernard Murphy on 11-15-2016 at 7:00 am
Categories: EDA, Fractal Technologies

I was CTO at Atrenta, home of SpyGlass, for many years before the company was acquired by Synopsys, so I know a thing or two about IP quality, to paraphrase a popular commercial. The problem is that even in the best-run IP shops, errors happen. Sometimes they happen on simple changes, especially when you think “This IP has been very carefully checked and the change I just made is so small it won’t affect anything”. They also happen in configurable IP, especially near architecture transitions where not all possible configurations have been comprehensively validated.

At Atrenta we worried about soft IP and were sometimes told “We have it covered internally and we’ll catch any escapes in simulation”. Then we’d wait (with confidence) for a call-back after a quality problem made it to silicon. But the “we’ve got it covered” argument is even more difficult to defend with hard IP. Simulation isn’t going to tell you that you have a mismatch between your GDSII and LEF models or an un-routable pin or many other potential problems in the long list of files now needed to describe a hard IP. Sure you’ll catch some of these in layout, but that’s way too late to be finding basic problems that could trigger major rework. And some will still escape to silicon.

Where can errors happen? Perhaps in foundation (cell) libraries. These get pretty well shaken out unless you’re an early user but some cells at some corners could remain untouched until you stumble across a problem. Memory compilers are a more likely source for an undiscovered problem because they are configurable. Then there are internally sourced hard macros – PLLs, PHYs, ADCs and DACs, voltage references, special I/Os. And there are hardened digital IPs – ARM cores, GPUs and accelerators – optimized by an internal team for performance, for whatever power profile you need for this design and for layout footprint. In all of these cases it’s much more likely you will be the first user on any given incarnation of a block and that you may see multiple releases of a block before tapeout.

What are typical errors? A small subset of examples, encountered on production designs, include:

Pin direction mismatch between views, pins in the wrong layer
Missing labels, or label spelling errors or labels in wrong layer
Abutment errors (layers do not touch outline)
Pins not on grid
Delay decreases with increasing output load, non-paired setup and hold times in Liberty file
CCS curves have more than one peak or a correction current in the tail
ECSM curves have large deviations between ECSM and NLDM values
Transistor bulk terminal connections in Spice incorrect

Checking for these kinds of problem obviously can’t be left to visual inspection, across potentially terabytes of data, much less at each point in the design evolution where errors may have crept in. You could build tool-based scripts to check for some problems, but that gets messy when you want to check correspondence between a Verilog view, a layout view and a Spice view. And you have to worry about the correctness and currency of over 30 parsers. If you feel that building and maintaining that kind of infrastructure is a good use of your company’s time, go for it. Or you could take a look at Crossfire from Fractal Technologies.

I first became aware of Fractal several years ago. I felt that Crossfire would be a really good fit with SpyGlass – SpyGlass for soft IP quality and Crossfire for hard IP. For various reasons we didn’t pursue that further, but not because I was unimpressed with the product or the company. I still feel Crossfire would be a great complement to SpyGlass. I also happen to know that, without naming names, some of the most significant design teams in the world use Crossfire. These teams are staffed by the best of the best. When they believe it is important to perform these checks, it’s worth taking note.

You can learn more about Fractal and Crossfire HERE.

Tech Industry Analyst Notes On Apple Event

Tech Industry Analyst Notes On Apple Event
by Patrick Moorhead on 11-14-2016 at 4:00 pm
Categories: Mobile

I attended Apple’s special event at the Bill Graham Civic Center in San Francisco and wanted to share with you some of my thoughts and highlights that came out of the event:
Continue reading “Tech Industry Analyst Notes On Apple Event”

November 14, 2016April 9, 2020

3 in 1 Hardware Verification

3 in 1 Hardware Verification
by Bernard Murphy on 11-14-2016 at 12:00 pm
Categories: Aldec, EDA, FPGA, Prototyping, Xilinx

Aldec has offered front-end EDA tools for over 30 years but may not be a familiar name to mainstream IC design engineers. That’s probably because for most that period they haven’t really targeted IC design. They have been much more focused on PC-based design for FPGAs particularly where requirements traceability has been important, for example in avionics design, where DO-254 compliance is mandatory.

But there have been important shifts in interesting markets over the past few years which move closer to Aldec’s center of gravity. Fragmenting market needs demand device volumes that are not cost-effective in custom IC implementations, a problem further compounded by rapidly evolving standards, such as communications protocols. This drives a trend to FPGAs at higher unit costs but much lower total cost. Additionally, standards which are either regulatory or de-facto regulatory have become more important in rapidly-growing markets like automotive (ISO 26262), industrial (IEC-61508) and medical (IEC-60601).

You may be even more surprised to hear that Aldec has a prototyping/emulation product. Why would their customers need such a thing? Because FPGA/multi-FPGA designs are getting to be too big and too software-driven for burn-and-churn debug to be practical. Just as FPGA designers are turning to UVM and formal proving, they’re also turning to hardware help in verification. That’s where the latest HES release, based on Xilinx UltraScale devices, becomes interesting.

One HES7XUS1320BPX board (pictured at the beginning of this piece) containing three XCVU440 devices on a single PCB has an estimated capacity of 79 Million ASIC gates. For larger designs the system can be scaled up with a standards-based backplane that can interconnect up to four boards to provide capacity of 316 Million ASIC gates. What’s more it can be used as an emulator or an emulation slave to a master simulation.

Of course hardware alone doesn’t make an emulator. Part of what you need is reasonable setup times. Judging by comments on earlier generations it seems this is why Aldec went with the biggest Xilinx devices – to reduce the need for partitioning for many of the designs they target. But to echo a comment in a reference below, it is less obvious how well this scales if you need to go to 2 or more boards.

The other thing you need is fine-grained debug support. HES offers up to 16 groups of 16kbits of “static probes”, spread across all FPGAs in the system. These seem to be effectively instrumented into a multi-chip logic analyzer. They also offer something called dynamic probes which you can select during runtime, allowing for debug access anywhere, though at slower speeds with Xilinx readback. You also get a backdoor interface for read and write of memory.

Aldec also provides support for using emulation mode in ICE (in-circuit emulation) modeling, with support for speed bridges, as a simulation accelerator, for co-emulation with virtual models and for software debug. Apparently a pretty comprehensive solution though to dig deeper you’ll need to talk to your local distributor.

One last thing. It’s always tricky to get information on pricing but I did find this reference which suggests that in 2012, HES-7 was under $20k for a single board solution. That is a very different price range from mainstream emulation and prototyping solutions. I can’t answer to how HES could address your needs, but pricing alone should pique your interest. You can read more about the latest Aldec HES capabilities HERE. There’s also a somewhat more detailed report on HES HERE.

CEO Interview: Chouki Aktouf of Defacto Technologies

CEO Interview: Chouki Aktouf of Defacto Technologies
by Daniel Nenni on 11-14-2016 at 7:00 am
Categories: CEO Interviews, Defacto Technologies, EDA

As a 30+ year semiconductor veteran I can tell you with 100% certainty that start-ups are the lifeblood of EDA. The mantra is “Innovate or Die!” and that is exactly what Defacto is doing. After more than 10 years of innovating in Design for Test at RTL, Defacto is now offering a complete EDA solution based on generic EDA tools to cover advanced Design Restructuring, Design Verification, Low Power Design, IP Integration, and RTL Signoff.

The development of Defacto’s technology began at the National Polytechnic Institute of Grenoble (INPG-France) in 1997, under the leadership of Chouki Aktouf, PhD. More than 18 man-years of work were invested in Defacto’s unique DFT technology. Dr. Aktouf and his team did the early market assessment and established proof of concept by working with a large European semiconductor manufacturer to validate the benefits of the company’s technology.

In 2003, Dr. Aktouf, Michel Oger, Philippe Duchene, and James Girand founded Defacto and the company raised Series A to D from two major investors in France, Innovacom and CIC-CM.

What does Defacto do?
Defacto provides RTL design solutions which help users to build a unified design flow where different standards like RTL for design description, UPF for power intent, SDC for timing constraints, LEF/DEF for physical design information, are considered jointly

What are the challenges facing EDA companies today?
Main challenges are three fold, first, different mergers between major semiconductor companies.

Second challenges are the new opportunities around design solutions especially for killing apps like for automotive, IOT (Internet of Things) and the ability to provide compelling solutions.

Last but not least are the emerging FPGA based solutions for complex designs, where EDA offers are still very limited compared to ASICs.

But why partitioning at RTL?
Partitioning and re-architecturing complex SoCs during or after logic synthesis is just unrealistic, knowing the complexity of the today chips with the related runtime and performance in general. So partitioning at RTL means analyzing different configurations, different scenarios, given several criteria: power, DFT, reliability, timing, physical information, etc. It’s just the way to go.

You spoke about unified flow what are the benefits to have this kind of platform?With the Defacto-based unified flow, RTL designers for example not expert in low power designs or timing will be able to automatically update the related databases UPF or SDC respectively when RTL change. Imagine an RTL designer who is able in minutes to (1) change complex RTL, (2) then update automatically UPF and SDC files and release all changes. This has a great benefit compared to traditional ways of updating manually UPF and SDC databases and different interactions between several teams to get a consistent RTL+UPF+SDC database.

What’s new this year?
Several breakthrough technologies are announced this year. First is around the unified flow as mentioned earlier. We are ready to demonstrate the related value to major semiconductor companies. Also this November at ITC (International Test Conference) in Fort Worth Texas, we will be demonstrating for the first time, a platform which will help exploring at RTL complex DFT architectures to help DFT engineers and DFT architects to decide about how much DFT logic is needed at different levels. The ultimate goal is to fit into an area overhead+test time budget given test coverage criteria. A typical DFT architecture includes test compression, memory BIST, etc.

How will chip companies benefit from Defacto STAR design solution?
Defacto tools are Tcl based and easily customizable to help and interoperate with existing DFT flows. Defacto doesn’t compete with existing DFT offers. Defacto augment existing DFT flows.

What are your major challenges?Is to demonstrate the benefits of this RTL DFT solution on complex chips on real projects, maybe the most important challenge is to convince users to start as early as possible to explore complex RTL design configurations. In other words, changing mindset is one of the challenges we face daily!

Which markets do you feel offer the most and best opportunities for STAR over the next few years and why? Is there a killer app somewhere in these markets?
Several, especially emerging markets. For example, the automotive market is now highly demanding of reliable, secure and testable chips: a higher test coverage where chips are tested when applications are running. This mean DFT requirements are higher. It is one of the reasons why to start building and configuring DFT architectures as soon as possible.

Also Read:

Executive Interview: Vic Kulkarni of ANSYS

CEO Interview: Taher Madraswala of Open-Silicon

CEO Interview: Simon Butler of Methodics

November 13, 2016

Hotz Tech Crunched

Hotz Tech Crunched
by Roger C. Lanctot on 11-13-2016 at 4:00 pm
Categories: Automotive

George Hotz, founder of Comma.ai told the world at TechCrunch that he was going to ship a $999 aftermarket autopilot system – the Comma One. The smartphone-sized device was designed to replace the rearview mirror enabling an automated driving experience in appropriately equipped cars – initially certain Acura and Honda models.

Last week the U.S. National Highway Traffic Safety Administration sent Hotz a letter seeking answers to questions regarding the functionality of his device. They also noted that a failure to respond to their outreach would lead to $21,000/day fines.

The agency, a division of the U.S. Department of Transportation, made clear that since the installation of the Comma.ai device required disabling and removal of existing safety technology in the car it violated various aspects of the Safety Act. Hotz quickly folded his tent indicating that he had no interest in tangling with lawyers and regulators. He also took issue with the NHTSA for what he perceived as a one dimensional communication that allowed no room for a conversation or negotiation regarding an actual market introduction of his device.

In his TechCrunch presentation Hotz more or less anticipated the demise of his efforts even as he was bragging about his achievement of actually delivering a product. He touted “shipability” as the key differentiator between Comma.ai and all other innovators in the space.

He took particular aim at Cruise Automation, long ago acquired by General Motors for a rumored $1B, describing the company as a “sellout.” He further ascribed mafia-like characteristics to Mobileye’s domination of the self-driving market.

In fact, he emphasized the value and power of his independence and his ability to control his own destiny since he had access to raw data that he was free to analyze and aggregate as he saw fit without any pre-processing or filtering. We can expect to hear more about this independent approach in the future, but for now Hotz has been sidelined.

NHTSA’s arrival on the aftermarket self-driving car scene raises questions about the ability of innovators like Hotz to bring their systems to market or at least test their ideas in real-world circumstances. Hotz claimed at TechCrunch to have more than 730 beta users in the field.

There are at least five other companies working in the aftermarket space including Pilot Automotive, Pearl Auto, Perrone Robotics, TorcRobotics and Paravan Industry. Presumably these companies have a path to testing and product development that will not run afoul of NHTSA.

Having pulled the plug on one player, though, it is possible that NHTSA may become more assertive. Kicking Hotz to the curb (or throwing him under the self-driving bus?) is like swatting a fly for NHTSA. Given the fact that Tesla Motors’ automated driving system offers a value proposition comparable to Comma One should we expect to see NHTSA exerting veto power over future enhanced cruise control or other safety systems from car companies?

It will be a shame if NHTSA’s entry into the automated driving conversation actually slows or delays development of this technology. The emergence of Cruise and Comma.ai and others reflects the reality that the tools for creating built-in and aftermarket self-driving systems are proliferating bringing with them a corresponding reduction in cost.

NHTSA will soon have its hands full. The best outcome will be for NHTSA to find a way to constructively engage with these innovators and developers rather than simply waiting on the sidelines with their finger on the termination trigger. Lives are truly at stake. With highway fatalities on the rise in the U.S. and around the world it seems clear that we need to advance this technology as rapidly as possible. Perhaps Hotz is just an overheated outlier. Let’s hope that is the case.

November 13, 2016

DDoS Attack: A Wake-Up Call for IoT

DDoS Attack: A Wake-Up Call for IoT
by Ahmed Banafa on 11-13-2016 at 12:00 pm
Categories: IoT, Security

Welcome to the world of Internet of Things wherein a glut of devices are connected to the internet which emanates massive amounts of data. Analysis and use of this data will have real positive impact on our lives. But we have many hoops to jump before we can claim that crown starting with a huge number of devices lacking unified platform with serious issues of security standards threatening the very progress of #IoT.
Continue reading “DDoS Attack: A Wake-Up Call for IoT”

November 13, 2016

The Ramifications of Not Accepting Industry 4.0

The Ramifications of Not Accepting Industry 4.0
by Bill McCabe on 11-13-2016 at 7:00 am
Categories: IoT

In the last couple of years, Industry 4.0 has significantly affected manufacturing on a global scale. With a heavy focus on the Internet of Things, the use of smart machines and other devices has become a critical part of Industry 4.0. With new networks of intelligence on the horizon, there is no doubt that Industry 4.0 will continue to spread and prove to be a critical part of manufacturing.

While the benefits are explored time and time again, some may wonder what would happen if they don’t embrace this advanced technology. Early on, the biggest nuisance would be higher costs. Older machinery will continue to age and will eventually need to be replaced. Those who have embraced Industry 4.0 will find that their marginal costs decrease while production flows smoothly and effortlessly. This allows a higher output and fewer issues along the way.

There is also a greater risk of running out of product when you need it the most. Human error can make estimating the amount of raw product you need for a week difficult. When you utilize Industry 4.0 technology, you can keep track of everything in real time. Based on the speed of machines, and the amount of raw materials you have in stock, the system can analyze and predict what the output will continue to be, and how long until you run out of essential items. Since the system can be set up to handle the reordering process when it is low, and ensure you never run out of product. So those who don’t embrace it will not benefit from this.

Those who do not embrace it will find that they are unable to remain competitive in the changing market. With the technology, there is less waste of raw materials, better supply chains, and lower operating costs due to improved efficiency. Even product output levels increase, so those who accept and utilize Industry 4.0 are poised to succeed. Those who do not, will find themselves operating too slow and at too high a cost to obtain the highest number of customers possible. After all, buyer expectations are changing in today’s world and it is critical that you keep up with it.

When a problem occurs during the production process, there is also the ability to note any machinery issues that take place. If something breaks down, or if there is a misfire that could damage product, the system can stop at once. It will then alert maintenance of any concerns that exist so you are down for shorter periods of time, and you don’t face any surprises along the way.

As you can see, it is incredibly important to embrace Industry 4.0. Take the time to explore how you can best utilize it within your own company and avoid many of the unpleasant surprises that can take place if you push off the conversion process to “save money”.

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