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Calibre Vision AI at #62DAC

Calibre Vision AI at #62DAC
by Daniel Payne on 07-29-2025 at 10:00 am
Categories: EDA, Siemens EDA

calibre vision ai min

Calibre is a well-known EDA tool from Siemens that is used for physical verification, but I didn’t really know how AI technology was being used, so I attended a Tuesday session at #62DAC to get up to speed. Priyank Jain, Calibre Product Management presented slides and finished up with a Q&A session.

In the semiconductor world we’ve seen a hardware-centric viewpoint starting with PCs in the 80s and 90s, where software ran on general-purpose hardware. Today, it’s more of a software-defined world, where the software architecture drives the hardware implementation.

The vision with Calibre is to shift-left and reduce Turn Around Time (TAT), accomplished by running the tools earlier in the design and implementation flows and using AI techniques. A huge challenge of trying to run full-chip integration earlier is that it produces billions of DRC errors, making the tool load slowly, increases debug time, all with little collaboration between engineering team members on what to fix first.

This challenge led to a new product called Calibre Vision AI, which enables full-chip analysis earlier in the implementation process by adding intelligent debug and user collaboration. With this new tool, engineers can quickly make sense of a DRC run that has billions of errors, as the AI feature clusters similar errors together making it easier to identify systematic issues such as block overlap, bad via, fill overlap and more, and let’s you  prioritize which errors should be fixed first.

Calibre Vision AI has a modern, multi-threaded foundation for fast operation. A GUI with dynamic panels for quick debug, and navigation features to pinpoint the source of errors.

The GUI helps visualize a heat map, showing the density of DRC errors. AI is used to cluster similar errors, and the AI works across all IC layout technologies with no model training required for tool users. Common failure causes are easily identified so that you will be more productive in fixing DRC errors. As an engineer uses the tool they can use dynamic bookmarks on the layout to capture, assign work and write notes for other team members to collaborate on the fixes.

It’s recommended that you run the Calibre RVE tool at the block level and for tapeouts, and run Calibre Vision AI for chip-level analysis at early stages, as the two tools complement each other. Using Calibre Vision AI for full-chip analysis accelerates full-chip debug through the high capacity and multi-threaded technology. Heat maps of errors show the entire die, so that you can pinpoint areas of highest interest. Results are visualized instantly, even when its millions of errors. One comparison showed that for 790 million DRC errors a traditional ASCII flow would load in 15 minutes, while a Vision AI flow using OASIS loaded in just 45 seconds.

Early users of Vision AI reported that it was faster to identify systematic issues and that DRC debug iterations were cut in half. For example, one run had 600M errors from 3,400 checks, then that was reduced to just 381 signal groups or clusters.

Siemens has many EDA tools using AI techniques.

There are three places where AI is used in Calibre Vision AI:

  • Chatbot – EDA knowledge using prompts
  • Reasoning – Data analysis and summarization
  • Tool Operations – Performing complex tool functions from prompts

Summary

DRC analysis and debug work can now reduce tasks that required hours into just minutes by using AI-based clusters. Teams doing physical design can collaborate and communicate more efficiently by using bookmarks, block debug and attaching reports.

Q&A

Q: Is there any plan to Auto-fix DRC errors?

AI quickly groups similar DRC violations for easier root-cause analysis, but we still need a human in the loop to fix the violations.

Q:  Can I create new Signals?

A: Vision AI comes with a set of Signals out of the box, and I can also create their custom signals by my own checks (i.e. M1 checks first).

Q: What’s the difference between RVE classifier and AI?

A: AI takes and elevates the classifier by 100X, analyzing the results, locations, proximity, root causes, cluster by groups. RVE is good for fewer errors, but AI works on billions of errors and earlier in the process.

Q: Can you aggregate AI across multiple designs, trends, library cells in common, broad trends?

A: It’s under development, stay tuned for a future release.

Q: Are signal groups an AI classification?

A: We use unsupervised learning to create the groups by location, proximity.

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Musk’s new job as Samsung Fab Manager – Can he disrupt chip making? Intel outside

Musk’s new job as Samsung Fab Manager – Can he disrupt chip making? Intel outside
by Robert Maire on 07-29-2025 at 6:00 am
Categories: Automotive, Foundries, Samsung Foundry, Semiconductor Advisors, Semiconductor Services
14 Comments

Elon Musk Samsung Tesla

– Musk chip lifeline to Samsung comes with interesting strings attached
– Musk chose Samsung over Intel-What does that say about Intel?
– Musk will hold sway over Samsung much as Apple/NVDA over TSMC
– Will Musk do a “DOGE” on chip tool makers? How much influence?

Tesla/Samsung $16.5B deal has many, many ramifications to rile chips

Samsung has been flailing for quite some time in the foundry business. TSMC is running away with the foundry industry leaving both Samsung and Intel far behind eating dust. Samsung just got a huge lifeline in the form of an endorsement from none other than Elon himself.

The Talyor Texas fab which had been on hold due to a lack of customers now has a customer big enough to fill the whole fab and then some. It puts the fab back on track overnight and puts Samsung back in the foundry business.

We are 100% certain that Musk got a super sweetheart deal that exacted a few pounds of flesh from Samsung which was backed up against a wall.

Certainly a way better deal than he could have gotten from TSMC which is up to its eyeballs in demand especially from the likes of Apple and Nvidia.

This also clearly puts Samsung in the middle of the AI business in a way they never could have by themselves.

“Intel Outside” – What does Musk’s choice say about Intel?

We are sure that Intel would have given away the farm to get this deal from Musk. It would have been the deal they needed to justify 14A and beyond. It would have been the deal of the century to rescue Intel……but it wasn’t……

The real question is why not Intel? Did they not offer Musk enough? I doubt it. Maybe there is not enough faith in Intel’s ability to execute. Maybe concern about viability.

Maybe Musk just wanted to thumb his nose at the US chip company (Intel) and the current Trump administration trying to come up with a post CHIPS Act strategy that works.

Maybe Musk just like the short commute to the Taylor fab in Texas….

Maybe its all of the above……

But what it clearly is, is very bad for Intel to be the last person standing at the chip industry dance without a partner…..

Musk’s new role: “Samsung Fab Manager”

A few Musk words that should strike fear into every semiconductor equipment maker;

“Samsung agreed to allow Tesla to assist in maximizing manufacturing efficiency. This is a critical point, as I will walk the line personally to accelerate the pace of progress. And the fab is conveniently located not far from my house”

Read that line again; ….. “I will walk the line (fab production line) personally to accelerate the pace of progress”

Imagine seeing Musk in a bunny suit inside the fab talking to tool operators…..It just blows my mind….and the fact that Samsung agreed to this shows just how desperate they are.

Is Musk going to personally negotiate with tools makers about the price/performance of their tools? Don’t be surprised as he has very clearly completely disrupted other industries. He is certainly smart enough and rich enough to turn the chip industry on its head….

  • Electrify autos
  • Reusable spaceships
  • Global high speed internet
  • Tunnels
  • Robots
  • AI
  • Drive Ins
  • Flamethrowers
  • DOGE
  • A third political Party
  • The semiconductor industry is a piece of cake
Tesla over other auto makers and other AI suppliers

Tesla now has guaranteed bleeding edge , us sourced, tariff resistant, chip capacity for its cars versus GM stuck with ancient, outdated, Global Foundries and foreign unreliable, tariffed, fabs……

Tesla/Musk now can get critical AI chip capacity for its robots, cars etc; and not be beholden to Nvidia/TSMC

Quite a stroke of genius……

The stocks

Obviously a big positive for both Samsung and Tesla.

Obviously a negative for Intel and TSMC

A negative for GM, Ford, BMW, Mercedes, Toyota etc; left in the analog dust….

Gotta love Texas……

Positive for chip tool makers in that Samsung’s Texas fab is back on but negative given the potential involvement of Musk in running the fab and impacting decisions.

Positive for all those former DOGE Musk minions (including “Big Balls”) will now have jobs “accelerating the pace of progress” in Samsung’s Taylor fab.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
Also Read:

Elon Musk Given CHIPS Act & AI Oversight – Mulls Relocation of Taiwanese Fabs

CHIPS Act dies because employees are fired – NIST CHIPS people are probationary

Trump whacking CHIPS Act? When you hold the checkbook, you make up the new rules

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Enabling the Ecosystem for True Heterogeneous 3D IC Designs

Enabling the Ecosystem for True Heterogeneous 3D IC Designs
by Kalar Rajendiran on 07-28-2025 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Siemens EDA

The Shift to System Technology Co Optimization

The demand for higher performance, greater configurability, and more cost-effective solutions is pushing the industry toward heterogeneous integration and 3D integrated circuits (3D ICs). These solutions are no longer reserved for niche applications—they are rapidly becoming essential to mainstream semiconductor design. However, their success hinges on the development of a robust ecosystem that brings together chiplet developers, foundries, OSATs, substrate suppliers, EDA vendors, and test providers. This ecosystem must support standardized workflows, interoperable tools, and reusable components to ensure seamless design, integration, and manufacturing across the entire 3D IC value chain.

Siemens EDA is leading this shift by enabling such an ecosystem through structured workflows, collaborative standards, interoperable tools and a new class of design enablement kits.

The Shift to System Technology Co-Optimization

To meet modern design requirements, the industry is embracing a system-level methodology known as System Technology Co-Optimization (STCO). Rather than designing a single monolithic SoC, STCO breaks down functionality into modular chiplets, each optimized for specific tasks and potentially manufactured using different process nodes or by different vendors. These chiplets are then integrated into a unified 3D IC package. This approach offers several advantages. Designers can achieve higher performance by using specialized chiplets for different functions, improve yields by isolating defects to individual modules, and reduce costs by combining mature and leading-edge technologies in a single package.

However, these benefits come with significant challenges. Coordinating the design, integration, and testing of multiple chiplets within a complex 3D package requires new tools, workflows, and standards that go beyond traditional IC design.

Enabling Design with 3D IC Design Kits

Recognizing the above-mentioned challenges, Siemens EDA has introduced a comprehensive framework of 3D IC Design Kits (3DKs) to support every phase of the design process. These kits were developed in collaboration with the Chiplet Design Exchange (CDX), a working group within the Open Compute Project that includes EDA vendors, foundries, OSATs, and system designers.

The first of these kits, the Chiplet Design Kit (CDK), provides standardized models for defining the electrical and physical characteristics of a chiplet. Built on the JEDEC JEP30 part model and enhanced with the CDXML schema, CDKs make chiplet attributes machine-readable and easily integrable into design workflows. The Package Assembly Design Kit (ADK) defines the mechanical and electrical rules for assembling chiplets, interposers, and substrates into a complete 3D stack. This includes specifications for spacing, pitch, and orientation, and may soon incorporate IEEE’s 3Dblox standard for describing 3D structures.

The Material Design Kit (MDK) addresses a previously unmet need: standardizing the material properties of components for use in thermal, stress, and electrical analyses. Instead of relying on manually input data from vendors, MDKs make this information readily available in formats that can be directly imported into EDA and MCAD analysis tools. Finally, the Package Test Design Kit (TDK) defines how embedded chiplets are tested at various stages, from wafer sort to final system-level validation. These kits include physical test pin locations, test modes, and interface specifications essential for planning and executing test strategies.

Building a Connected Chiplet Marketplace

Beyond enabling the technical workflows, Siemens EDA envisions a broader transformation of the supply chain through a standardized chiplet marketplace. CDKs, encoded in the JEDEC part model format, can serve as entries in an electronic catalog of chiplets. This allows system designers to discover, evaluate, and select components based on standardized attributes. In the future, this marketplace could also support inventory management, procurement, and real-time supply chain visibility, thereby streamlining business transactions between chiplet suppliers and customers. This open marketplace model has the potential to democratize 3D IC design by lowering the barriers for entry and fostering innovation beyond the realm of Tier 1 hyperscalers.

Authoring Tools and Open Access Initiatives

To support the widespread adoption of 3DKs, Siemens EDA is also investing in the development of authoring tools that simplify the creation and use of machine-readable models. While many of the underlying formats are based on XML for compatibility with automated tools, XML is not user-friendly for manual editing. Siemens EDA proposes the creation of open, EDA-neutral authoring tools for ADKs and MDKs that would ensure consistency across different workflows and enable a diverse set of vendors to contribute to the ecosystem.

These tools would allow design and manufacturing stakeholders to align on a shared set of rules and material properties, ultimately enabling a more efficient and collaborative supply chain. By enabling consistent and reproducible design parameters, these tools can help generate EDA-specific PDKs that are tailored for individual design environments while maintaining a common data backbone.

Toward an Open and Scalable 3D IC Ecosystem

To date, early adoption of 3D IC technologies has been concentrated among large cloud providers and HPC-focused companies. These organizations have largely operated within closed ecosystems, building custom chiplets for high-performance compute and AI processors. While effective for their specific needs, these proprietary environments limit broader participation and reuse.

Siemens EDA is working to expand the reach of 3D IC technology by promoting open standards, reusable chiplet components, and accessible design tools. The adoption of 3DKs by foundries, OSATs, material providers, EDA vendors, and system integrators is an essential step toward realizing a scalable, heterogeneous 3D IC design ecosystem. This vision supports not only high-end computing but also emerging applications in consumer electronics, automotive systems, IoT devices, and beyond.

Summary

Heterogeneous 3D IC design represents a profound shift in how semiconductor systems are conceived, developed, and manufactured. Siemens EDA is playing a pivotal role in enabling this transition by offering a comprehensive suite of tools, standards, and workflows that make 3D ICs more accessible and scalable. Through collaborative initiatives like the CDX and the development of open, interoperable 3DKs, Siemens EDA is helping to pave the way for a future where innovative semiconductor designs, addressing not only HPC but other emerging applications too, can thrive across a truly global and inclusive ecosystem.

This topic is discussed in detail in a whitepaper from Siemens EDA and can be downloaded from here.

Also Read:

Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC

Siemens Proposes Unified Static and Formal Verification with AI

Protecting Sensitive Analog and RF Signals with Net Shielding

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Why I Think Intel 3.0 Will Succeed

Why I Think Intel 3.0 Will Succeed
by Daniel Nenni on 07-28-2025 at 6:00 am
Categories: Foundries, Intel Foundry
6 Comments

Intel 3.0 Logo SemiWiki

Probably one of the most anticipated semiconductor investor calls was held last week and it did not disappoint. It was Lip-Bu Tan’s first full quarter since he took over as CEO. In the resulting discussions on the SemiWiki Forum I am viewed as overly optimistic of Intel’s recent pivot. That is true, I am optimistic, but my observations and opinions are based on 40 years of Semiconductor experience, 30 of which included foundries such as TSMC, UMC, SMIC, Samsung, Chartered, GlobalFounderies, etc… I also co-authored a book “Fabless” on the subject so this is not an armchair quarterback piece.

As it stands today, TSMC is the dominant force in the foundry industry which is the result of 30+ years of hard work. I experienced this first hand. One of the most important parts of TSMC’s success is that they do not compete with customers. Another is that TSMC is laser focused on yield which not only builds a strong financial base but also results in customer/partner trust and loyalty.

Bottom line: When TSMC says they are going to deliver something they over-deliver, absolutely.

TSMC’s leadership should also be recognized. Dr. Morris Chang and Dr. CC Wei should be in the semiconductor CEO hall of fame along with Dr. Andy Grove, Jensen Huang, Dr. Lisa Su, and Hock Tan. These CEOs have made semiconductors what they are today, a critical part of modern life.

Intel is one of the most important, if not THE most important companies in the history of semiconductors. The innovation and technology that have spawned from Intel are too numerous to count but I could easily say that the semiconductor industry would not be where we are today without intel.

Unfortunately, being a dominant semiconductor company for so many years is a blessing and a curse. Intel lost focus, and let’s just say that the massive Intel ego was no longer serviceable.

An example of that is when Intel decided to be a foundry in 2010. I had direct experience with this and the first thing that struck me was that Intel had no idea what the foundry business really was. Career Intel executives took charge and without practical foundry experience they failed. Intel decided to get give the foundry business another try when Pat Gelsinger took charge in 2021 which again failed even though Intel brought in outside expertise.

Let’s just say, in a nutshell, the Intel culture was not foundry friendly.  The foundry business is customer centric, thanks to TSMC, and that was not the Intel way, in my opinion. An example of that is building PDKs and fabs without direct customer involvement. We call it the Field of Dreams approach where you do something and expect customers to come running. That takes a very big ego and rarely does it succeed in my experience.

In 2025 Intel landed a foundry experienced CEO. Lip-Bu Tan is a famed Venture Capitalist who joined the board of Cadence Design Systems in 2004 and accepted the CEO position in 2008. As a side note, Lip-BU replaced Mike Fister as Cadence CEO who was a career Intel executive. Let’s just say that Mike left Cadence in much worse shape than when he joined. Mike’s ego was legendary. I have known Cadence since before they were Cadence so I experienced this first hand as well.

Lip-Bu lead a significant culture change at Cadence that brought them back to a leadership position in EDA. Cadence was in decline with $1 billion in revenue in 2008. Today Cadence is a $5 billion dollar company with double digit growth.

Why am I optimistic for Intel 3.0?

First and foremost Lip-Bu Tan. Lip-Bu knows the foundry business. He was an important part of the semiconductor ecosystem and is very customer centric. I saw Lip-Bu in Taiwan many times as TSMC was not only a Cadence partner but also a big customer. In fact, all of the top semiconductor companies are Cadence customers and I can assure you Lip-Bu knows the CEOs on a first name basis.

Second, Lip-Bu is transparent, he will tell it like it is, he will not tell you what you want to hear, he will set your expectations knowing full well he will beat them. Lip-Bu may have learned this from TSMC because that is a key part of the TSMC corporate culture.

Third, Lip-Bu would not have taken this job without a plan in mind. He is not in this for money, he took this job to guarantee him a spot in the semiconductor CEO Hall of Fame. There is no other explanation, this is all about his legacy and his respect for Intel. While I do believe that Lip-Bu uncovered more problems inside Intel than he was aware of as a board member, I have complete confidence in his abilities to facilitate change.

Yes, the investor call did not sound optimistic on the foundry side, but remember, Lip-Bu Tan sets expectations so he can beat them.

What does Intel Foundry need to do to succeed? I will write about that next but Lip-Bu already knows this so it will not be a surprise to him or his consolidated executive staff.

Also Read:

Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies

Intel Foundry is a Low Risk Aternative to TSMC

Intel’s Foundry Transformation: Technology, Culture, and Collaboration

Intel Foundry Delivers!

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CEO Interview with Jutta Meier of IQE

CEO Interview with Jutta Meier of IQE
by Daniel Nenni on 07-25-2025 at 10:00 am
Categories: CEO Interviews

Jutta Meier Headshot Color Courtesy IQE

Jutta Meier is an experienced executive who has held senior positions at global semiconductor companies for over 25 years. She joined IQE in January 2024 as CFO, and was announced as IQE’s CEO in May of 2025. She joined IQE after serving at Intel Corporation as a Senior Finance Director at Intel Foundry Services, supporting Intel’s Foundry business transformation. Prior to joining Intel, Jutta served as Vice President of Finance at GlobalFoundries Inc, a global leader in semiconductor manufacturing and she also held various positions at AMD.

Tell us about your company.

IQE enables the technologies that power our everyday lives, from smartphones and data centers to electric vehicles and advanced communications systems – by engineering the compound semiconductor materials at their core. We don’t make chips; we make the epitaxial wafers that make high-performance chips possible.

For over 30 years, IQE has led in compound semiconductors. Today, we remain focused on advancing smarter, faster, more efficient technologies – responsibly and sustainably, while enabling a more connected, inclusive world.

What problems are you solving?

The world is demanding more from technology — more performance, more efficiency, more reliability — and materials are where that progress starts.

Our customers come to us when they need differentiated performance. That means improving power conversion, enabling higher data throughput, supporting ultra-small displays and pushing the boundaries of speed and miniaturization. We also help customers manage complex supply chains and cost challenges, especially as demand grows for domestic sourcing and regional resilience.

What application areas are your strongest?

We focus where performance truly matters. Today, that includes:

  • Power electronics, where GaN on silicon is improving efficiency and reducing energy loss in everything from electric vehicles to AI infrastructure.
  • RF and 5G systems, where GaN on Silicon and GaN on Silicon Carbide support ultra fast, low latency, reliable wireless performance.
  • Optical communications, where our InP-based materials are helping move data faster and more efficiently.
  • MicroLED displays, especially in RGB applications, where precision and uniformity determines display viability.
  • Photonics, where our materials support sensing, imaging, and emerging applications like LiDAR and quantum.

What unites these together is our deep expertise in epitaxy. We don’t just achiebve performance, we scale it reliably.

What keeps your customers up at night?

A few things, depending on who you ask. From a technology standpoint, it’s about staying ahead of the curve while managing risk. Reliability, scalability and supply security are always top concerns.

But more broadly, I hear a lot of concerns around readiness. Is the ecosystem ready for the next wave of demand? Is the supply chain robust enough? Are the right partners in place? That’s where we come in, not just as a materials supplier, but as a long-term strategic partner who helps solve upstream challenges before they become downstream problems.

What does the competitive landscape look like and how do you differentiate?

The landscape is evolving quickly, especially as compound semiconductors gain mainstream traction.

What differentiates IQE is our ability to combine world-class epitaxial technology with deep customer alignment. We’re not trying to be everything to everyone. We focus where we know we can make a difference: in high-performance applications where material quality, consistency, and scale really matter.

We also bring a global footprint and a proven track record, which is important for customers navigating geopolitical uncertainty. That’s been especially critical in aerospace and security, where our work supports governments’ goals of building secure and resilient domestic supply chains.

What new features or technology are you working on?

As a pioneer in GaN with 20+ years experience, we’re doubling down across power and RF, to meet demand from AI to energy infrastructure. That includes scaling GaN on Silicon, improving performance and manufacturability at the epitaxy level.

We’re pushing forward in microLED, especially RGB, where our materials can enable brighter, more efficient and immersive displays. And our work in InP-based photonics is opening up exciting possibilities in data centers, telecom, and sensing applications.

Critically, we’re innovating in process, not just materials ensuring these breakthroughs scale from lab to fab.

How do customers normally engage with your company?

In Compound Semiconductors, the device performance is set with Epitaxy. Therefore, our engagement starts early, often at the design or feasibility stage because decisions made at the epitaxy level ripple through the entire device stack.

That means a lot of collaboration, problem-solving and trust which is underpinned by long-term partnerships that span decades with some customers. We’re also engaging with new customers and players across key growth markets, helping them ramp faster by sharing our experience and technical depth.

It’s a high-touch model, but we believe it’s the best way to deliver value, especially in a space where precision, reliability and innovation are non-negotiable.

Also Read:

Executive Interview with Ryan W. Parker of Photonic Inc.

CEO Interview with Jon Kemp of Qnity

Executive Interview with Matthew Addley

CEO Interview with Jonathan Reeves of CSignum

Podcast EP299: The Current and Future Capabilities of Static Verification at Synopsys with Rimpy Chugh

Podcast EP299: The Current and Future Capabilities of Static Verification at Synopsys with Rimpy Chugh
by Daniel Nenni on 07-25-2025 at 10:00 am

Dan is joined by Rimpy Chugh, a Principal Product Manager at Synopsys with 14 years of varied experience in EDA and functional verification. Prior to joining Synopsys, Rimpy held field applications and verification engineering positions at Mentor Graphics, Cadence and HCL Technologies.

Dan explores the expanding role of static verification with Rimpy. She describes significant improvements in static verification driven by increasing design complexity. These include scaling the technology to process much larger designs, the ability to efficiently analyze many more violations, and identify a larger class of bugs earlier in the design cycle (shift left). She describes the increasing usage of AI in tools such as Synopsys VC SpyGlass to identify coding practices and constraints that can cause issues during physical implementation.

She discusses how a CDC-aware synthesis flow can avoid over- and under-constrained designs. She explains how the issues associated with implementation design checks, or IDC can result in either unreliable designs or designs with sub-optimal PPA. She describes the current and future work going on at Synopsys to avoid these issues early in the design flow with lower designer effort.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Executive Interview with Ryan W. Parker of Phononic Inc.

Executive Interview with Ryan W. Parker of Phononic Inc.
by Daniel Nenni on 07-25-2025 at 9:00 am
Categories: CEO Interviews

ryan parker
Ryan W. Parker is a seasoned executive and product leader at Phononic Inc., where he oversees high-tech product incubation and drives P&L strategy. With a robust background at Intel’s IoT Group, Ryan has successfully led multi-disciplinary teams transforming cutting-edge semiconductor and IoT technologies into scalable, market-ready products.
An alum of both Arizona State University (W. P. Carey School of Business) and Intel’s internal leadership programs, Ryan combines business acumen with technical depth. His expertise lies in guiding innovation through rigorous operational discipline, streamlining development, optimizing supply chains, and achieving measurable commercial outcomes.
Known for his collaborative leadership style, Ryan cultivates cross-functional alignment between engineering, marketing, and manufacturing. At Phononic, he’s instrumental in scaling solid-state cooling solutions that address emerging edge-compute, telecom, and medical applications with zero-refrigerant, energy-efficient hardware.
Tell us about your company.

Phononic is changing the way datacenters cool.  We’re bringing solid-state technology to an industry that’s long overdue for a smarter approach.  Our first focus is transceivers that fit in tight spaces, with highly localized power, and no room for error.  That’s where we’re making an immediate difference.  Long-term, we’re building the thermal layer that AI infrastructure needs to scale.

What problems are you solving?

AI is pushing more power through the datacenter than ever before, and it’s generating heat that traditional cooling can’t handle.  We started with transceivers because they’re compact, high-density, and performance sensitive.  Our platform helps customers avoid throttling, cut energy use, and get more out of what they already have.

Where are you focused?

Right now, transceivers.  It’s a clear bottleneck with a fast ROI.  However, the same challenges exist across the datacenter, and our platform is built to meet these needs.

What keeps your customers up at night?

They’re trying to scale AI deployments but running into thermal and power walls.  They don’t want to rip and replace, they want a way to unlock performance with the systems they already trust.  That’s exactly what we’re doing, while also building for the future.

How do you differentiate?

Most cooling is fixed and passive.  Ours adapts.  It’s responsive, localized, and tuned to actual system loads.  That means better performance and less waste.  Also, since we own the full IP stack, we can work directly with customers to deliver solutions, not just parts.

What’s next?

While we’re focused on transceivers today, we’re already seeing strong interest in applying our platform more broadly.  The demand is growing, and we’re actively building toward that expansion.

How do customers engage?

We don’t just sell parts, we solve real problems.  Our customers know where the system constraints are, and we bring the thermal tech to break through them.  It’s a hands-on partnership built around performance and shared expertise.

Also Read:

CEO Interview with Jon Kemp of Qnity

Executive Interview with Matthew Addley

CEO Interview with Jonathan Reeves of CSignum

CEO Interview with Shelly Henry of MooresLabAI

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CEO Interview with Jon Kemp of Qnity

CEO Interview with Jon Kemp of Qnity
by Daniel Nenni on 07-25-2025 at 8:00 am
Categories: CEO Interviews

Jon Kemp Bio

Jon Kemp is President of the Electronics division for DuPont and Chief Executive Officer-Elect for Qnity, the planned independent Electronics Company, which will be an independent, publicly traded company spun off from DuPont’s (NYSE: DD) Electronics business upon completion of the intended separation on November 1, 2025.

With more than a decade of leadership experience in electronics at DuPont, Jon’s strategic vision set a pathway for significant portfolio growth. As president of the Electronics & Industrial business, Jon designed business strategy and operations to capitalize on market trends undergoing a major portfolio transformation and growing the business to nearly $6B in net sales in 2024.

Jon’s career at DuPont began in 2005, where he held several key roles, including President of Electronics and Communications and Global Business Director for Circuit & Packaging Materials. After the merger of DuPont and Dow in 2017, he led strategy and M&A for the newly formed Specialty Products Division.

Jon serves on the International Board of Directors for SEMI, where he chairs the Board of Industry Leaders.

Tell us about your company?

DuPont is targeting November 1, 2025, for the completion of its spin-off of the Electronics business, to be called Qnity. While the name is new, our legacy is longstanding. Driven by a purpose to make tomorrow’s technologies possible, Qnity will be one of the largest global leaders in electronic materials and solutions for the semiconductor and advanced electronics industries. As the partner of choice for our customers today, we have a seat at the design table working to advance their technology roadmaps through materials science and engineering solutions that the next generation of advanced computing and connectivity applications require. Qnity will have about 10,000 employees, 40 manufacturing sites, and nearly 20 R&D facilities strategically located near our customers to enable the speed of innovation.

Speaking of the name (pronounced cue-ni-tee), it’s inspired by the symbol for electrical charge, “Q,” and “unity” — a nod to our history and collaboration model with customers. Our electronics portfolio dates back more than 50 years, with a reputation built on speed, quality, and reliability. Looking forward, Qnity will be a global leader in differentiated electronic materials — supplying key consumables used in semiconductor chip manufacturing, advanced electronic materials for packaging and interconnects, thermal management, and innovative assembly and display technologies. We bring a unique, end-to-end perspective on the electronics value chain, and we’re excited about what’s next.

What problems are you solving?

The convergence of industry mega trends like advanced computing and advanced connectivity is accelerating the pace of innovation. AI and related investments are driving an acceleration of digitization and electrification across different industries, including data centers, electric and autonomous vehicles, smart consumer electronics, aerospace, manufacturing, and beyond. These cutting-edge technologies bring new, complex challenges that require a mix of materials science and engineering expertise. At Qnity, we’re committed to a mindset of continuous improvement to address key issues in high-performance computing, thermal management, signal integrity, energy efficiency, miniaturization, and more.

What application areas are your strongest?

We play a critical role partnering with the world’s semiconductor and advanced device manufacturing leaders for semiconductor chip manufacturing, advanced packaging and interconnects, displays, and more. I’ll break that down into a couple of key areas.

For semiconductor technologies, we offer products and expertise that improve chip performance, enhance manufacturing yields, and enable leading-edge node technology for multiple stages of the semiconductor manufacturing process, especially in chemical mechanical planarization (CMP) and lithography.

For interconnects, we provide material solutions that enable the seamless connection of various electronic components to address signal integrity, thermal and power management, advanced packaging, and circuitry technologies.

What keeps your customers up at night?

Supply chain reliability and resiliency is a big concern for customers. In recent years, the COVID-19 pandemic tested the capabilities of supply chains worldwide. Based on what we learned, we adjusted our strategies to emphasize a continuous improvement mindset and stronger local network across our entire business. As a result, we’ve strengthened our entire network — working closely with suppliers and customers alike to boost speed, agility, and reliability. We are committed to supporting our customers with continuous investments in end-to-end supply chain and manufacturing processes, including quality measurement, automation, rapid design and prototyping, and supply chain management.

Sustainability also continues to be top of mind. Customers are increasingly focused on meeting their goals around material usage, waste, and energy efficiency, and they rely on us to provide innovative materials and solutions that help them get there. We’re committed to embedding sustainability throughout our innovation pipeline to support those efforts.

What does the competitive landscape look like and how do you differentiate?

Our competitors range from large multinational corporations to smaller, more specialized regional players. Our global scale, strategic operational footprint, world-class process technologies, and robust portfolio that enables us to work both up and down the electronics value chain make us a compelling partner for our customers.

Simply put, we’re designed to facilitate optimal customer collaboration with strong product performance and consistency, high quality, and reliable supply. We’re focused on providing the materials that enable their technology roadmaps and ultimately power the next generation of semiconductor and other advanced electronics applications.

What new features/technology are you working on?

Partnering from the start of the design process through delivery of high-volume manufacturing, we have a seat at the design table working to advance customers’ technology roadmaps. We support the most advanced designs in both logic and memory (including N3, N2, advanced DRAM, and HBM), advanced packaging (including 2.5D, 3D, and heterogeneous integration), and thermal management while helping customers achieve improved performance, efficiency, and sustainability.

We’ve recently announced new product launches in chemical mechanical planarization (CMP) pads, post-CMP cleans, high-selectivity etchants, photoresists, and extreme ultraviolet lithography (EUV) underlayers for semiconductor chip manufacturing, as well as thermal solutions to achieve superior thermal performance and long-term stability for next-gen server and data center applications.

How do customers normally engage with your company?

Our disciplined and experienced team is laser focused on delivering value for our customers. We have a strong track record of collaborating to empower advanced technology roadmaps, working side by side at the design table with customers’ technology and engineering teams. This partnership extends from the laboratory to the manufacturing line, where we work to optimize and customize our solutions to maximize yields and performance in our customers’ manufacturing processes. We’re excited to continue building on this approach, looking to bring an even greater speed of innovation, higher quality, and more reliable supply to our customers.

If you have a technology challenge or want to learn more about what we’re working on next, get in touch with our team at qnityelectronics.com.

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Griffin Securities’ Jay Vleeschhouwer on EDA Acquisitions and Startups

Griffin Securities’ Jay Vleeschhouwer on EDA Acquisitions and Startups
by Bob Smith on 07-25-2025 at 6:00 am
Categories: EDA

jay vleeschhouwer SemiWiki Interview

Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, is a noted financial analyst who does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). This year was no exception. He and I spent a memorable afternoon discussing the Synopsys-Ansys merger and startups. A condensed version of our talk follows.

Big EDA includes Cadence, Siemens EDA and Synopsys, Ansys and Keysight. Now that the Synopsys-Ansys merger closed, do you see changes in the landscape?

Since this combination occurred, it is the largest Engineering Software company on the planet by revenue and by backlog.

In terms of financial profile, this is by far the largest company in all of Engineering Software, a well over $30-billion industry, including all the parts of that market—AEC, EDA and Technical Software. Synopsys plus Ansys is the largest part of that. The pro-forma backlog is the largest in the industry.

From an operational or strategy point of view, Ansys EDA is roughly a fifth of Ansys’ business, making it the fourth largest EDA company. Combining the largest EDA company with the fourth largest, Synopsys will pick up another roughly three and a half points of market share from Ansys’ EDA.

More broadly, the question is how Synopsys will integrate, employ and leverage the four fifths of Ansys that is not strictly EDA. It’s not Ansoft and Apache, the two entities that mostly comprise Ansys’ EDA, and it ties into the convergence theme.

We pointed out that this is more than $30-billion manifestation of convergence. Keysight, on a smaller scale, is pursuing its strategy for convergence through acquisitions, including last year’s acquisition of ESI, a small French simulation software company. Two pending Keysight acquisitions will be made in the photonics and optical area. Both are conditional upon the close of the acquisition of Ansys, something that the regulators required as a condition of approval.

This will certainly build out the Engineering Software portfolio for Keysight and is complementary to what they’re doing. They, too, speak about multi-physics in the same way that Ansys has been speaking about multi-physics as part of its strategy for years. Of course, Synopsys acquired the largest multi-physics software company on the planet with Ansys. In terms of changing the landscape, that is a function of the four fifths of Ansys that is not EDA, because the one fifth has already been working closely with Synopsys since their 2017 technical integration agreement. That will help smooth the integration, at least in terms of whether their products are integrated.

Beyond that, there’s always the question in any acquisition as to the balance between leaving the operations and the portfolios as they were. In other words, let them continue doing what they were doing if they were doing it well and/or absorbing, integrating and leveraging those portfolios into the buyer’s portfolio.

That roadmap is something that we would be interested in hearing more about in terms of its purely EDA aspects and then the convergence aspects. It will also be interesting to see if they update the initial revenue and cost synergies from SNUG in March 2024. They gave some specific revenue and cost synergies that they foresaw in terms of combined products and cost savings, which would seem to be, on the cost side, achievable.”

Will this make it harder for startups?

It’s always hard for startups in this industry because they have so much to prove when Synopsys, Cadence and Siemens are investing substantial amounts necessary in their portfolios. Opportunities for startups will always be a function of provable, superior performance in critical areas.

One of the interesting things for investors is how much of the technology requirements are foreseeable. The semiconductor roadmap is so well laid out and defined in terms of nodes that you can work backwards to what critical tools will be needed to solve new or upcoming problems. Opportunities are there for startups to correctly identify what those needs are and then be able to prove sufficiently superior performance in benchmarks for engineering groups to adopt a proof-of-concept tool or complementary tool.

The fact that the two largest companies have accumulated so much more share organically and inorganically and cover so much more of the EDA portfolio landscape, makes it’s harder for startups. I wouldn’t want to say it isn’t possible or it’s infeasible, but we know what the benchmarks or conditions for success have to be.”

About Jay Vleeschhouwer

Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, has more than 40 years of research analyst experience in the technology sector, including software, semiconductors and computer hardware. Vleeschhouwer does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). The slides can be found at: DAC presentation (June 2025) 2.pdf

Note: The ESD Alliance will host a three-hour design track “The Convergence of Semiconductor Manufacturing and Design” Tuesday, October 7, from 1 p.m. until 4 p.m. during SEMICON West in Phoenix, Ariz.

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Security Coverage: Assuring Comprehensive Security in Hardware Design

Security Coverage: Assuring Comprehensive Security in Hardware Design
by Daniel Nenni on 07-24-2025 at 10:00 am
Categories: Cycuity, Security

Assuring Comprehensive Security in Hardware Design

As hardware systems become increasingly complex and security threats grow more sophisticated, ensuring robust hardware security during the pre-silicon phase of development is more critical than ever. Cycuity’s white paper outlines how its Radix platform enables engineers to verify, visualize, and measure the effectiveness of hardware security throughout the design lifecycle, ultimately ensuring compliance, minimizing vulnerabilities, and building trust with customers, auditors, and regulators.

Radix provides security coverage through a data-driven approach that quantifies how thoroughly security verification has been applied to a hardware design. Like functional coverage in traditional verification, security coverage ensures that protection mechanisms and policies are not only in place but are rigorously exercised and validated during simulation or emulation. This enables design teams to identify and address vulnerabilities early, avoiding expensive post-silicon fixes and reducing overall risk.

The verification of hardware security features is split into two main activities: functional security verification and security protection verification. Functional security verification ensures that security components behave as expected. For example, a test might check whether a cryptographic key reaches the AES encryption block within a specified time frame when requested. This aspect of verification is often addressed using traditional techniques like formal verification, assertions, and directed tests.

In contrast, security protection verification addresses broader questions, such as whether sensitive data might inadvertently escape a chip’s boundary. This approach verifies that protections are in place to prevent unintended or unauthorized data flows, and it enables a more system-level perspective. While functional verification focuses on specific, localized behaviors, protection verification considers the full design over extended time periods and wider spatial contexts.

Cycuity’s Radix technology supports both types of verification and introduces security coverage metrics to evaluate the thoroughness of these efforts. These metrics show how well security requirements—like ensuring a key never exits a secure module—have been tested under various conditions. The platform allows security teams to define assets, specify security rules, and track whether these rules are upheld in practice. When rules are violated or not sufficiently exercised, Radix offers powerful debug tools including waveform, RTL, and schematic views that pinpoint information flow issues.

The concept of a protection boundary is central to Radix’s methodology. This refers to circuit logic that confines secure data within specific areas, preventing leakage or misuse. For instance, a control signal might be required to gate the release of encrypted data, thereby establishing a hardware-based boundary. Security coverage tracks whether this boundary has been properly implemented and whether all relevant paths leading to and from it have been adequately tested.

To calculate security coverage, Radix monitors information flow between a source (like a secure key) and its destination (such as a system output). Toggle coverage—a standard verification metric used to track how often signals change—is collected across test runs and merged into a comprehensive database. Radix then analyzes this database to produce a security coverage metric, which is visualized through its user interface. This GUI highlights problem areas and enables cross-probing into schematics and RTL code for further analysis.

Low security coverage may result from several factors, including misconfigured protection boundaries, insufficient test coverage, or flawed RTL implementations. Radix helps identify the root cause and allows teams to adjust designs or add targeted tests. This iterative process is akin to achieving functional coverage and is essential for preparing a design for final security signoff.

The value of security coverage extends beyond internal development. The reports generated by Radix offer credible, visual, and actionable evidence of compliance with standards like ISO 21434 and the NIST cybersecurity framework. These reports are useful for customers, regulators, and auditors seeking transparency and assurance.

In conclusion, Cycuity’s Radix platform brings much-needed rigor and visibility to pre-silicon hardware security. By defining, measuring, and analyzing security coverage, Radix empowers engineering teams to deliver secure silicon with confidence. It bridges the gap between design intent and implementation reality, helping organizations not only meet compliance requirements but also enhance trust, accountability, and resilience in their hardware products.

You can download this whitepaper here.

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Cycuity at the 2024 Design Automation Conference