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Simulating Gate-All-Around (GAA) Devices at the Atomic Level

Simulating Gate-All-Around (GAA) Devices at the Atomic Level
by Daniel Payne on 09-17-2025 at 10:00 am
Categories: EDA, Silvaco

GAA FET min

Transistor fabrication has spanned the gamut from planar devices o FinFET to Gate-All-Around (GAA) as silicon dimensions have decreased in the quest for higher density, faster speeds and lower power. Process development engineers use powerful simulation tools to predict and even optimize transistor performance for GAA devices. Dr. Philippe Blaise, Principle AE at Silvaco delivered a webinar on the topic of simulating GAA devices using their tool, Victory Atomistic with quantum-level precision.

An overview diagram shows the different FET device structures in 3D cross-sections.

The big challenge is how to simulate a GAA FET and predict its performance at the nano scale with quantum effects, easy for a TCAD engineer to use, fast enough to enable exploration and optimization, and accurate enough to produce trusted SPICE models. Silvaco uses the Non Equilibrium Green’s Function (NEGF) approach in their device simulation.

Using Victory Atomistic looked straight forward, where the user chooses a material from a database, defines the device structure, then the simulator solves density using NEGF equations and solves potential using Poisson’s equation, producing an output IV curve.

Dr. Blaise showed the details of the device template for a nanowire using a diamond crystal structure in Silicon, with lengths, number of gates, doping, oxide and contacts. Users also choose the type of solver, voltage ranges, temperature and output options. The goal of Victory Atomistic is to enable atomic-scale TCAD simulations easy to use by keeping the complexity inside the tool.

Simulation results showed the desired accuracy, along with options for silicon bands and orientation. Victory Atomistic uses the Low-Rank Approximation (LRA) optimization technique to make the complex, quantum-level simulations run in a short period of time on conventional computers.

SiGe materials were simulated using Virtual Crystal Approximation (VCA). Transition-metal dichalcogenide (TMD) monolayers were also simulated for MoS2. Electron-phonon scattering effects were modeled next. Victory Visual was demonstrated as a graphical post processing tool, showing 90,000 atoms loaded.

Simulation results for a GAA FET device showed accurate results across a temperature range of 300K to 2K.

Summary

GAA FET devices can be accurately modeled and simulated using the NEGF algorithm, so that TCAD engineers can predict and optimize a new process technology. Silvaco has made their Victory Atomistic tool easy to use, and the results are produced quickly with the option to employ multiple CPUs. Victory Visual helps to graphically show results, making analysis more intuitive. Simulating a process technology before running wafers saves time and money, so why not give modern TCAD tools a try.

View the entire webinar after registering online here.

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AI Revives Chipmaking as Tech’s Core Engine

AI Revives Chipmaking as Tech’s Core Engine
by Daniel Nenni on 09-17-2025 at 8:00 am
Categories: AI, Foundries, Intel Foundry

The Economist

A century ago, 391 San Antonio Road in Mountain View, California, housed an apricot-packing shed. Today, it’s marked by sculptures of diodes and a transistor, commemorating the 1956 founding of Shockley Semiconductor Laboratory—the birthplace of Silicon Valley. William Shockley, co-inventor of the transistor, aimed to craft components from silicon, but his firm flopped. Yet, his “traitorous eight” employees defected in 1957 to launch Fairchild Semiconductor nearby. This group included Gordon Moore and Robert Noyce, who later co-founded Intel, and Eugene Kleiner, pioneer of venture capital firm Kleiner Perkins. Most Silicon Valley giants trace their lineage to these early innovators.

Semiconductors revolutionized computing. Pre-semiconductor era computers relied on bulky, unreliable vacuum tubes. Semiconductors, solid materials controlling electrical flow, offered durable, versatile alternatives. Silicon enabled mass production of transistors, diodes, and integrated circuits on single chips, processing and storing data efficiently.

In 1965, Moore observed that transistor density on chips doubled annually (later adjusted to every two years), an observation dubbed Moore’s Law. This drove exponential progress: from 200 transistors per square millimeter in 1971 to 150 million in AMD’s 2023 MI300 processor. Smaller transistors switched faster, fueling breakthroughs like personal computers, the internet, smartphones, and artificial intelligence.

Chipmakers once dominated tech. In the 1970s, IBM integrated chips, hardware, and software into unparalleled dominance. The 1980s saw Microsoft’s software-only model thrive, but Intel’s processors remained vital. By 2000, Intel ranked sixth globally by market cap. Post-dotcom bust, however, firms like Google and Meta overshadowed hardware, commoditizing chips. Venture capitalist Marc Andreessen famously declared software was “eating the world” in 2011.

AI’s surge has reversed this. Training LLMs demands immense computation. Pre-2010, AI training compute doubled every 20 months, aligning with Moore’s Law. Since then, it doubles every six months, spiking chip demand. Nvidia, specializing in AI-suited GPUs, now ranks third-most valuable globally. Since late 2023, chipmaker stocks have outpaced software firms for the first time in over a decade.

Beyond training, AI inference, responding to queries, requires efficient, bespoke chips. General-purpose processors fall short, prompting tech giants to design custom silicon. Apple, Amazon, Microsoft, and Meta invest heavily; Google deploys more proprietary data-center processors than anyone except Nvidia and Intel. Seven of the world’s top ten firms now make chips.

Sophistication hinges on process nodes—feature sizes under 7nm define cutting-edge AI chips. Yet, over 90% of manufacturing uses 7nm or larger nodes for everyday devices like TVs, fridges, cars, and tools.

The 2021 COVID-19 chip shortage exposed vulnerabilities in global supply chains: design in America, equipment in Europe/Japan, fabrication in Taiwan/South Korea, packaging in China/Malaysia. Governments responded with subsidies—America’s $50 billion CHIPS Act in 2022, followed by $94 billion from the EU, Japan, and South Korea. Geopolitics complicates matters: U.S. export bans limit China’s access to advanced tech, prompting Beijing’s restrictions on key materials like gallium and germanium.

Yet, technological hurdles loom larger than political ones, argues Economist Global Business Writer Shailesh Chitnis. For decades, shrinking transistors boosted performance without proportional energy hikes. Now, denser chips and massive AI models drive soaring power use. Data centers could consume 8% of U.S. electricity by 2030.

To sustain exponential gains, innovations are essential. Incremental steps include hardware-software integration, like optimizing algorithms for specific chips. Radical shifts involve alternatives to silicon, such as gallium nitride for efficiency, or neuromorphic computing mimicking brain analog processes over digital ones. Optical computing, using light for faster data transfer, and quantum chips for complex simulations also promise breakthroughs.

AI’s demands are putting silicon back at tech’s heart, echoing Valley origins. As computation needs explode, chipmaking’s evolution will dictate future innovation, balancing efficiency, geopolitics, and sustainability. The apricot shed’s legacy endures—silicon’s story is far from over.

You can read the full article here.

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Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology

Revolutionizing Processor Design: Intel’s Software Defined Super Cores

Intel’s Commitment to Corporate Responsibility: Driving Innovation and Sustainability

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The IO Hub: An Emerging Pattern for System Connectivity in Chiplet-Based Designs

The IO Hub: An Emerging Pattern for System Connectivity in Chiplet-Based Designs
by Bernard Murphy on 09-17-2025 at 6:00 am
Categories: AI, Arteris, Automotive, IP

Disaggregation of NoCs min

In chiplet-based design we continue the march of Moore’s Law by scaling what we can put in a semiconductor package beyond the boundaries of what we can build on a single die. This style is already gaining traction in AI applications, high performance computing, and automotive, each of which aims to scale out to highly integrated systems meeting performance, power, cost, and reliability goals. The technology challenge then is to build effective communications infrastructure between those chiplets.

UCIe is mentioned frequently as the standard for connectivity between chiplets. That standard is important, but is only the bottom layer of the communication stack. In the modern era of networks-on-chip (NoCs), modern networks must also handle packetized communication, congestion, and quality of service, within chiplets and between chiplets. This prompts a deeper dive into Arteris’ recently announced collaboration with AMD, in which FlexGen smart NoC IP cooperates with AMD’s Infinity Fabric. Commercial and proprietary network co-existence has arrived.

Commercial NoC IP jumps a hurdle

For a long time NoC IP choices were an either/or decision. Build and use your own in-house NoC IP or buy a commercial IP. The choice was easy for new ventures or design teams who had outgrown earlier in-house options and who prioritized differentiation in core functions rather than in the communication fabric. Buy a commercial option from an IP supplier and work with that vendor to ensure they keep up as requirements evolved. Still, some semiconductor houses, particularly the big compute vendors like AMD and Intel, continue to see value in their proprietary NoC IP and were not obvious candidates for a commercial option.

Chiplet-based design seems to have scaled that wall. Highly optimized in-house communication IPs such as Infinity Fabric continue to be central in coherent compute chiplets but now AMD’s endorsement of using FlexGen smart NoC IP between chiplets has shown co-existence to be a very viable option.

Andy Nightingale (VP Product Management and Marketing at Arteris) told me that the term IO Hub is now commonly used to represent an emerging architectural pattern, a structure to bridge coherent fabrics (such as Infinity Fabric) with heterogeneous subsystems. A new realization that one unified fabric architecture may not be the optimal strategy across chiplet-based systems.

I asked Andy why some of their top-tier customers are turning to Arteris for this capability. Why not just build their own IO Hub? Their answer reflects what you’ll often hear when design houses choose a commercial solution over an in-house option. They want to prioritize in-house resources towards their core competencies, using a proven partner to handle off-chiplet communication. A co-existence solution meets that objective.

Digging a little deeper

The physical connectivity between chiplets will most commonly be wires, not active elements (also possible but that style of connectivity is more expensive I am told). Traffic management through the IO Hub is therefore handled through distributed control from chiplet interfaces (network interface units for Arteris IPs) to the hub. In the IO hub use-case FlexGen is optimized for non-coherent, high-bandwidth data flows like HBM, PCIe, and AI accelerators.

Effectively managing this structure – off-chip interconnect topology, adding buffers/ adapters, scaling wide datapaths, managing QoS, is a complex task that will probably demand iteration as the larger design evolves. That task usually must be handled by a senior NoC designer, consuming weeks of effort. Arteris’ FlexGen smart NoC technology acts as a virtual senior NoC engineer to automate this function, providing when compared with manual design up to 10x productivity improvement, 30% shorter wirelength and 10% reduced latency according to announced customer benchmarks.

Expanding Arteris reach

Arteris’ FlexGen NoC IP for non-coherent networks and Ncore for coherent networks are already well-established, particularly in new ventures, AI, automotive and many other applications. Arteris have announced a range of co-existence collaborations including:

  • Adoption by AMD to augment Infinity Fabric for AI chiplets
  • Accepted in the Intel Foundry AI + Chiplet Alliance
  • Adopted by Samsung LSI to use FlexNoC/FlexGen alongside proprietary fabric in mobile and AI SoCs
  • Adopted by NXP using Ncore and FlexNoC for automotive, integrating safety and accelerators in ASIL D systems
  • Publicly announced benchmarks from SiMa.ai showing increased productivity and reduced wirelengths

It’s now quite clear that Arteris can now augment proprietary NoC solutions in addition to providing comprehensive NoC fabric solutions, as already demonstrated in widespread adoption in multiple markets. Impressive. You can learn more about Arteris HERE.

Also Read:

Arteris Simplifies Design Reuse with Magillem Packaging

Arteris at the 2025 Design Automation Conference #62DAC

Arteris Expands Their Multi-Die Support

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Future Horizons Industry Update Webinar IFS 2025

Future Horizons Industry Update Webinar IFS 2025
by Daniel Nenni on 09-16-2025 at 2:00 pm
Categories: Events, Future Horizons, Semiconductor Services

Four Horsemen of the Semiconductor Apocolypse 2025

The Future Horizons Industry Update Webinar, presented today by Malcolm Penn, provides a comprehensive analysis of the semiconductor industry’s current state and future trajectory. Founded in 1989, Future Horizons leverages over 300 man-years of experience, emphasizing impartial insights from facts (e.g., IMF economy data, WSTS units/ASPs, SEMI capacity), sentiment (hype vs. reality), and decades of expertise. The agenda covers industry updates, outlooks on economy, unit demand, capacity, and ASPs, market forecasts for 2025-2026, key takeaways, and Q&A.

Malcolm opens by highlighting “truly extraordinary times,” driven by Trump 2.0’s “America First” agenda, which abandons free trade norms, raises tariffs to 1930s levels, and pivots to national interests. Geopolitical tensions—Netanyahu’s Gaza actions, Putin’s Ukraine aggression, Xi’s Taiwan threats—and China’s rise as a superpower challenge U.S. dominance, shattering post-WWII peace.

The market outlook is mixed: 1H-2025 growth relies on ASPs from the AI data center boom, masking non-AI weaknesses, excess CAPEX, and bloated inventories. Doubts emerge on AI’s ROI amid “insane” spending, with YoY revenue plateauing and a fragile U.S. economy. For 2H-2025, expect more of the same plus worsening economics, urging preparation for an AI “hangover” in a head (fundamentals) vs. heart (frenzy) battle.

Framing the analysis around the “Four Horsemen of the Semiconductor Apocalypse”:
  • Economy: Precariously unclear, with “tenuous resilience amid persistent uncertainty” (IMF July 2025). U.S. defies gloom, but EU/China stagnate; Trump shocks absorbed but risks linger. U.S. cost-of-living fears (70% worry income lags inflation) and Fed’s dual mandate conundrum (employment vs. prices) add pressure, with a September 17 rate cut a “dead certainty” but damned either way.
  • Unit Shipments: Yet to recover fully; July at 7.6b/week, 8% below peak, with unmeasured excess inventory choking supply chains (20b repaid of January’s 58b excess). Real recovery awaits unit growth resumption.
  • Capacity: CapEx stubbornly high at ~15% of SC sales vs. 11% trend, abnormal post-2022 crash. China is the culprit, accelerating to 34% global share (decoupling/tariffs-driven), 3x justifiable levels, focusing on non-leading edge but advancing (e.g., Huawei/SMIC 5/7nm). Domestic WFE vendors rise, closing markets; turning CapEx to capacity proves challenging (US$50-100b lost). India now ramps up ambitiously.
  • ASPs: Strong recovery from June 2022 crash ($1.11 to $1.85 peak), but plateauing/oscillating since December 2023. All sectors retreat except logic (TSMC’s SoC pseudo-monopoly holding prices). Long-term trend reverts to $1 (Moore’s Second Law), with disruptions temporary.

Forecasts: 2025 at +16% ($731.6b, range 15-17%), ASP-driven with early recovery in discretes/opto/analog; 2026 at +12% ($813.1b, range 6-18%), assuming no AI slowdown, stable geopolitics/economy, and unit rebound. Risks include AI crash, China dumping, overcapacity on mature nodes.

Bottom line: Technology roadmap to 2039 (GAA transition challenging, four-horse race: TSMC N2, Intel 18A, Samsung SF2, Rapidus 2nm). Power semis favor silicon over SiC/GaN/diamond; Makimoto’s Wave holds through 2037 (chiplets next). Packaging evolves from begrudging to enabling (ASATs vs. foundries). Next disruption: quantum computing, not AI (just improved tools). AI data center “madness” (e.g., 10GW plants, underwater/floating) and smart glasses echo 1970s watch disasters—ego over wisdom, fruition decades away. Chip drivers remain Moore’s Law, legislation, A/D conversion, geographic shifts—entertaining, drudgery-removing, enabling impossibles.

Malcolm also warns of structural risks (excess capacity, low utilization, economic tilts to bear), urging caution amid AI hype. Promotes monthly reports for tracking fundamentals., The next webinar January 20, 2026 which will be a must see round-up of 2025.

Also Read:

MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency

Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology

Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet

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Something New in Analog Test Automation

Something New in Analog Test Automation
by Daniel Payne on 09-16-2025 at 10:00 am
Categories: EDA, Siemens EDA

IJTAG min

Digital design engineers have used DFT automation technologies like scan and ATPG for decades now, however, analog blocks embedded within SoCs have historically required that a test engineer write tests that require specialized expertise and that can take man-months to debug. Siemens has a long history in the DFT field, SPICE circuit simulation and AMS simulation, so it was a natural fit for them to announce analog component testing as part of a new product dubbed Tessent AnalogTest. I had a video call with Etienne Racine, Product Manager, Tessent to understand what’s new.

Testing analog components inside an SoC drives up the test costs, so there’s impetus to reduce this time through automation techniques. Scan for digital has now been extended into the analog realm. There’s an that talks about a novel DFT and ATPG technique that has minimal area and performance impact, and Tessent AnalogTest uses it as part of its technology.

Using such scan-based analog tests reduces defect simulation times from days to minutes and brings to analog very similar benefits as what digital scan and ATPG provided to digital designs several decades ago. Leveraging evolutive standards thus becomes important for broad adoption and EDA industry support.

IEEE P2427 is both a working group and draft standard that gives a standardized approach for analog defect modeling and coverage in Analog Mixed-Signal (AMS) devices, where the defect universe contains all likely defects, and also defines detectable defect coverage. The test idea is to inject a defect in the netlist, run a SPICE circuit simulation and then measure the effects to see whether the resulting fault is detected.

Users of Tessent AnalogTest can also use the IJTAG framework to enable portable and retargetable AMS function tests, defined in the IEEE P1687.2 standard. There’s a learning curve with the Instrument Connectivity Language (ICL) and Procedural Description Language (PDL) to describe the analog test access, instruments and analog test mechanisms. The automation helps users to create those files when they don’t already exist.

Figure 1: Example of a digital IJTAG network used to access an analog block during tests.

Test engineers write PDL for the AMS block, like force 2.5V on this pin, then measure the current on another pin. Tessent AnalogTest reads the PDL file, then creates a simulation test bench automatically. The Siemens tool also reads in the SPICE netlist for the AMS blocks, runs the SPICE simulator to detect injected defects, then reports coverage achieved. Two Siemens simulators are supported for analog defect/fault simulation and detection, AFS or Symphony.

This new approach with Tessent AnalogTest combining digital scan-based tests and analog IJTAG measurements improves AMS test coverage plus reduces test development and application times. When silicon arrives, your team can optimize defect coverage or yield, eventually extending this to automated defect analysis. Safety critical applications that use ISO 26262 functional safety metrics will benefit from this approach with a consistent, simulated, automated test description.

Learning and using the high-level PDL language to describe intended test sequences is a big time saver, freeing up engineering resources. IJTAG is well understood by test teams, so expanding that to include analog blocks is an easy process. The Tessent AnalogTest tool automates the creation of DFT circuitry along with test patterns to test most analog circuits in under 1ms on digital-only testers. Even the test times get reduced 10X-100X while providing similar defect coverage to specification tests.

Structural test waveforms, multiple outputs tested concurrently

AMS designs now have new automation technology to dramatically improve analog test development and reach coverage goals, while being connected with IJTAG scan chains and an analog test bus. Siemens has introduced something not seen before, so it’s exciting times. Following the IEEE standards P2427 and P1687.2 ensures that this technology will be supported by the EDA industry going forward.

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MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency

MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency
by Daniel Nenni on 09-16-2025 at 6:00 am
Categories: AI, Foundries, TSMC
4 Comments

2nm

MediaTek’s first chipset using 2nm technology expected in late 2026

MediaTek, a global leader in fabless semiconductor design, has announced a groundbreaking achievement in its partnership with TSMC. The company has successfully developed a flagship system-on-chip (SoC) utilizing TSMC’s cutting-edge 2nm process technology, with volume production slated for late 2026. This milestone reinforces the long-standing collaboration between MediaTek and TSMC, which has consistently delivered high-performance, power-efficient chipsets for applications spanning flagship mobile devices, computing, automotive, data centers, and more.

TSMC’s 2nm process technology introduces a nanosheet transistor structure, a significant leap forward in semiconductor design. This innovative architecture enables substantial improvements in both performance and power efficiency, setting a new standard for advanced chipsets. MediaTek’s first 2nm-based chipset, expected to debut in late 2026, will leverage these advancements to deliver unparalleled capabilities across a wide range of devices and industries.

Compared to TSMC’s current-generation N3E process, the N2P technology offers remarkable enhancements: up to an 18 percent increase in performance at the same power level, approximately 36 percent reduction in power consumption at equivalent speeds, and a 1.2x increase in logic density. These improvements translate into faster, more energy-efficient chips that can handle the increasing demands of modern applications, from AI-driven computing to high-performance mobile devices and energy-conscious automotive systems.

“MediaTek’s innovations powered by TSMC’s 2nm technology underscores our industry leadership, as we continue to push forward with the most advanced semiconductor process technologies available for a variety of devices and applications,” said Joe Chen, President of MediaTek. “Our long history of close collaboration with TSMC has led to incredible advancements in solutions for our global customers, offering the highest performance and power efficiency from the edge to the cloud.”

Dr. Kevin Zhang, Senior Vice President of Business Development and Global Sales and Deputy Co-COO of TSMC, echoed this sentiment: “TSMC’s 2nm technology represents a significant step forward into the nanosheet era, demonstrating our relentless dedication to fulfilling our customers’ needs – tuning and improving our technologies to deliver energy-efficient computing capability. Our ongoing collaboration with MediaTek focuses on maximizing enhanced performance and power capabilities across a wide range of applications.”

This development marks a pivotal moment in the semiconductor industry, as MediaTek and TSMC continue to drive innovation in chip design and manufacturing. The adoption of nanosheet transistors in the 2nm process enables greater scalability and efficiency, addressing the growing complexity of modern devices. From smartphones and AI-powered PCs to smart homes, high-performance computing, and AI data centers, MediaTek’s 2nm chipset is poised to redefine performance standards while prioritizing energy efficiency.

MediaTek’s commitment to advancing transformative technologies such as AI, 5G/6G, and Wi-Fi 7/Wi-Fi 8 positions the company at the forefront of the industry. Powering over 2 billion connected devices annually, MediaTek’s solutions are integral to creating a smarter, more connected world. As a trusted partner to leading global brands, the company continues to innovate, ensuring that its high-performance, power-efficient products meet the evolving needs of consumers and businesses alike.

The successful tape-out of MediaTek’s 2nm chipset is a testament to the strength of its partnership with TSMC and its dedication to pushing technological boundaries. By leveraging TSMC’s state-of-the-art 2nm process, MediaTek is well-positioned to deliver next-generation solutions that enhance everyday life and drive the future of connectivity and artificial intelligence.

About MediaTek
MediaTek is a global leader in fabless semiconductor design, providing innovative solutions from edge to cloud. Powering over 2 billion connected devices annually, MediaTek drives advancements in AI, 5G/6G, and Wi-Fi 7/Wi-Fi 8, enabling devices from smartphones and AI PCs to automotive and data centers. Committed to a smarter, more connected world, MediaTek ensures access to world-class technology for all. Visit www.mediatek.com for more information.

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Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology

Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology
by Admin on 09-15-2025 at 10:00 am
Categories: 3D IC, Chiplet, Foundries, Intel Foundry

Intel Foundry Packaging Evolution 2025

In the rapidly evolving landscape of semiconductor manufacturing, the demand for processors that handle increasing workloads while maintaining power efficiency and compact form factors has never been higher. Intel’s Foveros 2.5D packaging technology emerges as a pivotal innovation, enabling denser die integration and enhanced functionality without substantially expanding the physical footprint of chip packages. Introduced in 2019, Foveros 2.5D represents an advanced die-stacking process that assembles multiple chiplets (small specialized silicon dies) into a cohesive unit. This approach addresses the limitations of traditional packaging by layering active dies, such as logic, memory, or FPGAs, atop a passive base die equipped with through-silicon vias (TSVs). The base die, often called a silicon interposer, facilitates seamless interconnectivity, marking a shift from monolithic chip designs to heterogeneous, modular systems.

At the core of Foveros 2.5D is its face-to-face chip-on-chip bonding mechanism, achieved through an ultra-fine microbump pitch of 36 micrometers. This precision bonding minimizes wire parasitics—undesirable electrical properties like resistance, capacitance, and inductance that degrade performance due to interconnect layouts. By reducing these parasitics, Foveros 2.5D ensures higher interconnect density, which is crucial for high-performance applications in data centers, AI accelerators, and edge computing. Furthermore, the technology allows designers to combine advanced process nodes for cutting-edge components with mature nodes for cost-effective, proven IP blocks. This hybrid strategy not only optimizes yields but also lowers manufacturing expenses, as smaller specialized dies on advanced nodes can be paired with reusable elements on established processes.

The benefits of Foveros 2.5D extend beyond density and cost. By stacking components vertically rather than spreading them horizontally, it significantly reduces signal travel distances, thereby lowering latency and boosting overall system performance. This vertical integration also enables more compact designs, ideal for space-constrained devices like mobile processors and embedded systems. When paired with Intel’s Embedded Multi-die Interconnect Bridge (EMIB), Foveros evolves into EMIB 3.5D, expanding reticle limits and supporting even more intricate multi-die configurations. This synergy allows for the connection of passive dies, further enhancing scalability for complex chip architectures.

Intel Foundry offers a versatile portfolio of Foveros 2.5D variants to cater to diverse needs. Foveros-S 2.5D employs a silicon interposer to position multiple chips side-by-side, delivering superior performance and power efficiency over conventional methods. In contrast, Foveros-R 2.5D prioritizes cost optimization and interconnect density by eliminating the interposer and utilizing fanout with up to three redistribution layers, enabling flexible heterogeneous systems. For applications requiring multiple base die chiplets, Foveros-B 2.5D integrates active and passive silicon bridges with RDLs, paving the way for future enhancements like cache disaggregation, integrated voltage regulators (IVRs), or metal-insulator-metal capacitors. All these configurations align with the Universal Chiplet Interconnect Express (UCIe) specification, an open industry standard that Intel helped pioneer. UCIe facilitates high-density integration of chiplets from various vendors, promoting interoperability, energy efficiency, and bandwidth gains through asynchronous and synchronous communication.

The evolution of Intel’s packaging technologies—from wire-bond and flip-chip methods to advanced solutions like Foveros—underscores a paradigm shift toward “systems of chips.” This disaggregated approach, championed by Intel Foundry’s Advanced System Assembly & Test, supports full-stack solutions that accelerate time-to-market for demanding use cases. With geographically diverse manufacturing capacity and ecosystem partners for system technology co-optimization, Intel is positioning itself as a leader in the transition from system-on-chip to multi-chiplet ecosystems.

Bottom line:  Foveros 2.5D exemplifies how innovative packaging can unlock new frontiers in semiconductor performance, efficiency, and scalability. By enabling heterogeneous chiplet integration, it not only meets current computational demands but also anticipates future challenges in AI and high-performance computing. As Intel continues to drive standards like UCIe, the technology promises to democratize advanced silicon design, fostering collaboration across the industry and ensuring that complex, power-efficient systems become the norm rather than the exception.

Foveros Technology Brief

EMIB Technology Brief

UCIe 3.0 Wiki

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EUV Lithography Without Pellicles: Accounting for Low Yields

EUV Lithography Without Pellicles: Accounting for Low Yields
by Fred Chen on 09-15-2025 at 6:00 am
Categories: Lithography

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While stochastic defects link yield with the practical resolution of EUV lithography resulting from its quantum nature [1], very low yields of EUV processes are more readily linked to the use of EUV masks without pellicles. Pellicles are thin film membrane covers on masks (regardless of wavelength: EUV and DUV and i-line) used to protect from particles landing on the patterns on the mask. Particles could land on the pellicle, but they would not print because they would be so out of focus. Without pellicles, yield can drop significantly just from having a few particles land on the mask [2].

Surprisingly, it has been reported recently that EUV users generally do not use pellicles [3,4]. The key reason is that pellicles can be damaged or even ruptured due to EUV light exposure [5]. TSMC also reported in 2023 that its EUV pellicle infrastructure was just completed, but still not yet in production [6]. They also noted that “with the increase in scanner power to 400W, a pellicle lifetime challenge has been observed” [6]. Moreover, it has been reported this year that TSMC was reluctant to use EUV pellicles since they need to be replaced every 3–4 days, at a high cost of over $10000 each [4].

Without the use of pellicles, it has been necessary to periodically check if particles had attached to the mask in the pattern area [7]. Note that increased inspection frequency means fewer output wafers per month. This leads to a tradeoff between inspection cost and yield risk (Figure 1).

Figure 1. A lower inspection frequency can keep costs low but increases the risk of letting a dirty mask print more wafers. The risk is reduced with increasing inspection frequency, which also increases costs.

The struggle for yield without pellicles is in line with continuing reports of yields less than 70% [8,9]. Nevertheless, even this year, Samsung reported ongoing concerns with EUV pellicle lifetimes, even with more promising candidate materials [10]. EUV users concerned about yield will need to continue to focus on particle contamination control.

Exposing EUV Site

References

[1] F. Chen, IMEC’s Advanced Node Yield Model Now Addresses EUV Stochastics; Facing the Quantum Nature of EUV Lithography.

[2] F. Chen, Explaining Pellicle-Free EUV Yield Loss.

[3] TheElec, FST in talks with Samsung to supply EUV pellicle, Sept. 3, 2025.

[4] Global Technology Research, Carbon Nanotube (CNT)- The Next Big Thing for EUV Pellicle?, Jan. 14, 2025.

[5] US Patent 10976674, assigned to TSMC.

[6] Y-Y. Lin et al., Proc. SPIE 12750, 127500N (2023).

[7] M. van de Kerkhof et al., Proc. SPIE 10957, 109570U (2019).

[8] TechPowerUp, Samsung’s Second-Gen 3 nm GAA Process Shows 20% Yields, Missing Production Goals, Nov. 11, 2024.

[9] TrendForce, [News] Intel 18A Yield Reportedly Just 10% at Risk Production, Casting Doubt on Panther Lake Plans, Aug. 6, 2025.

[10] M. J. Kim et al., Proc. SPIE 13424, 1342405 (2025).

Also Read:

TSMC Repurposing Old Fabs to Bring EUV Pellicle Production In-House

EUV Resist Degradation with Outgassing at Higher Doses

IMEC’s Advanced Node Yield Model Now Addresses EUV Stochastics

Edge Roughness Differences Among EUV Resists

Podcast EP307: An Overview of SkyWater Technology and its Goals with Ross Miller

Podcast EP307: An Overview of SkyWater Technology and its Goals with Ross Miller
by Daniel Nenni on 09-12-2025 at 10:00 am

Dan is joined by Ross Miller, senior vice president at SkyWater Technology. Ross leads the industrial and aerospace businesses while steering the company’s branding, and corporate communications efforts. He is a seasoned semiconductor and technology executive with over 20 years of experience across startup, enterprise, and government environments.

Dan explores the unique business model of SkyWater Technology with Ross, who explains that SkyWater is the only US-investor owned pure-play semiconductor and technology foundry. Ross describes the unique service model used by SkyWater and how the organization fits in the semiconductor ecosystem. He describes the recent IP licensing agreement with Infineon granting access to a robust library of silicon-proven, mixed-signal ASIC design IP and how that will enable innovation across the SkyWater customer base.

He also discusses the recent acquisition of Fab 25, expanding U.S. pure-play foundry capacity for critical semiconductor technologies. Ross points out that 90% of AMS designs are processed overseas and the vision of SkyWater is to re-shore these designs to enhance US technology independence.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Synopsys Announces Expanding AI Capabilities and EDA AI Leadership

Synopsys Announces Expanding AI Capabilities and EDA AI Leadership
by Daniel Nenni on 09-12-2025 at 6:00 am
Categories: 3D IC, AI, EDA, Synopsys

Synopsys.ai Copilot Customer Impact

In the fast-paced semiconductor industry Synopsys has redefined EDA with its Synopsys.ai Copilot, a generative AI tool. Since its launch in November 2023, and yes I was at the launch and very skeptical, Copilot has evolved to address the industry’s growing design complexity and projected 15-30% workforce gap by 2030. Let’s talk about its impact on productivity, its integration with Ansys, and its role in shaping the future of chip design.

The Synopsys.ai Copilot’s latest update introduces powerful assistive features, notably the Knowledge Assistant, now accessible to all Synopsys Cloud users in both SaaS and Bring Your Own Cloud environments. This tool slashes documentation search times from hours to minutes, enabling early career engineers to ramp up 30% faster while maintaining high-quality standards. To me this is critical as it can take months to ramp up new designers and from what I have heard the 30% faster number is conservative.

By leveraging 30 years of Synopsys design data, the Knowledge Assistant delivers context-aware guidance tailored to the engineer’s project and tools, such as Synopsys Fusion Compiler. Equally impactful is the Workflow Assistant, which accelerates script generation, achieving solutions up to 10X-20X faster when used with Synopsys PrimeTime for timing analysis. This reduces workflows from days to hours, helping engineers meet stringent performance, power, and area (PPA) targets efficiently.

The Copilot’s creative GenAI capabilities are equally groundbreaking. It now automates the generation of Register-Transfer Level (RTL) code, System Verilog Assertions (SVAs), and UVM testbenches from natural language inputs. Early adopters like Microsoft’s silicon team report over 80% syntax accuracy and 70% functional accuracy in automated formal verification workflows. This automation not only saves time but also enhances design reliability, allowing engineers to focus on innovation. The Copilot’s ability to generate tables, figures, and suggest fixes for issues like timing violations further streamlines complex system-on-chip (SoC) and multi-die designs.

Synopsys’ acquisition of Ansys has expanded the Copilot’s ecosystem to include the Ansys Engineering Copilot, enhancing productivity in simulation tools. Updates to Ansys SimAI, integrated with Ansys optiSLang, accelerate dataset creation and AI training, enabling faster exploration of design variations and shorter development cycles. This integration positions the Copilot as a holistic solution for both EDA and simulation-driven design, addressing the needs of diverse engineering teams.

Collaboration with Microsoft and NVIDIA underpins the Copilot’s scalability and performance. Built on Microsoft Azure’s high-performance computing infrastructure, it supports both on-premises and cloud deployments. Integration with NVIDIA AI Enterprise and platforms like NVIDIA DGX systems ensures robust performance for complex workloads, including air-gapped environments. These partnerships enable the Copilot to handle the computational demands of modern chip design, from SoC to multi-die systems.

Both Microsoft and Nvidia were on the “AI in EDA panel” I moderated at #62DAC. You can read more about it here: Insider Opinions on AI in EDA. The productivity numbers we are talking about are real, absolutely.

Copilot’s impact is evident across the industry. Early adopters, including AMD, Intel, and Microsoft, report a 35% productivity boost in formal verification workflows and up to 20X faster script generation. Over 100 startups using Synopsys Cloud SaaS leverage the Knowledge Assistant to accelerate time-to-tape-out, democratizing access to advanced EDA expertise. The introduction of AgentEngineer™, a prototype built on Microsoft Discovery, signals Synopsys’ vision for autonomous AI (Level 5), promising to re-engineer chip design workflows and further boost productivity.

Looking ahead, Synopsys plans to expand the Copilot’s capabilities with autonomous workflow creation and advanced 3D design optimization via 3DSO.ai. These advancements will enable engineers to explore larger design spaces and optimize for power, performance, and cost with greater precision. By addressing workforce shortages and design complexity, the Synopsys.ai Copilot is poised to lead the semiconductor industry into a new era of efficiency and innovation.

Bottom line: Synopsys is the EDA AI leader without a doubt. The Synopsys.ai Copilot’s 2025 update marks a milestone in EDA, combining assistive and creative GenAI to transform chip design. With its Ansys integration, industry partnerships, and measurable productivity gains, it empowers engineers to tackle complex challenges and drive technological advancement. For more details, visit www.synopsys.ai.

Also Read:

448G: Ready or not, here it comes!

Synopsys Webinar – Enabling Multi-Die Design with Intel

Synopsys FlexEDA: Revolutionizing Chip Design with Cloud and Pay-Per-Use