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May 4, 2020August 27, 2020

Linux for Medical Devices Q&A

As I have mentioned before SemiWiki gets to meet some very smart people and here is another one. Scot Morrison has an MS degree in Aerospace Engineering from MIT specializing in control systems. Today he is the general manager of the Embedded Platform Solutions Division at Mentor, a Siemens business. Scot oversees the Linux®, Nucleus®, and Mentor Embedded Hypervisor runtime product lines, as well as associated tools, middleware, and professional services.

Prior to joining Mentor in 2012, Scot served as GM and SVP of products at Wind River Systems, Inc. Before that he worked at Integrated Systems Inc., where he last served as the VP and GM of the design automation solutions business unit in 1999, responsible for MATRIXx, and the pOSEK embedded operating system.

In speaking with Scot, the top three points of interest/intrigue with Linux for medical devices is Safety, Security, and Size (of code) so keep that in mind as you continue reading:

Q: Can I use Linux in a medical device?
The answer to this question is, it depends. Linux has been deployed safely in a wide variety of medical devices, but in order to use Linux in a medical device that has a safety requirement you need to follow the process defined by the certification standard that you must comply with.

Q: We all know that safety and security are both necessary when we’re looking at medical devices. We hear that you can’t have safety without security, but why is that?
Security is something that can be looked at standalone; and even in medical devices, not all aspects of security are tied to safety. For example, when we talk about protecting people’s personal information, this is an aspect of security that does not overlap with safety. But, when we talk about safety, we talk about things that if they go wrong will impact the patient’s health. If the device is not secure, it makes it possible for bad actors to make these negative impacts happen either accidentally, or purposefully (which is much rarer).

Q. Does the use of Linux and other open source software help protect these devices?
Linux is the most heavily used operating system for devices in the world. It has a large, worldwide developer base that focuses on ensuring that it works as expected in all conditions, and is as secure as possible. That said, it is also the most studied operating system in the world, both by the vast majority of developers who are conscientiously working on improving Linux and other open source packages, and also by a small number of actors who are looking at ways to break into Linux for their own purposes. The security of applications using open source is a constant tug of war between these opposing forces. And as above, without security, you can’t have safety.

Q. How is it possible that Linux can have so many security flaws that we’re always finding more?
Linux (and other major open source packages like OpenSSL or SQLite) are large packages that have sometimes unpredictable interactions with other software that might be running in the system. This is combined with the fact that many flaws are hard to find in code reviews, normal testing, or by static analysis, and are undetectable unless software is combined with task switching and inter-process communication. Best practices will not identify every possible flaw or exploit, and much of the open source software that we rely upon was not originally developed with today’s best practices in place.

That said, the most important pieces of open source software used in devices world-wide are in a much more stable and secure place than they were 5 years ago, mainly due to the hard work and diligence of engineers all over the world in identifying avenues of exploitation, fixing those when they find them, and then the worldwide community looking for similar issues in their own projects. The work will never be complete, but it is becoming harder and harder to find exploitable flaws in this important infrastructure software.

Q. What happens when a security issue is found in Linux?
For the most part, security issues in Linux (and other important software like OpenSSL) are found by engineers either by happenstance (a bug that they uncover as part of their work), or through concerted efforts to find exploits (“white hat” hacking). Very occasionally, an exploit will be found as a result of a post-mortem analysis of an attack, but that is very uncommon. In either event, the discoverer of an exploit will notify the community of the offending open-source component, and in most cases, the discoverer or somebody in the community will notify the Common Vulnerability and Exposures (CVE) group, which is run by MITRE, and is closely related to US National Vulnerability Database (NVD), run by the National Institute of Standards and Technology (NIST).

Once a vulnerability is understood, and usually after a fix is available, the CVE is publicized by inclusion in these lists and if sufficiently serious, discussed by the security community worldwide. This is the point where devices are potentially most vulnerable; since most vulnerabilities are found by the “good guys”, the bad guys find out about them at the same time as the rest of the world, and can deploy exploitation that take advantage of the newly found vulnerability. That said, this publicity is very important, since it alerts the worldwide community of both the issue and the fix, so that an organization can determine if a particular exploit might affect their devices, and if it is, they can mitigate the issue before it may be attacked.

Of course, not everybody will be able to update their devices, which will leave them open to attacks, but since there are no real secrets in the world, this openness prevents more issues than it causes.

Q: Let’s bring it back to safety. Is Linux safe?
An operating system like Linux does not directly do anything to make a device safer. The Operating system doesn’t prevent a failure from occurring, nor does it make the system recover when a failure occurs; so in the terminology of safety an operating system is not a safety mechanism. This makes sense when you think about it. When you put Linux on a system with no other application and turn it on, Linux boots, but it just sits there at a login prompt; it’s not doing anything until applications run that leverage Linux, and it’s those applications that contribute to the overall safety of the device. When you think in those terms, while an operating system is not a safety mechanism, it does enable them; going back to the terminology of safety, the operating system is considered to be a safety element; something necessary but not sufficient to create a safety mechanism. So, the real question is “Can Linux be used as a safety mechanism?” The answer to that question is “Yes, but it’s complicated”.

Q. Why is it complicated?
To answer that, we need to look back 5 years or so. At that point, if Linux was used in a medical device, the architecture was designed to separate Linux from the safety critical part of the system to the greatest extent possible because it wasn’t trusted. The system would probably run Linux on a separate processor, and Linux would be responsible for activities that it was well suited for, like connectivity to the office or hospital network, running a display, taking user input, etc. Then, if information came in that would affect the safety function of the device (say, a dosage in an infusion pump), the new setting would be validated on another processor or in hardware before the change was administered to the patient. In many cases, these kinds of inputs that impact safety might not even come from Linux, but maybe from a dial or other hardware input. If an issue arose in Linux it would not impact the rest of the device, which would continue to execute safely.

Today, microprocessors are much more powerful and complex, with many cores, which are designed to support what we call heterogeneous multiprocessing; where there will be powerful general-purpose cores to support running an operating system like Linux, and then more specialized cores to handle other functions. Your cell phone probably has such a processor (or capabilities that provide for separation); the powerful processor is running Android or iOS and your apps, while something separate is managing your secure data. Safe devices today are taking advantage of this trend; the microprocessors are much cheaper than the multiple ones you might use in the past, and much more powerful. But, it means that there are more considerations to think about when you use them.

Q. How does a multiprocessor system affect safety?
Designing for safety is no longer just a hardware or software issue, it’s an integrated systems issue. To take full advantage of the lower board BOM costs and higher integration of components in an advanced multiprocessor chip for a safety sensitive design, applications must be kept separated – what’s known as mixed-safety criticality.

For example, you can now run the user interface portion of your system on a processor cluster that’s optimized for user applications with features like multi-level cache, and power islands for shutting off individual processors and memory, thus conserving power, say in a battery-operated medical device. Linux can also make optimal use of the application processor cluster with built-in features like Symmetric Multi-Processing, parsing tasks and threads to individual processors. Simultaneously, the safety critical portion of the system runs on a separate cluster that is dedicated to real-time processing with features like tightly-coupled data and instruction memory with extremely low fetch cycles, and highly deterministic performance; or lockstep mode to for error detection.

Advanced multiprocessing systems contain hardware-enforced isolation that keeps the application world and the safety-critical world separated, but the software designer will need to use middleware such as the Mentor Hypervisor or Mentor Multicore Framework to take advantage of those hardware features. These software packages make important system-level functions like secure Inter-processor Communication (IPC) between the processor clusters possible.

Q. Are there other hardware considerations Linux can take advantage of?
Definitely. One example is an advanced option in the Linux kernel known as the Power Framework. The software application can utilize the kernel to power down portions of the system when they’re not needed, and power them up when required, conserving system power. Advanced SoCs include peripheral interfaces in the processor clusters like I2C or USB that can be controlled in this manner, but that advantage can also be extended to implementing “soft” peripherals external to the processing cluster in RTL logic, for example a CAN interface; and even peripherals outside the chip, like an Ethernet PHY.

Taking full advantage of modern embedded systems means designing hardware with awareness of what the software is capable of; while at the same time, writing accompanying software drivers, firmware, and applications that can utilize all the features of the hardware.

Q. And I can get this advanced middleware and drivers from the silicon vendors?
The silicon vendors are primarily focused on what they do best, providing the best chips available to the market. All embedded silicon vendors provide some level of software support, but typically this is limited to bare-metal drivers, open-source builds of Linux, and some limited middleware. For advanced features like enabling mixed-safety criticality medical systems, the best option for the designer is to utilize a software vendor like Mentor that specializes in enabling multi-core applications. Thus your designers can focus on your own IP, and not having to code and debug the middleware.

Q. So, can Linux be pre-certified for use in a device?
Not really. Certain real-time operating systems (RTOSs) such as the Nucleus RTOS from Mentor, can be acquired pre-certified, as can other embedded software components from a number of vendors. To achieve this kind of pre-certification the vendor must be able to show that the complete software development process (requirements, design, development, testing and verification and all of the steps of development) have been performed to medical industry standards such as ISO 13485 and/or IEC 62304. Linux and other open source components are not developed to these standards, and thus cannot be pre-certified. As a note, there have been efforts to show conformance of Linux to the over-arching concepts of functional safety (usually mapping to IEC 61508, from which many industry standards are derived, including IEC 62304). While these have not been successful so far, the current effort (project ELISA) is showing promise in this area both in improving the processes used in open-source software development, and in mapping the higher-quality output to these standards. However, this promise is likely years away from being completely realized.

Instead of pre-certification, in medical devices, Linux is generally handled using a concept from IEC 62304 called Software of Unknown Providence, or SOUP. Under these guidelines the use of Linux is considered as part of the risk assessment of the overall device, and potential failures of Linux as used in the device must be considered, and mitigated if they might cause harm to a patient.

This risk assessment must meet the requirements of the FDA’s pre and post submission guidance, so on the front end it requires considerations on the use of Linux in the design, implementation, testing and verification of the device, and then after release, the use of Linux (and all open-source software) must consider the possibility that issues will be found after release. Certifiers are taking a very close look at this aspect of open-source, especially as far as security issues (i.e. CVEs) are concerned.

Q. How does using a commercial Linux provider help?
If you use open-source in your device, you are responsible for acquiring it, and maintaining it in your device both during development and after release. Acquiring Linux (and other open-source modules that you are likely to use) is easy; it often is available from your board or microprocessor vendor targeted to your development board. However, this Linux is usually made available on an as-is basis and is meant to get a system up and running; your board vendor will not be performing maintenance or timely updates of that Linux for you to use after release. As a result, this responsibility falls onto the device developer to manage, for the life-time of the device. This is not impossible, but by doing it yourself you are committing engineering resources to monitor and maintain the significant number of CVEs that are reported against open source components every day… As an example, in 2019 there were 170 CVEs issued just against the Linux kernel and 12,174 CVEs created in total. It is a significant effort to review each of these, determine which are important, round up the fixes, and verify that the operating system is still operating as you would expect. A commercial Linux provider does this work as part of their core competency, and while they will charge you for this kind of service, it will cost you less in the long run and you’ll end up with a higher-quality product with fewer integration issues as you maintain the product over its lifetime.

For additional information please check the Mentor Embedded Software and Medical Devices landing pages.

May 3, 2020July 6, 2020

Is Chip Embargo aimed at China, Huawei, TSMC or all three?

Is Chip Embargo aimed at China, Huawei, TSMC or all three?
by Robert Maire on 05-03-2020 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

Is TSMC the real target, not just collateral damage?
Is equipment embargo threat to bring TSMC to heel?
Is an embargo a “Trifecta” of US strategic goals?

Maybe TSMC is a real target of chip equipment embargo not just potential collateral damage
It occurs to us when we talk about TSMC being caught in the middle between the US and China and being “collateral damage” in the crossfire of an embargo and trade war that maybe the US is really targeting TSMC, along with China and Huawei, and really killing three birds with one embargo stone.

Think about TSMC from a US perspective…..they have blown past beloved Intel in terms of technology dominance and clearly enabling AMD and others. They are building chips for the US’s enemies both military and commercial. They have in essence put US foundries out of business, GloFo, Intel’s foundry effort among others, and forced the US to buy all advanced chips from them with no alternate. They are getting a “bear hug” from their bigger nearby neighbor who covets them and could crush the US technologically by taking them over. And last, but not least, TSMC has refused US efforts to get them to either put a fab in the US or help with one such that the US chip supply would be protected from a hostile takeover.

Maybe if I were in power in the US government I would want to something over TSMC to bring them to heel and get them to cooperate or see things my way. Maybe I could cut off, or threaten to cut off, their “oxygen supply” of US made or controlled semiconductor equipment which could effectively put them out of business or cripple them.

The hand of the US government continues to get closer and closer to that “oxygen valve” that controls the flow of equipment. The ratcheting up of pressure and implied threat is crystal clear.

We would not be surprised to see some capitulation on the part of TSMC by preemptively agreeing to some sort of licensing arrangement that gives the US more control over their customers. We would also not be surprised to see some sort of US based foundry effort that TSMC could be part of. Maybe joint with Intel. Buy out GloFo’s fab and refit it or maybe a greenfield somewhere that gains political points.

Intel will not shed a lot of tears over TSMC getting bullied and could stand to benefit. TSMC could play it publicly as a win for them with some sort of concession to build a fab in the US. The US could say that jobs and leadership are being brought back to the US.

China’s Chip aspirations
Obviously one of the larger targets of a US chip equipment embargo would be to stave off the “made in China 2025” plans that China is focused on. Right now China is not self reliant on Chip manufacture let alone equipment to make chips.

Sooner or later China will catch up and get more and more chip technology but the strategic game plan is to delay, slow down and make as difficult as possible that goal. The longer we can keep them behind, the better for the US.
We have already seen the risk associated with China making 90% of US pharmaceuticals and probably 90% of PPE etc;. Obviously not only the US’s health is at stake but our military & intelligence superiority which is based in very large part on our advanced technology.

Cutting off Huawei and 5G
Huawei, which not that long ago was a tiny “copycat” of US router innovator , Cisco, is now threatening to dominate 5G and along with it a significant part of technology infrastructure. Obviously cutting off their supply of advanced chips would kill or effectively kill their 5G program which in turn would keep the US effectively in charge of the 5G rollout.

Neither Apple nor Cisco would shed tears. We know that Tim Cook has been close to the current US administration much as Intel’s prior management was also very close and probably whispers in high ranking ears about the threat of China, Huawei and 5G to not only US defense interests but commercial interests which translates to the all important stock market and US jobs.

The perfecta embargo “Trifecta”
All this suggests that embargoing or at the very least threatening to embargo US made and controlled semiconductor equipment gets 3 big goals; 1) slows China access to chip dominance 2) slows or stops China’s 5G plans 3) gets TSMC to “align” with US interests. Maybe not in that order of importance.

Three big birds on one stone? Is the US government really that smart? or that devious? We”ll find out……..

The stocks
Obviously TSMC’s stock is just as vulnerable as US semiconductor equipment makers. Maybe I want to be long non-US equipment makers such as Advantest, Tokyo Electron,ASMI, BESI and others and perhaps neutral to short US equipment makers and TSMC (for now).

Investors seem pre-occupied with the Covid crisis and are finally starting to realize the long term implications of Covid economic impact will in fact actually impact beloved tech stocks, perhaps as much if not more than the broader market.

Ugliness and excess risk abounds…

May 3, 2020August 2, 2020

Covid Created Collateral China Crisis

Covid Created Collateral China Crisis
by Robert Maire on 05-03-2020 at 6:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services
7 Comments

Economic damage-
China relationship damage will far outlast direct Covid19 logistics impact-
Economic damage could be huge but trade damage could be larger with more specific impact on chips-

A long build up to a China trade nuclear winter, the “drum-beat of war”
When we started talking about a potential chip trade embargo with China 3 years ago we were roundly criticized and laughed at….not so any more as the specter of a full blown, tech led, trade war with China seems to get larger by the day.

Several months ago the heat got turned up again. On Monday the Commerce department issued three new rules that will effectively pave the way for technology exports to China and exports to companies doing business with China (read that as TSMC) to be more easily restricted.

Elimination of License Exception
Expansion of controls for Military Use
Modification of License Exception

This feels an awful lot like tanks are massing on the border and warships are moving into position. The direction and intention of moves made over the last several months are very, very clear. It seems with all this planning and build up that implementation is all but inevitable.

Can’t go after Covid so lets go after China
The administration seems to have lost the PR war and momentum of “rally around the flag” associated with Covid as approval ratings are dropping.
The media seems to be increasingly full of news that appears to be “redirecting” anguish and angst about Covid at China and their role (whether rightly or wrongly and as yet unproven…). Taking “revenge” on China for Covid through technology export restrictions restrictions seems like a logical, calculated response that may help sagging approval ratings with another “rally around the flag” associated with a conflict with China.

Chip companies votes don’t matter
As we have previously pointed out in several prior notes the political consequences of starting a trade war with China that primarily impacts tech companies (located in the “blue” state of California) doesn’t really matter. This is similar to stopping ASML’s export of an EUV scanner as Dutch residents don’t vote in US elections.

Starting a trade conflict with China as payback for Covid may get a lot of core support as well as support in swing states among the unemployed.

Locked and Loaded
The recently announced rule changes coupled with the current political and media under currents make it clear that we are ready to pull the trigger on the first shot in a trade war at any time as there is little more preparation to be done….all we need is some triggering event…..

Bracing for the impact
Lam updated its risk factors toady with a filing that said that China was 22% of 2019 and 29% of 9 months of 2020 and that all bets are off with respect to obtaining export licenses. Obviously Applied Materials and KLA as well as ASML and many others are just as impacted if not more.

Of course the biggest and most impactful company caught in the crossfire is TSMC with roughly 15% of revenues going to Huawei alone at risk and a lot more going directly or indirectly to China. TSMC would be major “collateral” damage in a trade war with China as would the US’s exports to TSMC.

We keep reminding readers that Taiwan is a short boat ride from mainland China which views Taiwan the same as Hong Kong just not yet brought back into the fold (by any means necessary)

Would a China trade war be limited to chips and tech ???
It is unclear whether China and the US would keep trade war limited to chips and tech. Could the entire trade deal recently concluded become at risk of falling apart before it ever started? Could US farmers and other industries become embroiled?

Maybe redirecting people’s attention away from Covid to a trade war with China would be viewed as a positive, after all, trade with China as well as a Southern wall were part of the reason the current administration is there in the first place.

Support for doing something against China is likely coming from both sides of the aisle and could prove a popular, uniting idea.

The real problem is limiting the fall out when the economy is already in a tail spin. Throwing fuel on an already raging economic bonfire by limiting exports is very tricky. Limiting it to tech or specifically chips, makes it much more palatable.

The stocks
Our position remains the same. The near term Covid impact is largely logistic by nature and will pass over time (though with a lot of pain and suffering…) but the longer term, economic impact is yet to be seen and much longer lived. If we add to that long term Covid economic impact the risk of a trade war with China revolving around chips and tech it makes the chip and tech stocks very unattractive at almost any valuation due to risk.

We have seen a short term pop in stock prices as the near term Covid impact has been lighter than most expected but the market seems to have not discounted the longer term impact nor much impact from the China trade risk.
While the values of the stocks on a purely numerical basis may look good right now, the risks are anything but.

We would prefer to keep our money on the side or in more defensive names.
The actual announcement of a chip/tech trade war could cut the value of the impacted stocks a lot more than Covid and a lot more quickly which is a risk that’s hard to tolerate especially now.

Semiconductor Advisors

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May 1, 2020July 6, 2020

TSMC’s Advanced IC Packaging Solutions

TSMC’s Advanced IC Packaging Solutions
by Herb Reiter on 05-01-2020 at 10:00 am
Categories: Foundries, TSMC
8 Comments

TSMC as Pure Play Wafer Foundry
TSMC started its wafer foundry business more than 30 years ago. Visionary management and creative engineering teams developed leading-edge process technologies and their reputation as trusted source for high-volume production. TSMC also recognized very early the importance of building an ecosystem – to complement the company’s own strengths. Their Open Innovation Platform (OIP) attracted many EDA and IP partners to contribute to TSMC’s success, all following Moore’s Law, to 3 nm at this time, to serve very high-volume applications.

Markets need Advanced IC Packaging technologies
For many other applications Moore’s Law is no longer cost-effective, especially not for integration of heterogeneous functions. “Moore than Moore” technologies, like Multi-chip modules (MCMs) and System in Package (SiP) have become alternatives for integrating large amounts of logic and memory, analog, MEMS, etc. into (sub)system solutions. However, these methodologies were and still are very customer specific and incur significant development time and cost.

In response to market needs for new multi-die IC packaging solutions, TSMC has developed, in cooperation with OIP partners, advanced IC packaging technologies to offer economical solutions for More than Moore integration.

TSMC as supplier of Advanced IC Packaging solutions
In 2012 TSMC introduced, together with Xilinx, the by far largest FPGA available at that time, comprised of four identical 28 nm FPGA slices, mounted side-by-side, on a silicon interposer. They also developed through-silicon-vias (TSVs), micro-bumps and re-distribution-layers (RDLs) to interconnect these building blocks. Based on its construction, TSMC named this IC packaging solution Chip-on-Wafer-on-Substrate (CoWoS). This building blocks-based and EDA-supported packaging technology has become the de-facto industry standard for high-performance and high-power designs. Interposers, up to three stepper fields large, allow combining multiple die, die-stacks and passives, side by side, interconnected with sub-micron RDLs. Most common applications today are combinations of a CPU/GPU/TPU with one or more high bandwidth memories (HBMs).

In 2017 TSMC announced the Integrated FanOut technology (InFO). It uses, instead of the silicon interposer in CoWoS, a polyamide film, reducing unit cost and package height, both important success criteria for mobile applications. TSMC has already shipped tens of millions of InFO designs for use in smartphones.

In 2019 TSMC introduced the System on Integrated Chip (SoIC) technology. Using front-end (wafer-fab) equipment, TSMC can align very accurately, then compression-bond designs with many narrowly pitched copper pads, to further minimize form-factor, interconnect capacitance and power.

Figure 1 shows that CoWoS technology is targeting Cloud, AI, Networking, Datacenters and other high-performance and high-power computing applications.

InFO serves some of these and a broad range of other, typically more cost-sensitive and lower power markets.

SoIC technology offers multi-die building blocks for integration in CoWoS and/or InFO designs. – see Figure 2.

SoIC technology benefits
TSMC’s latest innovation, the SoIC technology is a very powerful way for stacking multiple dice into a “3D building block” (a.k.a. “3D-Chiplet”). Today SoICs enable about 10,000 interconnects per mm2 between vertically stacked dice. Development efforts towards 1 Million interconnects per mm2 are ongoing. 3D-IC enthusiasts, including myself, have been looking, for an IC packaging methodology that enables such fine-grain interconnects, further reduces form-factor, eliminates bandwidth limitations, simplifies heat management in die stacks and makes integrating large, highly parallel systems into an IC package practical. As its name – System on IC – suggests, this technology meets these challenging requirements. The impressive capabilities of SoIC and SoIC+ are further explained here. TSMC’s EDA partners are working on complementing this technology with user-friendly design methodologies. I expect IP partners to offer soon SoIC ready chiplets and simulation models for user-friendly integration into CoWoS and InFO designs.

Personal comment: More than 20 years ago, in my alliance management role at Synopsys, I had the opportunity to contribute to Dr. Cliff Hou’s pioneering development work on TSMC’s initial process design kits (PDKs) and reference design flows, to facilitate the transition from the traditional IDM to the much more economical fabless IC vendor business model.

With the above described packaging technologies, TSMC is pioneering another change to the semiconductor business. CoWoS, InFO and especially SoIC enable semiconductor and system vendors to migrate from today’s lower complexity (and lower value) component-level ICs, to very high complexity and high value system-level solutions in IC packages. Last, but not least, these three advanced IC packaging solutions are accelerating an important industry trend: A big portion of the IC and system value creation is shifting from the die to the package.

May 1, 2020January 11, 2022

Lithography Resolution Limits: Line End Gaps

Lithography Resolution Limits: Line End Gaps
by Fred Chen on 05-01-2020 at 6:00 am
Categories: Lithography
1 Comment

In a previous article [1], the Rayleigh criterion was mentioned as the resolution limit for the distance between two features. On the other hand, in a following article [2], the minimum pitch was mentioned for the resolution limit for arrayed features. In this article, we reconcile the two by considering gaps between arrayed features, for example, between a minimum pitch line end and the edge of a perpendicular line.

Counting Spatial Harmonics (Diffraction Orders)

The number of features that can fit into the pitch equals the number of spatial harmonic intervals (=wavelength/pitch) that are passed by the numerical aperture (NA) of the optical system. If 5 spatial harmonics, or diffraction orders beyond the zeroth, are passed, then five intensity peaks emerge, indicating a minimum feature size of one-fifth the pitch (Figure 1).

Figure 1. The fundamental (1st harmonic) only generates one feature per pitch, while the fifth harmonic generates five.

With a minimum pitch of wavelength/NA in the horizontal direction, and a wider pitch in the vertical direction, the number of features spaced vertically within the vertical pitch at most will be the number of diffraction orders in the vertical direction (besides the zeroth), and this will depend on the illumination. The minimum pitch dictates an optimum illumination (e.g., dipole or quadrupole) which will limit the number of diffraction orders to two in the horizontal direction and a given number in the vertical direction. By dividing the vertical pitch by the number of diffraction order intervals, the minimum gap in the vertically running line can be estimated (Figure 2).

Figure 2. Left: The optimum illumination for a given pitch between vertical lines will arrange to have the diffraction orders at equal horizontal distances from the center, while allowing a number to spread out vertically. The circle represents the numerical aperture which will cut off diffraction orders which fall outside. Center: Top view of aerial image of a rectangle between horizontal lines. The cut line aerial image (right) from the center cutline shows the gap where intensity drops is roughly 1/5 the vertical pitch, as expected from the number of included diffraction order intervals.

This is calculated for a range of minimum pitches and cross-pitches and plotted in Figure 3.

Figure 3. Left: Tip-to-edge gap for a line pitch of wavelength/NA, as a function of cross-pitch, normalized to wavelength/NA. Right: Tip-to-edge gap for a cross-pitch of 4 x line pitch, as a function of line pitch, normalized to wavelength/NA. The illumination is optimized for the line pitch.

In fact, the lower limit of gap size can be calculated exactly if the minimum line pitch is at most wavelength/NA. It is sqrt(3)/3 * wavelength/NA. The proof is given in the Appendix.

Sanity Check: consistency with the Rayleigh Criterion

The Rayleigh criterion and the arrayed feature results are both derived from Fourier transforms truncated by the numerical aperture. The Airy disc underlying the Rayleigh criterion comes from the Fourier transform of a circular aperture while the Fourier transform of an array produces a Fourier series convolved with the apertures within a pitch. Hence, there should be no conflict between the above and previous [2] arrayed feature results and the Rayleigh criterion.

Shrinking the gap below k1=0.6

An interesting effect is predicted when the gap is smaller than 0.6 wavelength/NA. It appears as if less light is absorbed or transmitted (reflected for EUV case) by the shrinking feature. This can lead to resist scumming for example [4]. This can be understood by considering the amplitudes of the harmonics (Figure 4).

Figure 4. The amplitudes of the spatial harmonics (diffraction orders) which are not cut off by the numerical aperture all decrease when the gap size falls below 0.6 wavelength/NA (k1=0.6), but above this size, the higher harmonics decrease while the lower ones increase.

For features below 0.5-0.6 wavelength/NA, the amplitudes of all the harmonics decrease with decreasing size. However, for features sized 0.6 wavelength/NA and higher, the higher harmonic amplitudes decrease as size is increased while the lower harmonics have the opposite trend, indicating a trend toward sharper edges [5]. Below 0.6 wavelength/NA, gaps in lines are better patterned by a separate cut mask exposure [6]. This allows the smaller line end gaps to be compensated with a higher dose.

The gap between line end and perpendicular line edge can also be reduced below ~0.6 wavelength/NA by spacer patterning within an initially wider starting gap (Figure 5). This approach is also known as spacer-is-dielectric self-aligned double patterning (SID SADP) [7].

Figure 5. SID SADP approach to reducing gap width.

Summary of Lithography Resolution Limits

The lithography resolution limits are now summarized as follows:

Gap between isolated pairs: 0.61 wavelength/NA

Minimum pitch of arrayed features: 0.5 wavelength/NA/(1-angle tolerance)

Line end gaps for line pitch<=wavelength/NA: 0.58 wavelength/NA

Appendix: Derivation of lower limit of arrayed gap size for minimum line pitch of wavelength/NA or less

The starting point here is that for a minimum pitch p <= wavelength/NA (dense line k1<=0.5), the illumination will first produce the diffraction order distribution shown on the left in Figure 2. In terms of spatial frequency coordinates, this means the x-coordinates are +/- 0.5 wavelength/p. Here we express the y-pitch as a multiple of the minimum pitch, i.e., np. The diffraction order interval is therefore wavelength/p/n. The number of such intervals which fit within the numerical aperture NA is therefore given by

N=2 * sqrt(NA^2-(0.5 wavelength/p)^2)/(wavelength/p/n)

= 2 n sqrt((p*NA/wavelength)^2-1/4). (1)

The estimated gap size is therefore

gap size = np/N = n p/ [2 n sqrt((p*NA/wavelength)^2-1/4)]

= p/sqrt[(2 NA p/wavelength)^2-1]. (2)

Since p lies within the range 0.5-1 wavelength/NA, the minimum gap size occurs for p = wavelength/NA, giving a gap size of 1/sqrt(3) wavelength/NA = sqrt(3)/3 wavelength/NA ~ 0.58 wavelength/NA (Figure 6). Note that this is larger than the nominal line spacing (k1<=0.5). So, for connections to the next layer that must not exceed k1=0.5, the gap must be printed with a cut mask.

Figure 6. Gap size vs. line pitch, where both are normalized to wavelength/NA (k1=dimension/(wavelength/NA)).

References

[1] https://www.linkedin.com/pulse/lithography-resolution-limits-paired-features-frederick-chen/

[2] https://www.linkedin.com/pulse/lithography-resolution-limits-arrayed-features-frederick-chen/

[3] https://en.wikipedia.org/wiki/Fourier_optics

[4] D. Chou, K. McAllister, “Line end optimization through optical proximity correction (OPC): a case study,” Proc. SPIE 6154, 61543A (2006).

[5] https://user.eng.umd.edu/~tretter/enee322/FourierSeries.pdf

[6] Z. Li et al., “The study of 28nm node poly double patterning integrated process,” CSTIC 2015.

[7] Y. Du et al., “Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification,” Proc. SPIE 8684, 86840D (2013).

Slash Tapeout Times with Calibre in the Cloud

Slash Tapeout Times with Calibre in the Cloud
by Mike Gianfagna on 04-30-2020 at 10:00 am
Categories: EDA, Siemens EDA

I’ve spent many years in the ASIC business, and I’ve seen my share of complex chip tapeouts. All of these projects share one important challenge – compute requirements explode when you get close to the finish line. Certain tools need to run on the full-chip layout for final verification and the run times for those tools can get excessively long. The story is probably quite familiar to many. There is a fixed compute capacity available in any on-premise datacenter. That capacity is designed to handle typical workloads for the company and most of the time that works OK.

Near tapeout, run times for some key tools start to explode however, thanks to the massive amount of data to be processed for the final full-chip runs. Adding more processors and memory helps a lot. Going from 2,000 to 8,000 cores for example. But who has 6,000 cores sitting idle when the whole compute farm is provisioned at around 2,000 cores? You get the picture.

Mentor’s Calibre DRC is one such tool that is a key part of the full-chip tapeout process. That’s why a recent white paper from Mentor entitled “Mentor, AMD and Microsoft Collaborate on EDA in the Cloud” caught my attention. This white paper presents a thoughtful and complete analysis of how to tame the peak load demand problem using cloud computing to access essentially unlimited compute power when needed.

The white paper is written by Omar El-Sewefy, a technical lead at Mentor who has been working on their advanced products for almost 12 years. Omar presents a thoughtful analysis of how to reduce long run times by exploiting the cloud-ready capabilities of Caibre’s physical verification technology. The analysis is a collaboration with AMD for processing power and Microsoft Azure for cloud infrastructure, so the results are based on mainstream, “available now” technology. The punch line is that a speed-up of 2X or more in physical verification cycle time can be achieved on a 7nm design.

While that’s an eye-catching statistic, the piece offers a lot more insight into how to achieve that improvement and how to even exceed it. A key part of the analysis is finding the right mix of compute resources for optimal, cost-effective improvement. More isn’t always better, and when you’re using the essentially infinite resources offered by the cloud knowing what to ask for is very important.

The best practices for using Calibre in the cloud presented in the white paper were done using AMD EPYC™ servers running on the Azure cloud service environment. The latest foundry-qualified rule deck was also used to ensure the latest technology was applied. I mentioned Calibre’s cloud-readiness. Mentor has been steadily improving Calibre’s processing and memory efficiency to facilitate better results in the cloud. The figure below illustrates normalized memory improvements on the left and normalized run time improvements on the right for Calibre releases over the past year.

The analysis presented in the white paper used various configurations of AMD’s EPYC 7551 processors running in the Azure cloud. The 2019.2 release of Calibre was used, with Calibre nmDRC™ providing hyper-remote distributed computing capability up to 4,000 cores. The results in the white paper focus on the optimal balance of processing power and memory to deploy for the case used. This is quite important. The resources offered by the cloud are essentially unlimited. This means the user must be thoughtful about what resources are used or project budgets can go out of control.

The white paper provides a lot of good details about how to achieve this balance and I highly recommend you download it to see the details for yourself. To whet your appetite, here are a few key observations:

Regarding the number of cores, it turns out there is a “knee” in the scaling curve where the “best value for money” is achieved. For the design and node that was run, the knee was reached between 1,500 and 2,000 cores
Regarding memory usage, RAM requirements per remote core are reduced by increasing the total number of remote cores, which aligns with the overall scaling strategy

To put all this in perspective, the original run time for this case could be 24 hours using a typical on-premise datacenter. By increasing cores to 2,000 in the cloud, the run time can be reduced to 12 hours, allowing twice as many runs per day. I mentioned that the Calibre 2019.2 release was used for these experiments. What if the latest release was used? That experiment yielded an addition 3-hour reduction with 2,000 cores. More improvements are possible by increasing the cores to 4,000 of course. That becomes a cost/benefit decision, one that is only possible when you are using the cloud. You can download the whole story here.

April 30, 2020May 6, 2020

Radiation Tolerance. Not Just for ISO 26262

Radiation Tolerance. Not Just for ISO 26262
by Bernard Murphy on 04-30-2020 at 6:00 am
Categories: Automotive, EDA, FPGA, Siemens EDA

Years before ISO 26262 (the auto safety standard) existed, a few electronics engineers had to worry about radiation hardening, but not for cars. Their concerns were the same we have today – radiation-induced single event effects (SEE) and single event upsets (SEU). SEEs are root-cause effects – some form of radiation, might be cosmic, might be generated on earth, smacks into a chip die causing an ionization cascade. That may lead to a single event upset (SEU) where a bit in the logic is flipped. SEEs can also trigger latchup, gate rupture and other damage. But most efforts on rad hardening today, that I know of, focus on SEUs.

Two factors amplify the importance of SEUs – radiation flux intensity and the sensitivity of the circuit. Radiation flux at ground level, mostly neutrons triggered by cosmic ray events in the upper atmosphere, wasn’t energetic enough in most applications to be an issue until we got to smaller fabrication geometries where a bit can be flipped by a single ionization event.

Obviously above the atmosphere and higher in the atmosphere, cosmic ray energy and flux is less moderated by traveling through miles of air, which means that satellites and aircraft need a higher level of hardening. Also on the ground, some applications such as the European ITER fusion reactor need to use specially hardened FPGAs. The same applies to instrumentation around nuclear reactors.

Mentor recently released a white paper, “RETHINKING YOUR APPROACH TO RADIATION MITIGATION”, talking about a general methodology towards handling this need, particularly directed to the FPGA design so common in these aerospace and nuclear applications. Interestingly this paper doesn’t push any tools or even classes of tools. It’s one of those happiest finds among vendor white papers – a commercial-free information resource!

The paper starts with a common FPGA development flow for high radiation environments. This should look familiar to ISO 26262 aficionados, with a parallel flow for FMEDA, fault analysis, fault protection and fault verification. I’m thinking we may already be used to a decent level of automation in this flow in the automotive domain. There seems to less of this in aerospace and nuclear or perhaps less for FPGA design in general; maybe since FPGA design methodologies often follow behind those for mainstream SoC design?

Whatever the reason, it looks like designers in these domains depend mostly on expert-driven and largely manual fault analysis. The theme of the paper is to argue the benefits of moving towards a more automated, exhaustive (to some level) and scalable approach which will work not only with in-house designed logic but also with embedded 3^rd-party IP.

The paper walks in some detail through the challenges in conventional approaches to fault analysis, through metrics for fault coverage and FIT, and the structural analysis that must be performed to assess these metrics, from low-level logic up to a full design. It also talks about common fault mitigation approaches, parity, CRC, ECC, TMR, duplication and lockstep checking, you know the list.

The next topic is fault protection, with a nod to fail-operational behavior (also becoming more common in ISO 26262). The main emphasis here is on the error-prone nature of manually inserting mitigation techniques and the challenge in re-verifying those changes did not break mission-mode functionality. This implies a need for more automated equivalence checking.

The final section is on fault verification and the challenges in intelligently faulting a sufficient set of nodes to ensure a high level of coverage while keeping that set to a manageable level (since fault simulation is going to burn a lot of compute cycles).

An interesting insight into the needs of the aerospace and nuclear electronics design communities, who should definitely find it a good backgrounder. You can read the paper HERE.

April 29, 2020September 1, 2024

Can TSMC Maintain Their Process Technology Lead

Can TSMC Maintain Their Process Technology Lead
by Scotten Jones on 04-29-2020 at 10:00 am
Categories: Foundries, Intel Foundry, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
10 Comments

TSMC Process Lead Slides 20200427 Page 1

Recently Seeking Alpha published an article “Taiwan Semiconductor Manufacturing Company Losing Its Process Leadership To Intel” and Dan Nenni (SemiWiki founder) asked me to take a look at the article and do my own analysis. This is a subject I have followed and published on for many years.

Before I dig into specific process density comparisons between companies, I wanted to clear up some misunderstandings about Gate All Around (GAA) and Complimentary FET (CFET) in the Seeking Alpha article.

Gate All Around (GAA)
Just as the industry switched from planar transistors to FinFETs, it has been known for some time that a transition from FinFETs to something else will eventually be required to enable continued shrinks. A FinFET has a gate on three sides providing improved electrostatic control of the devices channel compared to a planar transistor that has a gate on only one side. Improved electrostatic control provides lower channel leakage and enables shorter gate lengths. FinFETs also provide a 3D transistor structure with more effective channel width per unit area than planar transistors therefore providing better drive current per unit area.

It is well established that a type of GAA device – horizontal nanosheets (HNS) are the next step after FinFETs. If the nanosheets are very narrow you get nanowires and significantly improved electrostatics. The approximate limit of gate length for a FinFET is 16nm and for a horizontal nano wire (HNW) is 13nm, see figure 1. Shorter gate lengths are a component of shrinking Contacted Poly Pitch (CPP) and driving greater density.

Figure 1. Contacted Poly Pitch CPP Scaling Challenges.

Please note that in Figure 1, the 3.5nm TSMC HNW is just an example of how dimensions might stack up, we know they are doing FinFETs at 3nm.

The problem with a HNW is that the effective channel width is lower than it is for a FinFET in the same area. The development of HNS overcame this problem and can offer up to 1.26x the drive current of FinFETs in the same area although they sacrifice some electrostatic control to do it, see figure 2.

Figure 2. Logic Gate All Around (GAA).

Another advantage of HNS is the process is essentially a FinFET process with a few changes. This is not meant to understate the difficulty of the transition, the HNS specific steps are critical steps and the geometry of a HNS will make creating multiple threshold voltages difficult, but it is a logical evolution of FinFET technology. Designers are used to FinFETs with 4 and 5 threshold voltages available to maximize the power – performance trade off, going back to one or two threshold voltages would be a problem, this is still an area of intense HNS development and needs to be solved for wide adoption.

At the “3nm” node Samsung has announced a GAA HNS they call a Multibridge, TSMC on the other hand is continuing with FinFETs. Both technologies are viable options at 3nm and the real question should be who delivers the better process.

Complementary FETs (CFET)
In the Seeking Alpha article there is a comment about a CFET offering 6x the density of a 3 fin FinFET cell, that isn’t how it works and in fact the comparison doesn’t even make sense.

Logic designs are made up of standard cells, the height of a standard cell is given by metal 2 pitch (M2P) multiplied by the number of tracks. A recent trend is Design Technology Co Optimization (DTCO) were in order to maximize shrinks the number of tracks has been reduced at the same time as M2P. In a 7.5 track cell, it is typical to have 3 fins per transistor but as we have transition to 6 track cells available at 7nm from TSMC and 5nm from Samsung, the fins per transistor is reduced to 2 due to spacing constraints. In order to maintain drive-current the fins are typically taller and optimized in other ways. As the industry moves to 5 track cells, the fins per transistor will be further reduced to 1.

Figure 3. Standard Cell layouts

CFETs are currently being developed as a possible path to continue to scale beyond HNS. In a CFET an nFET and pFET are stacked on top of each other as HNS of different conductivity types. In theory CFETs can scale over time by simply stacking more and more layers and may even allow lithography requirements to be relaxed but there is a long list of technical challenges to overcome to realize even a 2 deck CFET. Also, due to interconnect requirements going from a HNS to a 2 Deck CFET is approximately a 1.4x to 1.6x density increase, not 2x as might be expected. For the same process node, a 2 deck CFET would likely offer a less that 2x density advantage over an optimized FinFET, not 6x as claimed in the Seeking Alpha article.

2019 Status
In 2019 the leading logic processes in production were Intel’s 10nm process, Samsung’s 7nm process and TSMC’s 7nm optical process (7FF). Figure 5 compares the three processes.

Figure 4. 2019 Processes.

In figure 4, M2P is the metal 2 pitch as previously described, tracks are the number of tracks and cell height is M2P x Tracks. CPP is the contacted poly pitch and SDB/DDB is whether the process has a single diffusion break or double diffusion break. The width of a standard cell is some number of CPPs depending on the cell type and then DDB adds additional space versus a SDB at the cell edge. The transistor density is a weighted average of transistor density based on a mix of NAND cells and Scanned Flip Flop cells in a 60%/40% weighting. In my opinion this is the best metric for comparing process density, it isn’t perfect, but it takes designs out of the equation. A lot of people look at an Intel Microprocessor designed for maximum performance and compare the transistor density to something like an Apple Cell Phone Process with a completely different design goal and that simply doesn’t provide a process to process comparison under the same conditions.

It should be noted here that Samsung has a 6nm process and TSMC has a 7FFP that both increase the transistor density to around 120MTx/mm², In the interest of clarity I am focusing on the major nodes.

2020 Status
At the end of 2019, Samsung and TSMC both began risk production of 5nm processes and both processes are in production in 2020.

5nm is where TSMC really stakes out a density lead, TSMC’s 5nm process has a reported 1.84x density improvement versus 7nm whereas Samsung’s 5nm process is only a 1.33x density improvement. Figure 5 compares Intel’s 10nm process to Samsung and TSMC’s 5nm processes since 10nm is still Intel’s densest process in 2020.

Figure 5. 2020 Processes.

The values for Samsung in figure 5 are all numbers that Samsung has confirmed. The TSMC M2P is an incredible 28nm, a number we have heard rumored in the industry. The rest of the numbers are our estimates to hit the density improvement TSMC has disclosed.

Clearly TSMC has the process density lead at the end of 2020.

2021/2022
Now the situation gets fuzzier, Intel’s 7nm process is due to start ramping in 2021 with a 2.0x shrink. Samsung and TSMC are both due to begin 3nm risk starts in 2021. Assuming Intel hits their date, they may briefly have a production density advantage but Intel’s 14nm and 10nm process have both been several years late. With COVID 19 impacting the semiconductor industry in general and the US in particular, a 2021 production date for Intel may be even less likely.

Figure 6 compares 2021/2022 processes assuming that within plus or minus a quarter or two all three processes will be available, I believe this is a fair assumption. Intel has said their density will be 2.0x 10nm, TSMC on their 2020-Q1 conference call said 3nm will be 70% denser than 5nm so presumably 1.7x, Samsung has said 3nm reduce the die size by 35% relative to 5nm and that equates to a approximately 1.54x denisty.

In order to make Intel’s numbers work I am assuming an aggressive 26nm M2P with 6 tracks, an aggressive 47nm CPP for a FinFET and SDB.

For Samsung they have disclosed to SemiWiki a 32nm M2P for 4nm and I am assuming they maintain that for 3nm with a 6-track cell. For CPP with the change to a GAA HNS, they can achieve 40nm and SDB.

In the case of TSMC they are shrinking 1.7x off of a 5nm process that is a 1.84x shrink from 7nm and they are bumping against some physical limits. With them staying with a FinFET I don’t expect the CPP to be below 45nm for performance reasons and even with SDB they will have to have a very aggressive cell height reduction. By implementing a buried power rail (BPR) they can get to a 5-track cell, BPR is a new and difficult technology and then an M2P of 22nm is required. Frankly such a small M2P raises issues with lithography and line resistance and BPR is also aggressive so I think this process will be incredibly challenging but TSMC has an excellent track record of execution.

Figure 6 summarizes the 2021/2022 process picture.

Figure 6. 2021/2022 Processes.

Some key observations from figure 6.

The individual numbers in figure 6 are our estimates and may need to be revised as we get more information, but the overall process densities match what the companies have said and should be correct.
In spite of being the first to move to HNS, Samsung’s 3nm is the least dense of the three processes. The early move to HNS may make it easier for Samsung to shrink in the future but for their 3nm node isn’t providing the density advantage that you might expect from HNS.
Yes Intel is doing a 2.0x shrink and TSMC only a 1.7x shrink, but TSMC is doing a 1.84x shrink from 7nm to 5nm and then a 1.7x shrink from 5nm to 3nm in roughly the same time frame that Intel is doing a 2.0x shrink from 10nm to 7nm. A 1.7x shrink on top of a 1.84x shrink is a huge accomplishment, not a disappointment.

What’s Next
Beyond 2021/2022 I expect Intel and TSMC to both adopt HNS and Samsung to produce a second generation HNS. This will likely be followed by CFETs around 2024/2025 from all three companies. All of these confirmed numbers and projections come from the IC Knowledge – Strategic Cost and Price Model. The Strategic Cost and Price Model is not only a company specific roadmap of logic and memory technologies into the mid to late 2020s, it is also a cost and price model that produces detailed cost projections as well as material and equipment requirements.

Interested readers can see more detail on the Strategic Cost and Price Model here.

Conclusion
TSMC took the process density lead this year with their 5nm process. Depending on the exact timing of Intel’s 7nm process versus TSMC 3nm Intel may briefly regain a process density lead but TSMC will quickly pass them with their 3nm process with over 300 million transistors per millimeter squared!

Also Read:

SPIE 2020 – ASML EUV and Inspection Update

SPIE 2020 – Applied Materials Material-Enabled Patterning

LithoVision – Economics in the 3D Era

April 29, 2020May 7, 2023

Starting a Chip Company? Silicon Catalyst and Arm Are Ready to Help

Starting a Chip Company? Silicon Catalyst and Arm Are Ready to Help
by Mike Gianfagna on 04-29-2020 at 6:00 am
Categories: Semiconductor Services, Silicon Catalyst
1 Comment

Anyone who has started a company knows that landing the seed round of investment is just the beginning. There are many decisions to face. When to start building a sales team? What parts of the company’s infrastructure to outsource? How to price and promote your product? These are just a few of the questions to be answered. If your end product is a chip, you also face a maze of tasks regarding access to process technology, packaging and test, EDA tools and semiconductor IP, none of which is particularly easy to choose or inexpensive.

This is why a press announcement that crossed the wire today caught my attention – Silicon Catalyst Collaborates with Arm to Accelerate Semiconductor Startups.

Silicon Catalyst is an incubator that focuses exclusively on chip companies. They offer a broad range of support to get your company off the ground. I believe their singular focus on chip startups and their breadth of support make them unique in the world.

Silicon Catalyst is a new member of the SemiWiki family, and I got a chance recently to speak with Peter Rodriguez, CEO at Silicon Catalyst, about the organization and the significance of its press release with Arm. Pete is no stranger to the semiconductor business, with over 35 years of executive experience. He was formerly VP & GM of Interface and Power at NXP Semiconductors. Prior to NXP, Pete was CEO of Exar Corporation, CEO of Xpedion Design Systems, Chief Marketing Officer at Virage Logic and Major Account Manager at LSI Logic. Mr. Rodriguez also retired from the US Naval Reserves with the rank of Commander. He brings a wealth of technical and business leadership to Silicon Catalyst.

The primary news in the press release is that Arm has joined Silicon Catalyst as both a Strategic and In-Kind Partner, giving startup companies being incubated by Silicon Catalyst zero-cost access to trusted IP and support from Arm.

Silicon Catalyst’s In-Kind Partner Program offers a wide range of design tools, simulation software, design services, foundry PDKs and MPW runs, test program development, tester access and semiconductor IP, now including industry-leading IP from Arm. Arm becomes the 33^rd In-Kind partner for the incubator, joining the likes of TSMC, Synopsys, Mentor, Advantest, and Keysight, to name a few. Companies accepted into the incubator have two years of no-cost or significantly discounted access to these tools and services during the incubation period, resulting in a dramatic reduction in the cost of chip development.

Pete explained that since 2015, over 300 startup companies have engaged with Silicon Catalyst and the organization is closing in on 30 companies that have been admitted to the incubator program. Pete also discussed the many other programs at Silicon Catalyst and how they help chip startups. The Strategic Partner Program provides participants early access to review and help select the silicon startups seeking to participate in the Silicon Catalyst Incubator. Arm has also joined the Strategic Partner Program, making it the first company to join as both an In-Kind Partner and a Strategic Partner.

Silicon Catalyst maintains a growing network of over 150 seasoned Silicon Valley veterans who are available to advise portfolio companies. Their skills span technology, manufacturing, business development, sales, staffing, finance and legal matters. The Silicon Catalyst Angels was launched in July 2019 as a separate organization to provide access to seed and Series A funding for Silicon Catalyst portfolio companies.

I also had a chance to speak with Jim Hogan, Silicon Catalyst board member and semiconductor/EDA industry veteran. Jim has invested in many technology startups and has helped a lot of them achieve a successful exit. He knows the challenges of getting a chip startup off the ground well. Jim described the typical investment for launching a chip company to include $3M – $5M to get to proof of concept and perhaps another $20M or so to engage with customers. The Silicon Catalyst incubator can dramatically reduce these numbers, thanks to all their preferred tool and service access as well as the expert guidance of their advisor network.

In Jim’s words, it’s all about value preservation. Reducing the previously mentioned investment amounts allows the founding team to keep more of their company, making Silicon Catalyst portfolio companies a significantly more viable investment, and that’s good for everyone. Having seen many chip startup business plans, Jim was also able to put the current press release in context. He explained, “most of the startups I speak with say two things when they walk through the door – we need TSMC and we need Arm.” Jim sits on the board of five Silicon Catalyst portfolio companies, so he invested in the Silicon Catalyst model at multiple levels.

After my discussions with Pete and Jim it became clear that Silicon Catalyst has come a long way since its kickoff in 2015. Pete also explained that, while headquartered in Silicon Valley, Silicon Catalyst is expanding internationally. There is currently a joint venture in Chengdu, China and a presence in Israel through local partners with extensive semiconductor industry experience. The organization is also exploring expansion in Europe and India.

Simply put, if you want to start a chip company, Silicon Catalyst and Arm have you covered. Pete concluded our discussion by telling me the tagline for Silicon Catalyst. It’s a sentiment that is simple, direct and especially in the current times, a very important one I believe:

it’s about what’s next.

If you have a great idea and want to explore it with Silicon Catalyst, you can start the process here.

Also Read:

Silicon Catalyst Fuels Worldwide Semiconductor Innovation

Webinar: Investing in Semiconductor Startups

Silicon Catalyst Hosts an All-Star Panel December 8th to Discuss What Happens Next?

April 28, 2020July 28, 2020

Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems

Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems
by Daniel Payne on 04-28-2020 at 10:00 am
Categories: Events, IP, Moortec

During the COVID-19 pandemic I’m using Zoom and attending more webinars to keep updated on semiconductor industry trends, and one huge trend is the importance of AI applied to SoCs. Using more cores to handle ML and DL makes sense, but then how do you keep the chips within their power and reliability limits while at the same time achieving the greatest data throughput?

I’ve read about AI chips that have billions to even trillions of transistors, and that’s a huge challenge in several areas:

Localized junction temperatures impact performance and reliability
IR drop caused by transient switching currents increases timing delays
Process variations are localized and effect performance

In the 1970s we placed process monitor IP into the scribe lines of each wafer in order to answer some of these questions about process variation, but at the 40nm node and smaller nodes, we really need to have IP embedded within an SoC to understand what the local junction temperature is, how the VDD level is responding to noise, and which process corner the transistors are operating under.

Moortec is a UK-based IP provider that has delivered embedded in-chip sensors and monitoring to address these challenges for SoC design across several disciplines:

AI
Data Center
HPC
Automotive
Consumer

Multi-core Chip with Hotspots

With an accurate in-chip voltage monitor your design engineers can implement appropriate voltage scaling approaches:

Static Voltage Scaling
Dynamic Voltage Scaling
Adaptive Voltage Scaling

Multiple Voltage Monitors

Webinar

Register to view this webinar on Thursday, May 7th, 10AM PDT (6pm BST). There are two presenters and Daniel Nenni from SemiWiki is the host:

Richard McPartland, Technical Marketing Manager
Ramsay Allen, VP of Marketing

About Moortec

The company have been providing innovative embedded subsystem PVT IP solutions for over a decade, empowering their customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm & 5nm.

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