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September 15, 2020April 14, 2022

AI in Korea. Low-Key PR, Active Development

AI in Korea. Low-Key PR, Active Development
by Bernard Murphy on 09-15-2020 at 6:00 am
Categories: AI, Arteris, Automotive, IP

Based on press coverage and technical paper volume, you could be forgiven for thinking that Korea had decided to take a pass on AI mania, or maybe just to dabble a little here and there to stay abreast of trends. But you’d be wrong. Korea is very active in AI; they don’t feel a need to trumpet what they’re doing from the rooftops. If you dig around, there are plenty of hints. I talked with Kurt Shuler of Arteris IP to get a better understanding. I’m talking here about AI hardware, of course.

According to Kurt, most of the development action is between the Samsung Advanced Institute of Technology (SAIT), Seoul National University (SNU), and the government-funded Korea Institute of Advanced Science and Technology (KAIST), with substantial application development and competition among subsidiaries of the Samsung chaebol, which in part explains the lack of high-profile PR. Lots of internal development and competition, little entrepreneurial development outside those ecosystems.

Automotive AI

There is some activity outside these three. Hyundai and Kia do joint development. For example, they recently announced a Smart Cruise Control device that learns from the driver’s normal patterns how to adjust in a way comfortable to that driver. They base this on the fusion of sensing from cameras and radar. I couldn’t find information on ASIC support, but it’s not a stretch to assume Samsung played a significant role.

There’s an automotive Tier 1 in Korea called Hyundai Mobis which offers ADAS products, certainly within Korea, though aiming to be a worldwide supplier. They offer lane-keeping, smart cruise control (see above), autonomous emergency braking, highway driving assistance and autonomous parking. Again, unclear who is doing what in this development, but there’s no reason to believe the major IP depends on anyone outside Korea.

A startup

I was also able to find one startup, Furiosa (inspired by the movie Mad Max: Fury Road), by founders with backgrounds from Samsung, KAIST, Qualcomm and AMD. They have $7M in seed round funding from Korean investors, have built an FPGA prototype and expect to have first silicon this year.

Samsung

The bulk of the development Kurt sees is in Samsung and is predominantly applied engineering and applied research rather than core research. Arteris IP works with a number of these groups. Where is it going? Remember Samsung is massively vertically integrated. They make smartphones, of course, that need AI horsepower. But they also make TVs, fridges, other appliances, each of which has been adding AI capabilities like voice recognition. They’re not hiding this progress; they’re just not competing for attention in the “who has the biggest and baddest AI engine” race. It’s all about internal applications, from applied research, to chips, to consumer products, robotics, and industry 4.0 products.

On the flip side, SemiWiki readers know Samsung as one of the major semiconductor foundries. Samsung is very active in using AI for fundamental research in that area, to discover new materials they could use to advance semiconductor manufacturing. Along these lines, they recently announced discovery of a material called amorphous boron-nitride.

AI investment

In other recent news, the Korean government said recently that it plans to invest nearly $1B over the next ten years to advance the next generation of semiconductor development, including cutting edge AI. And Samsung reported that it plans to add 1,000 staff in AI this year.

So yeah, Korea is active in AI. They’re just not banging any drums about it. You can learn more about why so many of these groups are using the Arteris IP NoC interconnect technology HERE.

Also Read:

CEO Interview: Charlie Janac of Arteris IP

Interconnect Basics: Wires to Crossbar to NoC

Where’s the Value in Next-Gen Cars?

September 14, 2020March 25, 2022

Trusted IoT Ecosystem for Security – Created by the GSA and Chaired by Mentor/Siemens

Trusted IoT Ecosystem for Security – Created by the GSA and Chaired by Mentor/Siemens
by Mike Gianfagna on 09-14-2020 at 10:00 am
Categories: EDA, Siemens EDA
2 Comments

MentorSiemens and the GSA Team to Create a Trusted IoT Ecosystem

There’s a lot to keep you awake at night these days. If you live in California, it’s wildfires and unbreathable air. If you live on planet Earth, it’s COVID-19. And if you’re part of the value chain for IoT, it’s the security and robustness of the silicon and software fabric that connects our world. This fabric connects everything, from autonomous vehicles to the power grid to the world economy. And it’s vulnerable. A compromised piece of hardware or software can cause real damage and potential loss of life. This extends to the cloud and the data used for AI/ML. This is why the Global Semiconductor Alliance (GSA) created the collaborative Trusted IoT Ecosystem for Security (TIES) Group with Mentor/Siemens as Board Chair with board members NXP, Rambus, Microsoft and Arm.

In my opinion, creating a trusted, secure ecosystem to source the silicon and software for our current and future interconnected world is not an optional item. Rather it is a requirement for continued innovation, robust growth and a safe future. Let’s start with a look at one of the founders of this movement along with the GSA.

The Mentor/Siemens Vision

Siemens is a huge multi-national technology corporation. Electrification, automation and digitization (EAD) is a central theme for much of what Siemens does. Mentor now lives in Siemens Digital Industries, creating near-perfect synergy to tackle the challenges of the IoT ecosystem. A recent article entitled A Stroke of Genius That Saved the Day: Siemens’ Purchase of Mentor lays out the details of the Mentor synergy.

At Embedded World in 2019, Intel and Siemens delivered a joint showcase for Intel® Secure Device Onboard (SDO) and SIMATIC IPCs. Using Siemens MindSphere®, which is an industrial IoT as a service solution along with Intel® Secure Device Onboard provisioning service, a reduced cost and more robust system enabling a zero-touch mass deployment of devices was demonstrated.

This, in turn led to a three-way collaboration for a proof of concept project using Intel SDO with the Infineon TPM chip as root-of-trust for onboarding SIMATIC IPCs to MindSphere or other platforms. This demonstrates how a trusted ecosystem collaboration can be created to deliver end-to-end solutions across a variety of domains in the IoT value chain.

Secure Device Onboard (SDO) is now open source software via a Linux Foundation Edge project, and SDO technology is now migrating into an industry standard as part of a FIDO Alliance IoT initiative. A draft spec is now publicly available.

The GSA Reach

Addressing the challenges of creating a trusted IoT ecosystem requires a lot of companies to align. System OEMs, software development, design, IP, manufacturing, assembly and test along with cloud and edge applications are all involved. The problem has substantial scale. It turns out the GSA is a near perfect catalyst to bring all the key stakeholders together in one unified, focused setting. Its members represent 70% of the $450B+ semiconductor industry and include fundamental technology companies representing all major segments of the semiconductor ecosystem.

The Plan

Recently, I had a chance to chat with Tom Katsioulas. Tom is the Board Chair of the GSA TIES Group and the Head of TrustChain at Mentor, a Siemens Business. He has been working with the GSA to create the vision, charter and process to start tackling the work needed to create a trusted IoT ecosystem. Tom explained that a plan has been developed and is being circulated to the GSA membership.

This is very encouraging. With the right support, momentum from positive results and addition of new members from the broader system community, the GSA can expand its footprint and help solve a very important problem in the chip-to-cloud IoT value chain. New ecosystem members, from OEMs, to IC and PCB, to embedded system, to device, to edge applications, to digital twins are all needed.

Tom explained that the objective of this work is to promote trusted end-to-end solutions in the IoT value chain that accelerate the adoption, growth and field use of connected chips, devices, systems and IoT applications. Enabling recurring services revenue streams and high value business models is also a focus. Ambitious goals for sure, but ones that have the significant vision and support from the GSA TIES Group.

The operating model for the program is illustrated by the figure on the right. The process builds on itself with continued successful application to a growing list of end-to-end use cases that drive collaborative solutions and guidelines in the IoT value chain.

The output of these activities will be provided to the relevant parties (including standards organizations) for potential action and implementation. Tom explained that there are organizations usually in need of a well-defined problem statement with clear goals, use cases, examples and a group of companies to support the work. The GSA Trusted IoT Ecosystem Security Group can provide all this and promote any best practices developed.

Call to Action

Ecosystems capture higher value than sum of members acting independently, and trust is essential for collaboration. A number of companies are committing to contribute content for the effort. If you are a member of the GSA, you will have the opportunity to participate in this important initiative. If you’re not a GSA member, you can still participate. Either way, get involved and contribute. You may well be helping to save the planet.

You can learn more about this Trusted IoT Ecosystem for Security here. You can also contact Shungo Saito: SSaito@gsaglobal.org. Shungo is the director, program development at GSA.

Also Read:

Emulation as a Service Benefits New AI Chip

WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido

Creating Analog PLL IP for TSMC 5nm and 3nm

September 14, 2020January 27, 2022

CEO Interview: Pengwei Qian of SkillCAD

CEO Interview: Pengwei Qian of SkillCAD
by Daniel Nenni on 09-14-2020 at 6:00 am
Categories: CEO Interviews, EDA, SkillCAD

Pengwei Qian is the founder and CEO of SkillCAD, a grassroots EDA company that has amassed the most impressive customer list (60+ companies) I have experienced for a company of this size, absolutely.

Pengwei has a Bachelor’s degree in Physics and a Masters in Material Science from Fudan University and a Masters in Electronic Engineering from National University of Singapore. He started as an IC designer and now has more than 20 years of experience in EDA. Pengwei is also the co-founder of MiniSilicon and founder of YAMMI Inc.

Why did you start SkillCAD?
When I was a CAD engineer for Elantec (acquired by Intersil) I saw that layout design required many repetitive mouse clicks, even for simple tasks. As IC design became more complex so did the use of highly repetitive commands which significantly reduced layout team productivity while increasing the number of design errors and tape-out delays. I felt that if tedious, repetitive, layout tasks could be simplified and automated it would reduce design time and increase the layout quality of results.

But the automation could not come at the expense of loss of control by the layout designer. The type of custom layout design required by sophisticated Radio Frequency (RF), Power Management (PM), and many other complicated Mixed-Signal applications requires that the experienced layout designer maintain complete control of the design outcome. The focus of SkillCAD has always been to create commands to automate complex layout tasks so that the designer can focus on the critical thought processes needed to create high quality layout.

How does SkillCAD integrate with the Cadence Virtuoso Layout Suite?
As the name implies, SkillCAD is a collection of layout commands written in the SKILL programming language. The SkillCAD IC Layout Automation Suite (IC LAS) seamlessly integrates into the Cadence Virtuoso layout design environment, using the layout and rule files supplied by the Cadence system. Since the tools were developed to support the native Cadence library objects they can be used in compliment to the Cadence tools. The levels of simplification and automation afforded by the SkillCAD commands can improve layout productivity by more than 50%. Cadence Virtuoso plus SkillCAD IC LAS have become the preferred layout environment for analog, RF and mixed signal designs.

What are the benefits of using SKILLCAD?
In the past internal CAD groups have independently written SKILL based tools for layout teams but rarely do they have the number of proven commands that are found in IC LAS. SkillCAD works closely with the top semiconductor companies and foundries integrating the latest design practices and process technologies. It really is a collaborative software product with many years of experience embedded into it.

Can you provide more detail on that?
Sure, SkillCAD commands have been used in production IC design for more than 12 years and have been developed in response to requests by layout designers around the world who are experts in the field and know what they need to increase their productivity and accuracy.

The commands are inspired by dedicated semiconductor professionals and implemented in innovative ways. SkillCAD’s proprietary “correct and optimized by construction” commands eliminate design rule violations, automates complex error prone layout implementation, and significantly improves a layout team’s productivity.

SkillCAD tools are maintained and supported by our SKILL programming experts, who are also knowledgeable on the needs of layout designers. This relieves CAD teams, often under-manned and over-tasked, of the burdens of trying to develop and maintain tools specific to layout teams or semiconductor manufacturing technologies. The initial setup required for SkillCAD IC LAS is minimal and can be done for each manufacturing process. Today SkillCAD IC LAS works with Cadence Virtuoso Platforms: IC5, IC6, IC12 and IC18.

Who is the typical customer of SkillCAD IC LAS?
SkillCAD commands are designed to support all levels of the layout design flow and adapt to the design methodologies of most layout teams and individuals. Today our 120+ commands target custom mixed signal, RF and analog designs for process nodes at 12nm and above. We do have customers using IC LAS for advanced FinFET processes down to 3nm which will be fully supported in the upcoming release.

What are some of the issues associated with advanced process nodes as it relates to Layout design?
What makes designing at 10nm and below difficult is the increased complexity that comes from the additional physical design rules and constraints required for the additional metal layers and EUV technology. Advanced nodes also require that Layout teams must now incorporate sophisticated color-aware custom routing and color aware physical design layout.

To better understand the upcoming layout challenges SkillCAD works very closely with advanced node customers and foundries to develop new commands and features to provide the automation needed to insure their layout teams can handle the increased complexity and shorten time to tape-out.

Where are you located and can you tell me a little more about your company?
We are located at 1580 Old Oakland Road, San Jose CA. We have been a Cadence connection partner since 2008. We have distributors in Japan, China, Erupoe, Taiwan and Korea. Feel free to visit our website to learn more: www.SkillCAD.com. Should you want to view our 120 commands with tutorials and videos just click on the link below. www.SkillCAD.com/reference-guide. If you would like a demo or download an eval license please contact us at support@SkillCAD.com.

Also Read:

CEO Interview: Charlie Janac of Arteris IP

CEO Interview: Anna Fontanelli of Monozukuri

CEO Interview: Isabelle Geday of Magillem

September 13, 2020April 26, 2022

VLSI Symposium 2020 – Imec Monolithic CFET

VLSI Symposium 2020 – Imec Monolithic CFET
by Scotten Jones on 09-13-2020 at 10:00 am
Categories: Events, Semiconductor Services, TechInsights
2 Comments

The 2020 VLSI Technology Symposium was held as a virtual conference from June 14^th through June 19^th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.

It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung has already announced that they are moving to Horizontal Nanosheets (HNS) at 3nm. TSMC is staying with FF at 3nm but is expected to move to a new architecture for 2nm. Intel is expected to stay with FF at 7nm and then move to HNS at 5nm, assuming they are still pursuing their own technology at that point.

The most likely roadmap for the industry is FF to HNS with or without Forksheets, and then to transition to Complimentary FETs (CFET), see figure 1.

Figure 1. Imec CMOS Roadmap.

The forksheet and CFET provide shrinks by improving the n to p spacing with CFETs stacking nFET and pFET devices, see figure 2.

Figure 2. CFET structure.

In the current work a “monolithic” CFET has been developed by using separate wafers for the nFET and pFET and then bonding them together versus a “sequential” CFET where both FET types are fabricated on the same wafer. Imec claims that the monolithic technique is less expensive than the sequential technique with the sequential technique requiring SOI that adds 1% to the substrate cost, see figure 3.

Figure 3. Monolithic CFET cost advantage.

Authors note, my company is the leading provider of cost and price models to the industry. I plan to cost model this process versus the sequential process but have not had time yet. I find the ~1% higher starting wafer cost confusing for two reasons, one, I do not believe sequential CFETs requires SOI and two, SOI is a lot more than ~1% more expensive than a standard wafer. The monolithic approach will also require two starting wafers and not just one. In my opinion this cost analysis needs more investigation.

In the monolithic approach the nFET and pFET are fabricated on separate wafers allowing each device fabrication flow to be optimized for that device. The process flows for each wafer is illustrated in figure 4.

Figure 4. Process flows for monolithic CFET.

As we move to N3 and beyond less n to p separation reduces parasitics and improves performance. Also moving to gate all around (GAA) from FF improves electrostatic control by providing a gate on all four sides instead of three sides.

Monolithic CFET as fabricated in this work provides an alternative to sequential CFET for next generation devices and bear further investigation

Also Read:

SEMICON West – Applied Materials Selective Gap Fill Announcement

Imec Technology Forum and ASML

VLSI Symposium 2020 – Imec Buried Power Rail

September 13, 2020September 14, 2020

The Cloud Changes Connected Cars

The Cloud Changes Connected Cars
by Roger C. Lanctot on 09-13-2020 at 8:00 am
Categories: 5G, Automotive

Rare is the auto maker today that views connectivity as an option when designing a car. Connectivity is essential even if it is not yet universally available.

Strategy Analytics interviewed a selection of automotive executives in connection with a white paper prepared for Ericsson to explore this proposition. (“Connected Vehicle Services: Benefits of Automotive Cloud” ) The findings suggest a growing opportunity for public cloud partnerships in the automotive industry.

This year was the first for which more than half of all cars manufactured globally shipped with built-in cellular wireless connections. It is a remarkable level of industry commitment given the demanding operating environment of a moving vehicle and the uneven quality of wireless connectivity globally.

The challenging operating condition of a wireless connectivity device in a car with power management, temperature, and vibration issues, paired with the varying quality of wireless reception is enough to give pause to even the boldest car makers. “Why am I doing this,” one such car maker executive might ask. “It just seems like I am asking for trouble.”

Add to this complex connectivity decision-making matrix the ambivalence with which car buyers greet connectivity and car makers are in a real pickle. The need for a wireless connection to the car today is manifest, the reality is expensive and complicated, the consumer is ambivalent or perhaps even hostile.

For many car buyers, connectivity means privacy violations and cybersecurity threats. And most auto makers – seeking an immediate return on their investment – are charging the consumer with a monthly or annual fee for the privilege of having an on-board wireless connection.

Oddly enough, consumers around the world surveyed by Strategy Analytics say they are in fact interested in connectivity – though they may not want to pay for it. In spite of the cost and complexity, car makers have become quite enthusiastic.

For auto makers, connectivity is a gateway to greater customer retention and advanced product life cycle management – including software updates and enhanced feature deployment – to say nothing of the fact that car connectivity is expected to rewrite the rules of insurance underwriting. Car makers may not want to part with their legacy of selling cars and more or less forgetting about them, but in a world of increasingly connected things the value proposition inherent in a connected car is tantalizing.

The need for vehicle connectivity has translated into a need to understand, in advance, the quality of vehicle connections in real-time. This need has introduced the concept of predictive quality of service (PQOS). For embedded connectivity systems to function properly they must be able to anticipate, in real-time, the availability and quality of wireless car connections.

The onset of 5G networks has further stimulated car maker interest in connectivity as the prospect of wireless enabled collision avoidance and automated driving enter the conversation – to say nothing of teleoperation. The connected car has now become part of the Internet of Things communicating with other cars, infrastructure, and pedestrians.

Car makers have been suddenly thrust into the world of big data and cloud computing. Cars that, today, exchange maybe a 1Gb or two of data per month will soon be exchanging 8Gb of data a day.

Car makers are being forced to come to terms with the need for increased cloud storage and data processing capability linking the disparate worlds of enterprise, manufacturing, distribution, and vehicle ownership. It is the cloud computing associated with connected cars, though, that offers the greatest opportunity for value creation and cost savings – if car makers can overcome their resistance to adding public cloud partnerships.

The small sample survey of automotive executives carried out by Strategy Analytics reveals the overwhelming need for cloud-based computing resources and the lingering resistance to reach out to external resources. The easiest justification for acquiring external relationships and capabilities is the correlated cost savings versus a reliance on internal systems and expertise.

Strategy Analytics’ executive surveys reveal a turbulent decision-making environment sweeping the automotive industry related to cloud computing. Car makers are increasingly turning to multiple cloud partners for different application and development scenarios.

Moreover, agreements are signed and deals broken on a routine basis as needs change or as complex implementations overwhelm development teams. The dynamic automotive cloud computing market is already testing the resilience and patience of both car makers and suppliers.

Key to surviving and thriving in the current competitive environment will be a keen understanding of the means to overcome connectivity challenges in an unforgiving operating environment. With connectivity becoming an essential element associated with the safe operation of vehicles, car makers will be looking for partners with expertise in measuring and managing connectivity.

Ericsson has pioneered the concept of predictive quality of service which has been more or less codified by the 5GAA. Multiple organizations are working on standards and requirements. (“Making 5G Proactive and Predictive for the Automotive Industry”

The 5GAA identified nine factors involved in proactively predicting the quality of service at a particular time for a particular car driving along a particular route.

SOURCE: 5GAA

The onset of both C-V2X cellular connectivity and 5G in cars will introduce the prospect of multiple simultaneous vehicle connections which, in turn, will introduce the need for triaging vehicle data exchanges based on the nature and urgency of different applications.

While the future may bring streaming audio and video content to vehicle “drivers” and passengers, navigation systems enhanced by real-time roadway and weather conditions, and built-in digital assistants awaiting customer commands, the real revolution in vehicle connectivity lies in safety and collision avoidance. Car makers are looking for cloud and edge solutions to reduce traffic congestion and vehicle emissions and improve the efficiency of vehicle operations. With the help of PQOS, C-V2X and 5G technologies will help deliver on these promised benefits of connectivity within a few short years. Car makers will be able to save lives and enhance customer retention with cloud-enhanced car connectivity.

September 13, 2020September 14, 2020

Could loss of SMIC lead to loss of most of China?

Could loss of SMIC lead to loss of most of China?
by Robert Maire on 09-13-2020 at 6:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services
5 Comments

Is the US finally getting truly tough on China? or just a bluff?
Could lead to a global reset of the industry & 10 year retreat?
Tech stocks wings have melted after super heated stock run?
SMIC added to the “naughty” list?

There have been numerous reports that the US is considering adding SMIC to the China “naughty” list of bad actors linked to Chinese military or defense related industries.

Trump administration weighs blacklisting China’s chipmaker SMIC

This is obviously a continuation and escalation of the tit for tat trade exchanges between the US and China. Huawei has so far been the focal point and star of the show having taken over from the opening acts of ZTE and Jinhua.

It is an important escalation as someone in Washington has finally figured out that stopping China from buying chips also means that you have to stop selling them equipment to make chips….. duh!!!

It s also naive to assume that China would never use its most advanced fab to make chips with non-civilian use cases. Just where do all the chips in China’s latest military equipment come from?…the tooth fairy? TSMC? SMIC? Lets get real. You don’t need some Washington think tank (SOS International) to figure that out….

U.S. Weighs Export Controls on China’s Top Chip Maker. Will the ban spread beyond SMIC?

We think its safe to say that because SMIC is the most advanced of China’s native fabs , it is at the top of the list to go after. Such as stopping the shipment of an EUV scanner.

But it is also equally as clear that there are a number of Chinese memory fabs that are quite advanced, though lesser known, that might get on a list.

We think its a safe bet that SMIC is just first on a long list of perhaps most if not all of China’s new, domestic fabs.

The ban may not spread to fabs owned by non Chinese firms such as Intel or Samsung etc, but then again , those fabs are by design not at the leading edge.

Foundry makes sense to ban first as it would be a replacement for TSMC capacity and potentially try to keep Huawei limping along in business.

China is up to half of Semiconductor Equipment business

Unless you have been asleep for the last ten years, China is the fastest growing market for semiconductor equipment as well as the largest market for most equipment. Although spread over a larger number of customers as compared to Korea (Samsung) and Taiwan (TSMC), China is still huge.

SMIC recently raised $7B in a public equity offering which is on top of $2B raised from the Chinese government in the spring. The vast majority of that $9B was likely going to purchase semiconductor equipment (maybe some facilities), with most of that likely purchasing US made equipment.

The percent of business which China represents for US equipment companies is anywhere from a quarter to a half of business with most being at the upper end of the range. This means that the loss of China business could be devastating and set semiconductor equipment companies back almost 10 years to when China started its huge investment run a while ago.

We don’t see Japan coming back as a huge force in semiconductor manufacturing nor do we see the US on a comeback path, especially after Intel announced its “fab lite” model to outsource more manufacturing to TSMC.

A “cold turkey” cut off could be very ugly

If the US government decided to cut off SMIC cold turkey, things could get very ugly, very quickly. Much like Jinhua we would have to assume that the government would also cut off support of existing installed equipment as well, which would cut off recurring revenue as well.

At Jinhua, US companies employees left literally in a day and were on the next plane out leaving the fab in a lurch and killing it in 24 hours.

Without spare parts, maintenance and upgrades SMIC would have serious problems continuing to function.

So much as with ZTE, Jinhua and Huawei, denying access to US technology could prove a death sentence for SMIC.

Not much political leverage

As we have pointed out many times over the last several years, semiconductor and semiconductor equipment makers are primarily headquartered in California, which the current administration could care less about….well maybe not less than the Netherlands (ASML).

As we get closer to the election, more aggressive posturing is likely, which would include that “no one is as tough on China as us”, to increase election odds.

The administration could easily cut off SMIC in front of the election only to open it back up based on some new trade deal afterwards. Getting tougher on China will only increase much needed votes.

No easy way out

There is no easy way out of the situation. The administration has put itself in a corner it can’t back down from without looking weak on China at a bad time. Technology is one of the few leverage points the US has, especially in semiconductors and it likely needs to use it as it has run out of levers to pull.

We think the situation will get bad the only question is how bad and how quickly. With time pressures on we could get an announcement soon.

Tech stocks and Icarus…flying to high…then melting

Tech stocks and especially semiconductor stocks have been on fire all through Covid as a safe refuge due to the work at home economy and need for laptops and servers.

We have been suggesting and warning that this could see a poor end once the initial flurry of buying cools down to the reality of unemployment and an ugly holiday season.

There has already been noise of weaker memory demand/pricing looming. One of our biggest concerns is that the threatened cut off of Huawei has generated a storm of buying, hoarding and stocking up in front of the drop dead date. Which we think has created a false sense of demand that many investors have viewed as 100% real.

The Scramble for Chips

Hong Kong Chip route cut

Huawei will have a lot of inventory to work down but will need it. So far, non Huawei demand is very strong at TSMC and will likely fill any near term void but perhaps not forever. Right now TSMC is in good shape as it ramps for its biggest customer, Apple , and their latest release, but after that???

The Icarus effect…Tech stocks flew too high

Tech stocks have gotten over inflated during Covid as money looked for a safe haven from the Covid fallout, and as today’s stock action noted the air may not come out of them slowly but rather suddenly as investors figure out that even tech is not safe as SoftBank and now SMIC may be only be the beginning.

As is usually the case, sub suppliers such as AEIS, UCTT and ICHR are the hardest hit and most volatile with each being off over 10% today. KLAC and AMAT with high Chinese exposure were down 9%, along with LRCX.

SMIC and Huawei related fears could be the catalyst for a correction in chips, especially if we get confirmation of the administrations potential actions.

Although we could also get a dead cat bounce here we think its safer on the sidelines as at the very least it will be volatile for a while and we don’t see nearly as much upside as we see downside here as it could get uglier still….

September 11, 2020May 6, 2022

Online Verification Meet-up With Intel and Arm!

Online Verification Meet-up With Intel and Arm!
by Daniel Nenni on 09-11-2020 at 10:00 am
Categories: Events, Semiconductor Services, Veriest

Veriest is headquartered in Israel with engineering sites in Serbia & Hungary. The team has accumulated a wealth of experience through involvement in projects in the forefront of semiconductor technology.

Veriest maintains unrivaled quality standards in terms of both service and knowledge. With the ability to take on all significant parts of the design process ourselves, we offer detailed expertise coupled with a big-picture view that enables us to successfully address any issue that arises during the verification process.

By demanding complete accuracy and taking into account all the intricacies of each specific case, including schedules, resource limitations and technical specifications, Veriest is able to achieve the very best levels of efficiency.

REGISTRATION

Now Veriest is inviting us to join their next event, with an interesting keynote about Safety in Deep Learning devices and an award-winning technical presentation about formal verification of deadlock cases:

Speakers and Agenda

Technical presentation

Save Your Place!

Also Read:

Python in Verification. Veriest MeetUp

5 Talks on RISC-V

Ramping Up Software Ideas for Hardware Design

September 11, 2020October 3, 2020

Samtec Delivers Ultra-High Density with Direct Connect™ to IC Package Technology

Samtec Delivers Ultra-High Density with Direct Connect™ to IC Package Technology
by Mike Gianfagna on 09-11-2020 at 6:00 am
Categories: Samtec, Semiconductor Services

We all know the signal integrity and power integrity challenges of high-performance system design. It used to be enough to design a robust chip. Now, the interaction between the chip, the substrate/package and the PCB all matter. If your design is 2.5D, as many are these days, the problems just gets worse. Chiplets are becoming more popular as a method to bring known-good interfaces to a design. This technology creates even more challenges associated with interconnect. Don’t give up hope, Samtec addresses these challenges and delivers ultra-high density with direct connect to IC package technology.

As is the case with a lot of Samtec product lines, there is a well thought out roadmap for what’s needed today and tomorrow. For today’s interconnect, Samtec offers FireFly™ Micro Flyover System™. 28 Gbps NRZ and 56 Gbps PAM4 speeds are supported and both copper and optical transport are available. And around the corner is Si-Fly™, delivering 56 Gbps NRZ and 112 Gbps through copper and optical transport.

These systems utilize Samtec’s Direct Connect™ Technology. These interconnects can directly connect to the IC package, bypassing the PCB and route signals from the silicon through a long-reach cable, such as Samtec’s FlyOver® cables assemblies. The result in a denser design and higher performance since PCB parasitics are bypassed. Up to a 5X increase in reach is achievable with this approach. 5G, high-performance computing, emulation and machine learning are example applications that benefit from the enhanced speed and reach of the Samtec ultra-high density with direct connect to IC package technology approach.

I recommend an excellent video that explains a FireFly demo Samtec delivered at DesignCon 2020. The demo is presented by Keith Guetig, Samtec high-speed product manager. The video is part of a post from Danny Boesing, product marketing director at Samtec. As an aside, you will find a rich library of information, collateral and videos on Samtec’s website. There’s a lot to learn there. Back to the demo. At a little over four minutes run time, you can get a lot of information in a short amount of time.

Keith explained that the demo incorporates eight BGA-style packages. Four use FireFly copper cable assemblies and four use FireFly optical cable assemblies. The signal path runs from the die to the Samtec connector on the edge of the chip package. The copper signal path uses Samtec ulta-low skew twinax cable assemblies. There are 32 copper direct connect assemblies in the demo and 16 optical direct connect assemblies. Connecting one of the optical channels to a Keysight scope reveals a wide-open eye diagram with plenty of margin for the system designer as shown.

Keith goes on to list the benefits of Samtec Direct Connect technology compared to traditional PCB topologies, which include:

Increased density in a smaller footprint allowing for higher data rate density
A future-proof design, since optical or copper interconnect can be used with the same connector
A 5X increase in reach due to no PCB interconnect

He also goes into some details about Samtec’s next generation Direct Connect technology – Si-Fly. The low-profile, high density of this technology will deliver 25.6 TB aggregate data rate with a path top 51.2 TB in the time frames shown in the figure, below.

Keith concludes the video with a discussion of the IEEE 802.3ck insertion loss spec, which limits the reach of high-speed PCB substrates to 4.5 inches. Samtec’s approach with Si-Fly Direct Connect and ultra-low skew twinax shatter this barrier and support 22 inches of reach before approaching the IEEE limits. Don’t like the IEEE 802.3ck rules? Change them with Samtec. IF you want more information about how Samtec delivers ultra-high density with direct connect to IC package technology, you can start here.

September 10, 2020October 3, 2020

How HCL VersionVault Works – Directory Versioning

How HCL VersionVault Works – Directory Versioning
by Mike Gianfagna on 09-10-2020 at 10:00 am
Categories: EDA, HCL Software

Pieter Gosselink Senior Technical Support Engineer HCL Technologies

Last month, I discussed a webinar about HCL VersionVault – HCL VersionVault Delivers Version Control and More. This webinar introduced the HCL VersionVault product. This post will discuss a new video entitled “How HCL VersionVault Works – Directory Versioning.”

To recap, VersionVault delivers a lot of capabilities to the software development process. These include:

Version control software
Enterprise class (unlimited scalability and the ability to handle very complex structures)
Easy to use with a built-in configuration management process
Good for regulated industries thanks to built-in authoritative auditing capabilities
Reduces time for embedded system development
Can synchronize design among a globally disparate development team

Also discussed during the webinar was the virtual file system and the benefits that technology delivered. Recently, HCL has released a new video that digs into aspects of the file system inside VersionVault. While this kind of detail isn’t for everyone, I find it refreshing that HCL is providing this level of insight into how their product works.

Successful deployment of any enterprise tool requires a broad spectrum of participation and stakeholders. An easy to use product that is supported by good training and documentation is a necessary condition for success. If the product solves a well-known problem in an efficient way (from the user’s perspective) that helps a lot with adoption. For all this to work, there needs to be a broader infrastructure and stakeholder list, however.

Typically, power users will lead the way to adoption and others will follow. These users are supported by the development team and typically require insights into how the tool works that go well beyond what an average user would care about. The recent video on how directory versioning works in VersionVault provides the kind of insights these users will need. I was encouraged to see HCL deliver these details, I’m sure it will help with the adoption process.

The video isn’t done in a typical webinar format. It is presented by Pieter Gosselink, senior technical support engineer at HCL Technologies. Peter is behind a clear glass. He uses this surface as a white board to illustrate his points. It’s a clever way to deliver the content since you get to see both the speaker and the annotation on the full screen. It does require Peter to write backwards, which is impressive.

Peter’s video is short (~ 5 minutes), so if you have interest in learning about the inner workings of VersionVault I encourage you to watch it. Here are some of the basics to whet your appetite:

The VersionVault file system is based on a combination of directories and file elements organized in a tree-like structure
Like file elements, directories can have versions
The first version of a directory is empty
It should be noted that files get their names from data in the directory elements. This is how Unix works we well
When a directory version is populated, each file will be represented by a record number and file name (the record number is part of the file element as well)

Peter goes on to explain how versioning of directories is implemented and how those structures track the files associated with each directory version, ensuring all data is accounted for under all circumstances.

You can watch the video, “HCL VersionVault Works – Directory Versioning” here. If you’d like to watch the webinar on the product, you can access the replay of Introducing HCL VersionVault here. You can also learn more about HCL VersionVault here.

About HCL Technologies

HCL Technologies (HCL) empowers global enterprises with technology for the next decade today. HCL’s Mode 1-2-3 strategy through its deep-domain industry expertise, customer-centricity and entrepreneurial culture of ideapreneurship™ enables businesses transform into next-gen enterprises.

HCL offers its services and products through three business units – IT and Business Services (ITBS), Engineering and R&D Services (ERS) and Products & Platforms (P&P). ITBS enables global enterprises to transform their businesses through offerings in areas of Applications, Infrastructure, Digital Process Operations and next generational digital transformation solutions. ERS offers engineering services and solutions in all aspects of product development and platform engineering while under P&P, HCL provides modernized software products to global clients for their technology and industry specific requirements. Through its cutting-edge co-innovation labs, global delivery capabilities and broad global network, HCL delivers holistic services in various industry verticals, categorized under Financial Services, Manufacturing, Technology & Services, Telecom & Media, Retail & CPG, Life Sciences & Healthcare and Public Services.

As a leading global technology company, HCL takes pride in its diversity, social responsibility, sustainability and education initiatives. As of 12 months ended June 30, 2020, HCL has a consolidated revenue of US $ 9.93 billion and its 150,287 ideapreneurs operate out of 49 countries. For more information, visit https://www.hcltech.com/

September 10, 2020March 25, 2022

Emulation as a Service Benefits New AI Chip

Emulation as a Service Benefits New AI Chip
by Bernard Murphy on 09-10-2020 at 6:00 am
Categories: AI, EDA, Siemens EDA

It’s no secret that innovation in AI chip architectures is on a tear. When you put together the spatial complexity of highly parallelized algorithms with the need to localize memory accesses on-chip to the greatest extent possible, we’re seeing a proliferation of all kinds of domain-specific architectures. Which in the normal cycle of these things inevitably leads to wondering if there might be a good general-purpose architecture for AI chips. One recent entry in this field is from Simple Machines, based in San Jose. They have a novel approach they call Composable Computing, in which they build on four fundamental behaviors: data gathering, computational dataflow, synchronization between algorithm stages, and control. Using this platform, they illustrate how they can reconfigure on-the-fly to implement multiple different types of accelerator. To do that, the needed help from Emulation as a Service (EaaS).

Early software prove-out through EaaS

The tricky part is the software. To take advantage of that composability and specialization in behaviors a compiler needs to manage computation placement, data routing, event timing, resource utilization and other goals. This is not a regular compiler and must be tested very carefully. Compounding the problem, workloads for AI engines are huge. So how are you going to test, debug and refine that software while the hardware is still in development?

The normal answer would be an FPGA prototype. Which would work for a small inference engine. But these big general-purpose engines are designed for training as well as inference. They barely fit in an SoC reticle, much less in a single FPGA. And custom FPGA boards come with their own problems. So Simple Machines turned to emulation, with Mentor.

The emulation challenge for startups

Simple Machines is a young company, still on their Series A round and still proving themselves to early stage customers. I’m guessing that they are talking to strategic investors who might want to participate in a Series B round. To raise that level of interest, Simple Machines will need to show a proof of concept to those investors, perhaps early silicon or an emulation prototype. But emulators are expensive. How could Mentor help?

Through Emulation as a Service is how. The ‘as a Service’ concept has taken off widely for organizations that doesn’t have the constant heavy workloads to justify purchasing hardware and software. Emulation needs in a startup are a good example of a cyclic need. Simple Machines can buy access in blocks rather than buying the emulator.

The EaaS flow

John Anderson, Verification Consulting Manager at Mentor told me how this works. Mentor establishes a secure chamber (a virtual Linux host) loaded with Mentor software for emulation and debugging. They also establish an encrypted Mentor Secure Transport (MST) channel for a customer to support secure transfer of data between their site and that chamber. That customer also gets remote desktop software to allow VPN-like access to their own chamber.

As needed Simple Machines were able to upload their design and software to the chamber. The Mentor’s EaaS team provided expert consulting to optimize the cost- and time-efficiency advantages of the Veloce emulation hardware technology. Simple Machines could then compile code, launch jobs, debug and edit designs in the remote chamber via their desktop interface. Once they were done, they could pull results back to their own machines via MST.

Performance and power modeling

One more noteworthy point. Simple Machines were using EaaS not only to model performance but also to model power consumption to assess key power metrics in this pre-silicon design. Modeling the most important aspects of their prototype in preparation for discussions with those strategic investors.

You can read the press release HERE.

Also Read:

WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido

Creating Analog PLL IP for TSMC 5nm and 3nm

Getting Physical to Improve Test – White Paper