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A 2021 Summary of OpenFive

A 2021 Summary of OpenFive
by Kalar Rajendiran on 02-01-2022 at 10:00 am
Categories: Chiplet, OpenFive, Semiconductor Services

Key Features of the Edge AI Vision Platform

Building a better mousetrap plays a key role in achieving market success in any industry. Of course, building one requires differentiating the product from the others already in the market. A differentiated product can even lead to creating demand for new products in adjacent markets. All of this is great but how do you implement the differentiation? In the semiconductor industry, it is through a combination of custom circuits and software. While custom silicon solutions as a market segment has been around for a long time, it certainly has gone through its waxing and waning phases. The partition of customization implementation between hardware and software is an ongoing balancing act and is dictated by various driving factors.

Currently, there are a few trends that are reinvigorating the custom silicon solutions industry. The move toward domain-specific architectures, more processing at the edge and edge-AI accelerators are some of those trends. The spectrum of power, performance, area (PPA) and latency requirements demand custom silicon. These factors are driving innovations in design methodology, interfaces, and packaging to name just a few areas. Custom silicon solution companies will be playing a critical role over the coming years.

Who is OpenFive?

OpenFive is a full-service custom silicon solutions company with differentiated IP that offers a proven path from custom SoC architecture to volume silicon. More below from their website.

“OpenFive offers end-to-end expertise in Architecture, IP Integration, Design Implementation, Software, Silicon Validation, and Manufacturing to deliver high-quality silicon in advanced nodes down to 5nm. With spec-to-silicon design capabilities, customizable platforms, and differentiated IP for Artificial Intelligence, Datacenter/High Performance Computing, Networking, and Storage applications, OpenFive is uniquely positioned to deliver highly competitive domain-specific processor-agnostic SoCs customized for your application.”

You can learn more about OpenFive from an interview of their CEO that SemiWiki published..

With the above as the backdrop, let’s review how OpenFive fared in 2021.

As an overview, they completed a year filled with interesting accomplishments and are poised for continued growth in 2022. Some of their 2021 accomplishments are highlighted below.

Chiplet-optimized IP Subsystems

With unrelenting time to market pressures, the key to increased productivity is leveraging pre-verified IP subsystems. OpenFive offers many different IP subsystems addressing connectivity and memory interfaces. You can learn more at their IP portfolio page.

With chiplets-based design implementations gaining momentum, OpenFive developed a die-to-die (D2D) IP subsystem. The subsystem supports low-power, high-throughput, and low-latency links enabling quicker integration for heterogenous chipset connections in wired communications, AI and HPC applications. You can learn more from a SemiWiki post published last year.

Edge AI Vision Platform

With the market trends noted earlier, standard chips will have difficulty meeting the wide range of performance, power and latency requirements. A custom system-on-chip (SoC) tailored for a specific edge application will deliver a competitive advantage in the marketplace. The competitive differentiation is contained within a portion of a SoC with the bulk holding necessary functions but not the differentiators.

Given the above, it makes sense to start with a platform that includes preconfigured subsystems and customize with one’s key differentiators. The customization could be limited to just adding your own custom accelerators. Or it could include customizing the different subsystems and mixing and matching with different interfaces to meet an application’s unique requirements.

With a long list of edge AI applications, OpenFive launched an Edge AI Vision platform that makes it easier for building customized edge AI SoCs. You can learn more from a SemiWiki post published last year.

 

OpenFive offers a turnkey solution by handling the entire process from design to IP procurement to manufacturing, test, prototypes and production.

Processor IP

While OpenFive as a custom silicon solutions provider is processor agnostic, they do have a front-row seat when it comes to RISC-V. With a multitude of RISC-V SoC designs and tapeouts, OpenFive is in a vantage position to translate the advances SiFive makes into custom silicon solutions. With the tremendous momentum behind RISC-V, this could be a major differentiator for customers. For example, SiFive has been enhancing RISC-V vector extensions to accelerate performance on ML workloads. You can learn more from a SemiWiki post published last year.

Leading-Edge Design to Production Capabilities

OpenFive offers custom silicon services on a wide range of foundries and process nodes including leading-edge process nodes. They announced a successful tapeout of a high-performance SoC on TSMC’s N5 process. The SoC is targeted for HPC/AI, networking and storage solutions and includes their HBM3 IP subsystem, D2D IP subsystem as well as SiFive’s E76 32-bit CPU core. You can learn more from their press release here.

Commitment

Even during the pandemic-stricken year, their consistent presence at industry and partner events is commendable.

You can review their extensive set of resources/collateral in the form of on-demand webinars, technical papers, brochures here.

Also Read:

Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads

Die-to-Die Interface PHY and Controller Subsystem for Next Generation Chiplets

Enabling Edge AI Vision with RISC-V and a Silicon Platform

 

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WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama

WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama
by Don Dingee on 02-01-2022 at 6:00 am
Categories: EDA, Events, Keysight EDA

Flat Z design and voltage ripple example in board-level EM simulation

Advanced board designs are fertile ground for misbehavior in time and frequency domains. Relying on intuition, then waiting until near-final product for power integrity (PI) or EMI testing almost guarantees board respins are coming. Lumped-parameter simulations of on-board power delivery networks (PDNs) struggle with predicting behavior in the face of parasitics. A new series of Keysight engineering webinars dive inside PDNs with critical insights on where PI problems develop. Results from Keysight’s board-level EM simulation and EMI compliance analysis tools and techniques can help teams reduce late respin drama.

Modeling on-board power delivery

One of these webinars tears into decoupling capacitors. If a few are good, more must be better, right? That myth gets busted quickly, and so does another. Capacitor manufacturers want engineers to think they’re buying a certain value of a capacitor. Instead, what every manufacturer ships is a bundle of impedance with resistance, inductance, and capacitance.

Now multiply by a bunch of decoupling caps of different values across a board. Clean power delivery and controlled EMI depend on how those capacitors interact with loads, and each other, at various frequencies. A PDN provides three sources of power:

  • The voltage regulator module (VRM), which resembles a low-pass filter. At higher frequencies, the VRM control loop falls behind and its output impedance goes inductive.
  • The decoupling capacitors, which become a bandpass filter as they also go inductive beyond their self-resonant frequency.
  • Any on-chip capacitors and parasitic package capacitance, not large enough to supply power at lower frequencies but able to stabilize delivery as frequency increases.

Minimizing voltage ripple and preventing the “rogue wave” resonance calls for flat impedance from those three sources over a range of frequencies.

The discussion continues with a look at the pitfalls of lumped-parameter EM simulations, then wraps up with an in-depth FPGA placement case study. “The simulations are only as good as the models,” says Keysight’s Heidi Barnes, SI/PI Application Engineer. Keysight helps vet and optimize capacitor models used in its PathWave ADS PIPro EM simulation tool – for example, models with capacitor package mounting inductance removed improve results. The EM field solver in PIPro generates an S-parameter model, including all components and parasitic effects, enabling board-level EM simulation matching real-world measurements.

Going back to the power source with board-level EM simulation

Another webinar in this series looks at one specific type of design: switched-mode power supplies (SMPS). Switching magnetics reduces size and improves efficiency but throws off noise and EMI as part of the process. Power supplies also fall under a wide range of EMI compliance specifications in different geographic markets and application segments. Designs again often fall victim to expensive late-stage test failures and respins, especially when moving from one market where testing passed to another market with a different profile.

Noise correlates to the high switching speeds and currents, or high di/dt in industry terms. Square-wave switching waveforms also throw off strong harmonics at even higher frequencies, up into RF ranges. Wide band gap (WBG) transistor technology, such as GaN or SiC, is also changing the picture. These technologies lower impedance and enable higher switching speeds. But, parasitic effects once buried by more dominant terms now rise to the surface.

“The pre-layout schematic simulation using Spice gives you a best-case result,” according to Steven Lee, Product Manager for Keysight PathWave Power Electronics. That can trap SMPS engineers in a complex test-respin cycle where differential noise, common mode noise, resonance and harmonic spikes are hard to predict and mitigate. Adding EMI filters can have unexpected effects as capacitors and board parasitics reveal their impedance characteristics.

A more effective approach for better EMI results is post-layout simulation and layout adjustments, introducing minimal EMI filtering. Using Keysight PathWave ADS PEPro brings layout-based design and board-level EM simulation technology optimized for power electronics, with similar field solvers for parasitic extraction. Steven walks through a demo of PEPro during the webinar.

Analyzing EMI compliance quickly 

A big workflow improvement is the EMI compliance overlays in PEPro. Instead of manually scanning and comparing EMI plots to specifications, pre-loaded compliance profiles including FCC Class A and B, CISPR 22 Class A and B, and CISPR 25 Class 1 through 5 can drop over simulation results with a couple of clicks.

Tightening the loop between developing higher fidelity EM models, making board layout adjustments accounting for parasitics and impedance behavior over frequency, and visualizing EMI compliance virtually before moving to physical test are big breakthroughs.

“You should be board-level EM simulating”

The main takeaway from this Keysight webinar series is power integrity and power electronics teams should be simulating to know more about their designs sooner. If teams had prior experience simulating with less accurate models and lumped parameters, it’s time to bring in better board-level EM simulation tools that can help shift-left virtual testing, leaving the late respin drama behind.

 

Webinars available on-demand now:

Optimizing Capacitor Selection and Placement for Power Integrity

Reduce EMI in Switched-Mode Power Supply Design

 

Future live events:

Both Heidi and Steven have new, live webinars coming with more thoughts on PI and EMI in the coming months – watch the main Keysight Webinars page for these and other live events.

Also Read

Shift left gets a modulated signal makeover

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Faster Time to RTL Simulation Using Incremental Build Flows

Faster Time to RTL Simulation Using Incremental Build Flows
by Daniel Payne on 01-31-2022 at 10:00 am
Categories: EDA, Siemens EDA

lump sum build min

I’ve been following Neil Johnson on Twitter and LinkedIn for several years now, as he has written and shared so much about the IC design and verification process, both as a consultant and working at EDA vendors. His recent white paper for Siemens EDA caught my eye, so I took the time to read through the 10 page document to learn more about the build flow choices now available to SoC teams.

Modern RTL languages most be compiled before they are ready to simulate, so turnaround time is always important. For engineering teams using functional simulation from Siemens EDA, they use the Questa simulator, and there are a few ways to approach build flows.

Lump Sum Build Flow

The simplest build flow has all of your input files (modules, packages, Testbench, DUT) compiled into a single library.

Lump Sum Build

This approach works efficiently for design complexity up to the sub-system level, and teams with a handful of engineers can handle any dependency issues. Typical build times are on the order of seconds, so it’s a good method.

Partitioned Compile

If your SoC team uses much design IP integration and testbench layering, then consider using the partitioned compile, where libraries are compiled separately and then gathered into a single simulation input.

Partitioned Compile

As your sub-systems grow larger in size, then compile times becomes faster by moving from the lump sum to a partitioned compile.

Parallel Compile

By partitioning your library and using more cores in parallel, then build times are further reduced, so it’s the classic tradeoff of number of EDA licenses versus time.

Pre-optimized Design Units (PDU)

Parts of an SoC hierarchy can be compiled independently into PDUs, then used as input to simulation. These PDUs are areas of the design that are rarely changing, so this avoids having to re-compile a stable design area. With this build approach you are only compiling the areas of code where changes have been made.

Pre-optimized Design Units (PDU)

Elaboration Flow

Elaboration is where modules are bound to module instances, model hierarchy is built, parameter values are computed, hierarchical names get resolved, and nets are connected. With Questa you create an elaboration file on the first test run then just re-use that file in the following runs.

Elaboration Flow

Command Line Front-end

Questa users have the Qrun tool to compile their designs, so here’s how it works for each of the build flow choices.

Lump Sum Build

Specify your testbench files and design files, then qrun will compile, optimize and simulate.

qrun -f testbench_files.f -f design_files.f

Partitioned Compile

To separate testbench and design files in the partitioned compile build flow, use qrun with this syntax:

qrun -makelib testbench_library -f testbench_files.f -end \
     -makelib design_library -f design_files.f -end

Parallel Compile

Compiling in parallel across multiple cores with Qrun looks just like the partitioned compile with one extra option:

qrun -makelib testbench_library -f testbench_files.f -end \
     -makelib design_library -f design_files.f -end \
     -parallel

Pre-optimized Design Units (PDUs)

Using Qrun for the PDU build flow adds the makepdu option:

qrun -makelib testbench_library -f testbench_files.f -end \
     -makelib design_library -f design_files.f -end \
     -makepdu design_top design_library.top -L design_library -end \
     -parallel

Elaboration Flow

The first time through the elaboration flow creates an elaboration file, then subsequent runs reuse the elaboration file:

qrun -makelib testbench_library -f testbench_files.f -end \
     -makelib design_library -f design_files.f -end \
     -makepdu design_top design_library.top -L design_library -end \
     -parallel \
     -elab elaboration.output -do “quit”

qrun -load_elab elaboration.output -do “run -all; quit”

Summary

Build flows are an important part of what SoC teams do in getting a design completed and verified in the shortest time possible. With Questa there are multiple build flows to choose from, depending on the complexity and composition of your project. The Qrun command line tool supports each build flow choice with a simple syntax, and it’s even smart enough to incrementally compile only the files that have changed or when dependencies change.

Read the complete 10 page White Paper online here.

Related Blogs

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Breker Attacks System Coherency Verification

Breker Attacks System Coherency Verification
by Bernard Murphy on 01-31-2022 at 6:00 am
Categories: Breker Verification Systems, EDA

System Coherency min

The great thing about architectural solutions to increasing throughput is that they offer big improvements. Multiple CPUs on a chip with (partially) shared cache hierarchies are now commonplace in server processors for this reason. But that big gain comes with significant added complexity in verifying correct behavior. In a shared memory model, the value stored in a logical memory address appears not only in main (DRAM) memory but also potentially in multiple on-chip caches and even possibly in buffers in the coherency fabric. Which raises a consistency issue – for a given logical memory address these should all contain the same value under all circumstances, but do they? Breker attacks this coherency verification problem through their test synthesis technology, looking at full system coherency in heterogenous systems.

The challenges in coherency

The logical memory view can become inconsistent when two or more processors are working with their own local copy of a value at a shared address and one updates its local value, unknown to the other. Chaos ensues as CPUs each work with their own view of reality. The coherent fabric itself has structure supporting data in-flight, such as write-back buffers. Coherency verification must also deal with these. And then of course peripherals can write directly to main memory through DMA, unknown to internal caches.

Clearly some mechanism is needed to keep shared values in sync when required. But it must be light-handed. Synchronization comes with a latency penalty which can significantly reduce the performance advantage of caching, unless used only when absolutely needed. The latency problem is compounded further when you consider shared memory multi-socket processor boards interconnected via CXL. Adding more complexity to solutions.

Clever techniques are used to spy on cache contents and changes, to determine when a synchronization update is necessary. These include snooping and directory-based coherency systems, which tag cache addresses (more exactly cache lines) as being clean (coherent) or invalid, with a variety of refinements. These methods must walk a fine line between minimizing net performance impact while ensuring no possible escapes. Escapes being possible cases in which a non-coherent condition can survive.

The Breker System Coherency TrekApp

To check that the design does not cross that fine line, verification engineers must independently construct tests which they believe will cover all possible cases. Cache, fabric and IO coherence across all control variations (power, interrupt, clocking, etc) through which the design might cycle. That’s where the Breker Trek System Coherency app comes in.

Adnan Hamid, founder of Breker, started many years ago in coherency verification at AMD. The ideas he developed there around cache coherence verification and system verification methods in general he built into Breker. The coherence solution expanded over time to also include fabric and IO coherence and interaction with power switching, etc. After proving this capability out with a few lead customers, Breker announced the product at the recent DAC 2021 in San Francisco.

Adnan offers an insight: to know how to achieve meaningful coherence verification, you first must know how to measure coverage. As with any system-level coverage objective, RTL coverage metrics aren’t helpful. More useful is coverage first of the coherency manager state machine per cache, with variants in cache values and address stride, then a similar coverage for cross-cache interactions, then coverage across a synthetic set of software-based torture tests, crossed with power and other transitions, running on an emulator. The System Coherency TrekApp supports all of this.

What about escapes?

Talk to anyone working with coherent designs and they’ll all tell you they find coherency problems post-silicon. Getting close to that fine line without crossing it is really quite difficult. After all you’re trying in pre-silicon verification to model a vast state space with, in comparison, a tiny set of tests, even if you run tens of thousands of tests. Given that exhaustive testing is not even remotely possible, the trick is to find the best practical set of tests to run. Since this will be unavoidably incomplete, the System Coherency TrekApp extends even to post-silicon, helping to diagnose silicon failures. Perhaps a power transition in the middle of synchronization. Or an interrupt unfortunately timed against a tag update. In Adnan’s view, this post-silicon learning will help refine the pre-silicon verification coverage plan. To reduce if not eliminate post-silicon escapes.

Interesting stuff, incidentally supported for both Arm-based and RISC-V-based systems, recenly endorsed in a press release with Nuclei System Technology. You can learn more HERE.

Also Read:

WEBINAR: Adnan on Challenges in Security Verification

Breker Tips a Hat to Formal Graphs in PSS Security Verification

Verification, RISC-V and Extensibility

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KLAC- Great quarter and year – March Q is turning point of supply chain problem

KLAC- Great quarter and year – March Q is turning point of supply chain problem
by Robert Maire on 01-30-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
1 Comment

KLAC Foundry Logic

-KLAC – great QTR & calendar year but supply chain impacted
-Management feels supply chain to improve after March Q
-Demand remains strong, driven by foundry/logic
-Process management is next best place in industry after litho

Great end to calendar year

KLA reported revenues of $2.53B with non GAAP EPS of $5.59 nicely exceeding street expectation of $2.33B and EPS of $5.45. Guidance was muted due to supply chain issues at $2.2B +-$100M and Non GAAP EPS of $4.80+-$0.45. This is versus expectations of $2.37B and $5.50 in EPS

March is worst of supply chain impact

Management was clear and adamant that March would be the worst of the supply chain impact and that things would improve going forward for the remainder of the year . The company estimated that the March quarter would see an 8-10% negative impact on revenue. Importantly that revenue would likely ship in June creating the uptick.

This is certainly in contrast to Lam that didn’t identify a clear end to their issues and seemed to be more open ended as to how long there would be supply chain issues. While we are certainly not happy to see the issues finally crop up we feel better that the impact seems to be for one quarter with most all the revenue just slipping into the next quarter.

In KLA’s case, there is essentially zero likelihood that KLA will lose any revenue to competitors as they supply very unique products and are certainly less interchangeable as compared to dep and etch products.

Process control continues to outperform overall WFE

Process control tools such as those made by KLA continue to grow faster than the overall market as rapidly increasing process complexity requires more process control at higher costs as we continue to push the limits of physics.

Process control follows litho sales and complexity and is somewhat of a shadow proxy for ASML’s sales and growth. Wafer and especially reticle inspection are driven by the increasing lithographic challenges. We see this out performance in the mid to high single digits continuing in 2022.

Being a play on foundry helps in the current environment

While Lam remains the poster child for memory manufacturing so too does KLA remain the poster child for foundry/logic which was 79% of business.
The huge bump up in spend by TSMC coupled with what will likely be a large bump up by Intel as well, will clearly benefit KLA as those are two key and significant customers.

While memory spend remains solid it is also conservative as the industry wants to have supply and demand remain in balance. The challenges in 3D NAND are clearly one of the big drivers of process control in the memory space.

Backlog is Beautiful

KLA has historically had good backlog which enables them to dial in and control their numbers better than most in the industry. We know that some KLA products are quoting deliveries of over a year and a years backlog in products at this point given such strong demand is not out of the norm.

While KLA’s backlog may not exactly be like ASML’s its not far off. KLA obviously has the added benefit of superb gross margins. The current super strong demand environment coupled with the constrained supply chain will keep backlog high and likely growing. Although the supply chains issues may get better after the March quarter , we think backlog will remain high due to current demand which will not diminish.

The Stock

Investors will obviously not like the weak guide for the March quarter but the negative impact on the stock should be more muted as the worst of it will be March and things will pick up after that with the revenue just slipping into June.
Obviously the overall market sentiment and volatility is quite horrible so the limitation of the impact to a single quarter may not matter as investors are just in a general supply chain panic.

We could see some collateral help from Apple talking about supply chain issues improving which would lend credence to KLA’s view of March as the low point with the rest of the year up from there.

The stock has lost quite a bit for such a high quality name which makes us feel more attracted to it especially if it were to trade off too sharply.
Unfortunately the recent volatility continues to reduce predictability and makes investors wary of even high quality stories.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
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Also Read:

LRCX- Supply Chain Catches up with Lam- Gets worse before better- Demand solid

ASML Too Much Demand Plus Intel and High NA

Forty Four Billion Reasons Why TSMC Remains Dominant

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Apple and OnStar: Privacy vs. Emergency Response

Apple and OnStar: Privacy vs. Emergency Response
by Roger C. Lanctot on 01-30-2022 at 8:00 am
Categories: Automotive

Apple and OnStar Privacy vs. Emergency Response

In the season 6 premiere of Showtime’s “Billions,”, financier Michael Prince and his lieutenant are remotely monitoring Wags’ heart rate thanks to an Oura-like smart ring as he works out on a Peloton stationary bike. The remote observers conclude Wags is having a heart attack and dispatch emergency medical technicians to his aid without his knowledge.

This kind of experience may soon become more common as a growing range of devices are enabled with connectivity and sensors to identify or anticipate emergencies ranging from heart attacks to car crashes. In fact, emergency response is becoming a theme in television advertising most recently from Apple and General Motors’ OnStar.

Apple: https://9to5mac.com/2022/01/01/apple-watch-emergency-sos-911/

OnStar: https://www.youtube.com/watch?v=jhVqHLqK4M4

The issue of automatic crash detection is front of mind in the U.S. thanks to the universal shutoff of 3G wireless service which robbed a few million cars in the U.S. of their automatic crash notification functions. This is not an issue in Europe (yet) where so-called eCall has been a mandatory automotive feature since 2018. (Europe is currently facing its own 2G/3G shutoff challenges.)

The key difference between the experience of an Apple Watch SOS user or an OnStar subscriber and the scene depicted in “Billions” is that Apple and OnStar customers must knowingly activate and/or opt-into use of the service.  Wags in “Billions,” on the other hand, is a victim of a privacy violation.

The point is, emergency response is swiftly becoming a high profile connected service. RapidSOS, a leading platform provider in this space, already has 400M SOS-equipped devices on its network representing 65 companies including SiriusXM, TrueMotion, Farmers’ Insurance, Lemonade, Apple, and Uber.

The challenge is to get the story right – helping consumers understand the value proposition and how and why it works the way it does. The two commercials in question get some things right – but the OnStar commercial gets a lot wrong.

The Apple Watch commercial gets the SOS function right because it shows that the smartwatch will dial 911 directly (via a Bluetooth connection to an iPhone or Wi-Fi) if the user doesn’t cancel the call. The OnStar commercial gets this message wrong because it portrays the OnStar operator speaking directly with the first responder on the scene.

In reality, the OnStar operator contacts the relevant emergency call center (public service access point) and provides information delivered from the car and the customer. It is also not unusual for the OnStar operator to remain on the line to continue to exchange information between the customer and the PSAP. But the call center operator usually handles the communication to the first responders on their way to or at the scene.

Inadvertently, OnStar’s commercial – which was taken off the air almost as quickly as it appeared – does demonstrate the value of communicating valuable, if not essential information directly to first responders at an emergency event. Most basic ACN systems deliver latitude and longitude information, vehicle make and model and color, some crash severity info, vehicle VIN, and time of the incident.

Time is important, because the whole point of automatic crash notification in cars is to reduce the response time by immediately determining that an event has occurred. According to published analysis of emergency response calls, each minute of response time, represents a 7% reduction in mortality (mainly for non-automotive scenarios).

This is why RapidSOS has developed a massive middleware integration infrastructure for quickly processing information from incidents and sending it on to the PSAP. RapidSOS has been successful in delivering on this value proposition and increasingly dominates the emergency response market.

RapidSOS is at the forefront of a transformation of emergency response systems. The industry is poised to revolutionize this application as the technology finds its way into smartwatches, smartphones, cars, home security systems, and any number of other personal and mobile devices – like smart rings.

The risk to the automotive industry, though, is that the introduction of crash detection into smartphones – it is already available in Google’s Pixel phones – may lead consumers to believe they don’t need it in their cars. Consumers may come to regard smartphone-based 911 in the U.S. as “good enough” ACN. What it will really amount to is ACN-lite – tastes great, less useful. (Europe has yet to allow smartphone-based ACN capability.)

First responders already need and want more information about a crash as they arrive at the scene. What is missing is the integration of off-board data such as:

  • Vehicle ownership
  • Whether the car is stolen
  • Fire and extraction protocols – if the car is an EV
  • Customer towing preference
  • Emergency contacts or next of kin
  • Existing medical conditions of driver, passengers

Having all of this information is especially important if the driver of the vehicle is unconscious. One company has emerged to integrate this essential off-board data: Roadside Telematics.

Apple and Google cannot deliver this kind of information. Properly configured ACN systems equipped with RapidSOS compatibility and linked to technology from Roadside Telematics will be able to deliver on the last-mile proposition of getting vital information to first responders at the scenes of crashes.

RapidSOS estimates that upwards of 150,000 lives could be saved for all sorts of incidents with more timely processing of event information. This is why the company integrates with a wide range of applications currently in use at emergency call centers. Getting the last mile information correct – using Roadside Telematics – will contribute to these life-saving implementations.

For organizations with devices capable of generating emergency calls – such as Apple and OnStar – it is now more important than ever to get the messaging right. Consumers need to be educated that this is one circumstance where sharing personal information may be a life-saving proposition.

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RedCap Will Accelerate 5G for IoT

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LRCX- Supply Chain Catches up with Lam- Gets worse before better- Demand solid

LRCX- Supply Chain Catches up with Lam- Gets worse before better- Demand solid
by Robert Maire on 01-30-2022 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services

Lam Research

-Supply chain issues finally catch up to Lam- Ongoing issue
-Problem from one main supplier to spread to more
-Causes low December Quarter and soft guide for March
-Quarters could be lumpy due to differed & revenue push outs

Lam Stews over supply Chain Issues

It sucks when you have all the demand in the world but can’t build enough product. Its even worse when the problem is getting worse before it gets better. Lam, which had previously dodged supply chain issues when Applied Materials got hit, now has its own issues.

The company reported revenues of $4.23B below street estimates of $4.4B and below conservative mid point of guidance. Earnings were more of less in line at $8.53 versus street of $8.52 and were actually light if you back out a one time investment gain. Guidance is not that great at all, at $4.25B +-$300M with EPS of $7.45 +- $0.75. This is way, way short of current estimates of $4.5B and $8.72 in EPS.

Sloppy quarters due to revenue movement

Lam suggested that the March quarter could see $500M in revenue deferrals as revenue slips out of the quarter due to supply chain issues. Product can be shipped without missing subsystems to be reunited at the customer installation site. This is similar to what we had heard from ASML who has a way more complex tool.

Situation gets worse before better

Lam suggested on the call that the issue was primarily one key supplier in the last two weeks of the quarter but that the problem was broadening to other sub suppliers.

We think the problem has likely been around for a bit longer than the last two weeks of the quarter as it was described as being at least three areas of 1) Labor, 2) Freight and 3) Supply Chain.

Perhaps its that while Lam may have hit prior issues and dealt with them, the severity of the issue probably became insurmountable.
One of the key questions that will weigh on the stock is how much worse it gets and for how long

Demand remains strong

Demand exceeds supply…..At this point anything beyond that doesn’t matter. Obviously the supply issue in the semiconductor industry remains with us and all manufacturers and would be manufacturers , like China, continue to place orders and wait in line.

Focus is entirely on fixing the supply chain

Management sounds like it is laser focused on fixing the supply chains issues. Most likely resorting to daily beatings of sub suppliers, looking for alternate suppliers and scouring the globe for needed parts inventory.
God help the sub supplier who cant ‘fix their issues or messes up.

Lam also had the unfortunate timing to be moving a lot of production to Malaysia in the middle of this supply chain crisis. We understand its likely not possible to delay the transition but it makes things just that much worse.
Margins are negatively impacted as you have the costs associated with Malaysia before you get a full ramp of production.

Concerns about market share loss

We have pointed out a number of times that we remain concerned about share loss when tool makers can’t fulfill orders. Desperate chip makers, hungry for tools might be tempted to order competitors tools that are not as good or more expensive.

Even worse, uncertainty of delivery could cause customers to double or triple order from Lam, Applied and TEL etc in hopes of taking the first tool that gets delivered.

While this is not not an issue on critical applications like “drill and pray” deep etches for NAND where Lam commands the market, it could become a problem on more generic , easy applications that are more competitive.

The Stock is gonna get trashed

LRCX was already off 5% in the after market….even though that seems like nothing in light of the recent overall market volatility. We think the stock could get very badly hit as the market is not in a positive mood and any bad news such as what Lam delivered will likely have an overreaction.

The reality is that the semiconductor equipment stocks had been overbought and have been correcting for a while anyway….this will certainly speed up the correction.

We don’t see any reason to go out and buy the stock any time soon as the uncertainty is getting worse and will keep investors waiting. We also don’t see a price at which we would be a buyer given the current momentum and tone.

As far as collateral damage goes, the other tools makers like AMAT and KLAC will likely see some sympathetic weakness in their stock. We don’t expect AMAT to buck the supply chain issue trend that they have already reported. Its more likely it has worsened.

KLAC is likely most resistant to supply chain issues but is certainly far from immune. TEL in Japan may be more secure as most of their supply chain is from inside Japan and is much tighter relationships exist in Japan.

Our two conclusions are that supply chain issues are still getting worse in some cases and are clearly longer than expected and two, that this years performance may have upside limited in growth due to these supply issues more than previously anticipated.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also read:

ASML Too Much Demand Plus Intel and High NA

Forty Four Billion Reasons Why TSMC Remains Dominant“Too Big To Fail Two” – Could chip failure take down tech & entire economy?

TSMC Earnings – The Handoff from Mobile to HPC

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Tesla: Kick-ass Radio in an EV

Tesla: Kick-ass Radio in an EV
by Roger C. Lanctot on 01-29-2022 at 6:00 am
Categories: Automotive

Tesla Kick ass Radio in an EV

It seems that all we hear about over-the-air radio broadcasts in electric vehicles is that AM is going away due to interference and FM is irrelevant due to streaming apps. Tesla has very affirmatively upended this conventional wisdom with an over-the-air update that adds Xperi’s DTS AutoStage to most Tesla’s.

This free software update, just the latest in a long string, brings metadata for station identification and artwork to the in-dash radio experience. It also reveals a lot about how in-car radio is evolving.

First of all, as is illustrated in the image (above), some stations may not have metadata associated with their displayed icon. In Tesla’s case this is most likely due to the strong radio reception in Tesla vehicles exceeding the anticipated coverage radius defined by DTS AutoStage. This is easily corrected, but a tip of the hat to Tesla’s engineers.

The display of 18 station logos also raises real questions as to how drivers will interact with the radio. The radio dial was abandoned long ago. Will we select stations by voice or touch? How will we search?

The bigger issue is that Tesla has brought this experience to dashboards with an over-the-air update with little or no fanfare. Tesla is expected to add a Radio Traffic Alert function via over the air update and will be adding Dolby Atmos audio enhancements via over-the-air update.

This is in addition to adding Emergency Safety Solution’s Hazard Enhanced Location Protocol broadcast (H.E.L.P.) functionality via over-the air update. HELP is designed to alert oncoming cars when a Tesla – or similarly equipped vehicle – is disabled along the side of the road due to a crash or breakdown.

And this, too, is in addition to Full Self-Driving having been switched on for thousands, if not hundreds of thousands, of Tesla drivers in the past few weeks. Tesla is calling the tune in the automotive industry from the standpoint of both innovation and speed to market.

We always knew that over-the-air updates would help preserve the value of so-equipped vehicles, such as Teslas. What we didn’t expect was that Tesla would become the go-to partner for industry startups seeking the fastest route to market.

Where the average auto maker offers a 2-3 year implementation plan to new market entrants. Tesla offers the prospect of instant deployment along with the ability to assess consumer response also almost instantly.

The preservation and enhancement of vehicle value has been proven as used Teslas are routinely resold at the same prices at which they were acquired. But serving as a platform for innovation means every dreamer with a new idea for safer driving or in-vehicle content consumption is making Tesla a first stop.

It so happens that in the process, radio has benefited handsomely with new content and interfaces. But, actually, if you want the state of the art in a connected radio experience you probably still have to look to Mercedes-Benz or Hyundai. Tesla’s DTS AutoState implementation uses only static station data and has not yet implemented artist and track information – already deployed in select Mercedes-Benz and Hyundai vehicles. But if you want Dolby, Tesla will be the place to look and listen.

Also Read:

Regulators Wrestle with ‘Explainability’​

Functional Safety for Automotive IP

Don’t Lie to Me

Podcast EP59: A brief history of semiconductors and EDA with Rich Goldman

Podcast EP59: A brief history of semiconductors and EDA with Rich Goldman
by Daniel Nenni on 01-28-2022 at 10:00 am
4 Comments

Dan is joined by good friend and fellow boater Rich Goldman. Rich has a storied career in EDA that began at TI with Morris Chang and Wally Rhines, continued through a long career at Synopsys and included a book collaboration with Neil Armstrong, Stephen Hawking and Brian May (the lead guitarist for Queen),

Dan and Rich cover a lot of ground across both semiconductors and EDA, the innovation, the trends and what it means.

Book reference: Starmus

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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WEBINAR: How to add a NIST-Certified Random Number Generator to any IoT device?

WEBINAR: How to add a NIST-Certified Random Number Generator to any IoT device?
by Daniel Nenni on 01-28-2022 at 6:00 am
Categories: Events, Intrinsic ID, IP, Security

Intrinsic ID Webinar Blog

In the first half of 2021, the number of attacks on IoT devices more than doubled to 1.5 billion attacks in just six months. These attacks target some typical weaknesses, such as the use of weak passwords, lack of regular patches and updates, insecure interfaces, and insufficient data protection. However, researchers from Bishop Fox recently identified a new critical vulnerability of IoT devices that might not be so obvious to many of us. Their study showed that hardware random number generators (RNGs) used in billions of IoT devices fail to provide sufficient entropy. Insufficient entropy causes predictable instead of random numbers, which severely compromises the foundation of many cryptographic algorithms. Secret keys will lose their strength, leading to broken encryption.

REPLAY is HERE

So a new approach for generating random numbers is needed. This webinar shows how large amounts of entropy can be extracted from unpredictable SRAM behavior. Using this method only requires a software installation, meaning the security systems of billions of devices can be patched without the need to make hardware changes, even in devices that have already been deployed.

What will you learn?

This webinar shows how you can utilize Zign™ RNG, the Intrinsic ID embedded software IP for random number generation, to add a NIST-certified random number generator to any device, simply using software. The webinar will explain to you:

  • Why having a trusted RNG is important for any IoT device
  • How entropy can be harvested from unpredictable SRAM behavior
  • How this entropy is used to create a strong RNG
  • Which steps have been taken to turn Zign RNG into a NIST-certified RNG

Who should attend?

This webinar is must-see for anyone responsible for product design and/or embedded security of IoT chips and devices. Whether you are a semiconductor professional or an IoT device maker, this webinar will show you how you add a trusted source of strong entropy to your product without making any changes to your hardware.

About Zign RNG

Zign RNG is an embedded software IP solution from Intrinsic ID that that leverages the unpredictable behavior of existing SRAM to generate entropy in IoT devices. This approach enables anyone to add a random number generator to their products without the need for hardware modifications. The Zign RNG product is compliant with the NIST SP 800-90 standard, and it is the only hardware entropy source that does not need to be loaded at silicon fabrication. It can be installed later in the supply chain, and even retrofitted on already-deployed devices. This enables a never-before-possible “brownfield” deployment of a cryptographically secure, NIST-certified RNG.

About the Speaker: Nicolas Moro

Nicolas Moro holds a PhD in Computer Science from Université Pierre et Marie Curie in Paris. After receiving his PhD, he worked in varying R&D roles at NXP and Imec. Two years ago Nicolas joined Intrinsic ID, where he works as a Senior Embedded Software Engineer. He has extensive experience in embedded systems security and is the author of several research papers about fault injection attacks and software countermeasures.

REPLAY is HERE

About Intrinsic-ID

Intrinsic ID is the world’s leading provider of security IP for embedded systems based on PUF technology. The technology provides an additional level of hardware security utilizing the inherent uniqueness in each and every silicon chip. The IP can be delivered in hardware or software and can be applied easily to almost any chip – from tiny microcontrollers to high-performance FPGAs – and at any stage of a product’s lifecycle. It is used as a hardware root of trust to protect sensitive military and government data and systems, validate payment systems, secure connectivity, and authenticate sensors. Intrinsic ID security has been deployed and proven in hundreds of millions of devices certified by EMVCo, Visa, CC EAL6+, PSA, ioXt, and governments across the globe.

Also Read:

Enlisting Entropy to Generate Secure SoC Root Keys
Using PUFs for Random Number Generation
Quantum Computing and Threats to Secure Communication