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LIVE WEBINAR – The ROI of User Experience Design: Increase Sales and Minimize Costs

LIVE WEBINAR – The ROI of User Experience Design: Increase Sales and Minimize Costs
by Daniel Nenni on 04-11-2023 at 10:00 am
Categories: Events, Planorama Design, Semiconductor Services

planorama webinar blog graphic sm

The semiconductor industry has seen a significant shift towards vertical integration of products, expanding from chips to generalized or purpose-built integrated solutions. As software becomes an increasingly critical component of these solutions, leveraging modern software development processes with User Experience (UX) design are integral to successful launches.

It should be no surprise that intuitive, simple-to-use software drives sales, customer satisfaction and retention, and brand loyalty.  However, beyond these benefits, User Experience design accelerates your time-to-market while reducing your internal product development costs. In light of this, we organized a webinar to explore the role of UX design in software-hardware solutions, with its influence spanning from product development to sales wins.

With an intended audience of sales and software engineering managers responsible for product development, this live webinar will discuss how the User Experience design practice achieves the aforementioned business goals simultaneously.  Participants will learn how UX is practically implemented in IoT and integrated solution project teams, review real world case studies, and discuss questions in a live Q&A.

The webinar, “The ROI of User Experience Design: Increase Sales and Minimize Costs,” will be hosted by Matt Genovese, founder and CEO of Planorama Design, himself a seasoned engineer whose career spans semiconductors and software product development.  Don’t miss out on this opportunity to learn from an industry expert and take your product development process to the next level.  Watch the replay.

Abstract:
In today’s competitive landscape for IoT, edge, and cloud solutions, User Experience (UX) design has become more crucial than ever in achieving customer and business goals. During this live webinar, we will explore how UX design affects everything from sales, customer retention, time-to-market, to internal support and development costs. We’ll delve into key principles of user-centered design, and discuss how they drive more complete product and purpose-built solutions that differentiate you from competitors, and accelerate your customers through engineering to ramp more quickly into production.

Speaker:
Matt founded Planorama Design, a user experience design professional services company to design complex, technical software and systems that are simple and intuitive to use while reducing internal development and support costs. Staffed with seasoned engineers and UX designers, the company is headquartered in Austin, Texas, USA.

Watch the replay

Also Read:

CEO Interview: Matt Genovese of Planorama Design

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WEBINAR: Design Cost Reduction – How to track and predict server resources for complex chip design project?

WEBINAR: Design Cost Reduction – How to track and predict server resources for complex chip design project?
by Daniel Nenni on 04-11-2023 at 6:00 am
Categories: Defacto Technologies, EDA, Events, Innova

picture innova

During the design of complex chips, cost reduction is becoming a real challenge for small, medium and large companies.  Resource management is a key to contain design cost.

The chip design market is expecting automated solutions to help in the resource prediction, planning and analysis. AI-based technologies are promising for emerging resource management solutions.

It is known that the trend during the design of modern chips is to more and more rely on cloud-based computing servers, but the key question is: Is it timely predictable to switch from on-premise to cloud-based servers?

INNOVA is providing a clear ML-based answer to this question. The INNOVA tool called PDM (for Project Design Manager) is making easy the three following key steps:

  1. Model training
  2. Model selection
  3. Time prediction of server resources

By including precise CPU, memory and disk information.

Worth noting that INNOVA’s PDM provides the infrastructure to track the usage of different resources (EDA tools, servers, engineering resources, libraries, …).  It can be securely plugged-in to any existing IT environment and interoperates with standard project, license, and server management tools.

Once the tool is installed, executing resource prediction is straightforward including the selection of the ML-model which is the most suitable according to the user and company context.  Report generation including comparison between real data and predicted data are also made easy even for non-AI experts.

Figure: Predicted vs. Real Data

No need to train the tool for months. With PDM for a 3-month prediction, in less than 24 hours, first training results are generated as well as the correlation reports between real and predicted data.

To make design managers, CAD and procurement teams comfortable when using this kind of technologies, the tool provides several APIs such as a web-based graphical interface, and high level scripting APIs in Python or using GraphQL. Reports generation and alarm creation are also made easy.

A dedicated Webinar entitled “AI-Based Resource Tracking & Prediction of Computing Servers For Chip Design Projects”. See the replay HERE.

About INNOVA:

INNOVA Advanced Technologies has been founded in 2020 by seasoned from the semiconductor industry. Its solution is intended for designers as well as design managers of complex and multi-domain projects, ranging from microelectronics to computer science. It helps them to manage projects and resources in one unique place.

For more information about INNOVA Advanced Technologies you can visit their website here: https://www.innova-advancedtech.com/

Also Read:

Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy

Using IP-XACT, RTL and UPF for Efficient SoC Design

Working with the Unified Power Format

Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG

Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG
by Daniel Nenni on 04-10-2023 at 2:00 pm

This is a special edition of our podcast series. At the recent Synopsys SNUG User Group, SemiWiki staff writer Kalar Rajendiran got the opportunity to conduct an informal interview with Aart de Geus, Chairman and CEO of Synopsys.

What follows are some of Aart’s thoughts on the deployment of AI across the semiconductor ecosystem. Technology and business implications are discussed as well as the impact of multi-die design on the overall landscape.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Multiphysics Analysis from Chip to System

Multiphysics Analysis from Chip to System
by akanksha soni on 04-10-2023 at 10:00 am
Categories: Ansys, Inc., Chiplet, EDA

Image 1 2

Multiphysics simulation is the process of computational methods to model and analyze a system to understand its response to different physical interactions like heat transfer, electromagnetic fields, and mechanical structures. Using this technique, designers can generate physics-based models and analyze the behavior of the system as a whole.

Multiphysics phenomena play a key role when designing any electronic device. In the real world, most devices that we use in our day-to-day life consist of electronics. These devices consist of chips, wires, antennas, casing, and many other components responsible for the final operation and execution of the product. The physical phenomena happen not just within an electronic device but also impact nearby devices. Therefore, it’s important to consider the effects of physical interactions from chip to system and the surrounding environment.

Alternative methods and their shortcomings

Understanding the electrical behavior of any device or system isn’t enough. Designers also need to consider the Multiphysics aspects like thermal, mechanical stress/warpage, and electromagnetic effects. Designers may use different ways to understand the Multiphysics behavior of the system at different levels.

Engineers can simulate each physical phenomenon separately and integrate the results to understand the cumulative behavior. This approach is time-consuming and prone to errors, and does not allow for a comprehensive analysis of the interactions between different physical fields. For example, temperature variations in a multi-die IC package can induce Mechanical stress and mechanical can impact the electromagnetic behavior of the system. Everything is co-related; therefore, a comprehensive Multiphysics solution is required for simulating the physics of the entire system.

To achieve high performance and speed goals, chip designers are embracing multi-die systems like 2.5D/3D-IC architectures. The number of vectors to be simulated in these systems has reached millions. Conventional IC design tools cannot handle this explosion of data, so chip designers considered a limited set of data to analyze the Multiphysics behavior of the system. This approach might work if the system is not high-speed and not used in critical conditions, but it is definitely not applicable for today’s high-speed systems where reliability and robustness are the major requirements.

Ansys provides a complete comprehensive Multiphysics solution that can easily solve millions of vectors to thoroughly analyze the Multiphysics of the entire system- chip-package-system.

Advantages of Multiphysics Simulation from Chip to System

Comprehensive Multiphysics simulation is a powerful method that enables designers to accurately predict and optimize the behavior of complex systems at all levels, including chip, package, and system. Multiphysics simulation has many advantages but some of the most prominent advantages are:

  1. Enhanced Reliability: Comprehensive Multiphysics simulation methods analyze the physics of each complex component in the system and also consider the interactions between different physical domains. This technique provides more accurate results which ensure the reliability of the system. Ansys offers a wide range of Multiphysics solutions enabling designers to analyze the Multiphysics at all levels, chip, package, system, and surrounding environment.
  2. Improved Performance: Multiphysics solutions give insight into the different physics domains, their interactions, and their impact on the integrity of the system. By knowing the design’s response to the thermal and mechanical parameters along with electrical behavior, designers can take an informed decision and modify the design to achieve desired performance. In a 3D-IC package, Ansys 3D-IC solution provides a clear insight into the power delivery, temperature variations, and mechanical stress/warpage around chiplets and interposer, allowing designers to deliver higher performance.
  3. Design Flexibility: Designers can explore a wide range of design options and tradeoffs. It allows designers to take decisions based on yield, cost, and total design time. For example, in a 3D-IC package designers can choose the chiplets based on functionality, cost, and performance. Multiphysics simulation allows this flexibility without extra cost.
  4. Reduced cost: It allows designers to identify potential design issues early in the development process, reducing the need for physical prototypes and lowering development costs. Using simulation, you can also tradeoff between the BOM costs and expected performance.
  5. Reduced Power Consumption: A system consists of multiple parts and each part might have different power requirements. By Multiphysics simulation, the designers can estimate the power consumption in each part of the system and optimize the power delivery network.

Ansys offers powerful simulation capabilities that can help designers optimize their products’ performance, reliability, and efficiency, from chip to the system level. By using Multiphysics solutions by Ansys, designers can take informed design decisions while designing.

Learn more about Ansys Multiphysics Simulation tools here:

Ansys Redhawk-SC | IC Electrothermal Simulation Software

High-Tech: Innovation at the Speed of Light | Ansys White Paper

Also Read:

Checklist to Ensure Silicon Interposers Don’t Kill Your Design

HFSS Leads the Way with Exponential Innovation

DesignCon 2023 Panel Photonics future: the vision, the challenge, and the path to infinity & beyond!

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Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet

Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet
by Madhumita Sanyal on 04-10-2023 at 6:00 am
Categories: EDA, IP, Synopsys

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The increasing demands for massive amounts of data are driving high-performance computing (HPC) to advance the pace in the High-speed Ethernet world. This in turn, is increasing the levels of complexity when designing networking SoCs like switches, retimers, and pluggable modules. This growth is accelerating the need for the bandwidth hungry applications to transition from 400G to 800G and eventually to 1.6T Ethernet. In terms of SerDes data-rate, this translates to 56G to 112G to 224G per lane.

The Move from NRZ to PAM4 SerDes and the Importance of Digital Signal Processing Techniques

Before 56G SerDes, Non-Return-to-Zero (NRZ) signaling was prevalent. It encoded binary data as a series of high and low voltage levels, with no returning to zero voltage level in between. NRZ signaling is mostly implemented using analog circuitry since the processing latency is low, which is suitable for high-speed applications. However, as the data rates increased, the need for more advanced signal processing capabilities emerged. Digital circuits became more prevalent in SerDes designs in 56G to 112G to 224G. Digital signal processing (DSP) circuits enabled advanced signal processing, such as equalization, clock and data recovery (CDR), and adaptive equalization, which are critical in achieving reliable high-speed data transmission.

Furthermore, the demands for lower power consumption and smaller form factor also drove the adoption of digital SerDes circuits. Digital circuits consume less power and can be implemented using smaller transistors, making them suitable for high-density integration. Pulse Amplitude Modulation with four levels (PAM4) has become a popular signaling method for high-speed communication systems due to its ability to transmit more data per symbol and its higher energy efficiency. However, PAM4 signaling requires more complex signal processing techniques to mitigate the effects of signal degradation and noise, so that the transmitted signal is recovered reliably at the receiver end. In this article, we will discuss the various DSP techniques used in PAM4 SerDes.

Figure 1: PAM4 DSP for 112G and beyond

DSP techniques used in PAM4 SerDes

Equalization

Equalization is an essential function of the PAM4 SerDes DSP circuit. The equalization circuitry compensates for the signal degradation caused by channel impairments such as attenuation, dispersion, and crosstalk. PAM4 equalization can be implemented using various techniques such as:

  • Feedforward Equalization (FFE)
  • Decision-Feedback Equalization (DFE)
  • Adaptive Equalization

Feedforward Equalization (FFE) is a type of equalization that compensates for the signal degradation by amplifying or attenuating specific frequency components of the signal. FFE is implemented using a linear filter, which boosts or attenuates the high-frequency components of the signal. The FFE circuit uses an equalizer tap to adjust the filter coefficients. The number of taps determines the filter’s complexity and its ability to compensate for the channel impairments. FFE can compensate for channel impairments such as attenuation, dispersion, and crosstalk but is not effective in mitigating inter-symbol interference (ISI).

Decision-Feedback Equalization (DFE) is a more advanced form of equalization that compensates for the signal degradation caused by ISI. ISI is a phenomenon in which the signal’s energy from previous symbols interferes with the current symbol, causing distortion. DFE works by subtracting the estimated signal from the received signal to cancel out the ISI. The DFE circuit uses both feedforward and feedback taps to estimate and cancel out the ISI. The feedback taps compensate for the distortion caused by the previous symbol, and the feedforward taps compensate for the distortion caused by the current symbol. DFE can effectively mitigate ISI but requires more complex circuitry compared to FFE.

Adaptive Equalization is a technique that automatically adjusts the equalization coefficients based on the characteristics of the channel. It uses an adaptive algorithm that estimates the channel characteristics and updates the equalization coefficients to optimize the signal quality. The Adaptive Equalization circuit uses a training sequence to estimate the channel response and adjust the equalizer coefficients. Circuit can adapt to changing channel conditions and is effective in mitigating various channel impairments.

Clock and Data Recovery (CDR)

Clock and Data Recovery (CDR) is another essential function of the PAM4 SerDes DSP circuit. The CDR circuitry extracts the clock signal from the incoming data stream, which is used to synchronize the data at the receiver end. The clock extraction process is challenging in PAM4 because the signal has more transitions, making it difficult to distinguish the clock from the data. Various techniques such as Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) can be used for PAM4 CDR.

PLL is a technique that locks the oscillator frequency to the incoming signal’s frequency. The PLL measures the phase difference between the incoming signal and the oscillator and adjusts the oscillator frequency to match the incoming signal’s frequency. The PLL circuit uses a Voltage-Controlled Oscillator (VCO) and a Phase Frequency Detector (PFD) to generate the clock signal. PLL-based CDR is commonly used in PAM4 SerDes because it is more robust to noise and has better jitter performance compared to DLL-based CDR. DLL is a technique that measures the time difference between the incoming signal and the reference signal and adjusts the phase of the incoming signal to align with the reference signal. The DLL circuit uses a delay line and a Phase Detector (PD) to generate the clock signal. DLL-based CDR is less common in PAM4 SerDes because it is more susceptible to noise and has worse jitter performance compared to PLL-based CDR.

Advanced DSP techniques

Maximum Likelihood Sequence Detection (MLSD) are used to improve the signal quality and mitigate channel impairments in high-speed communication systems requiring very long reaches. MLSD is a digital signal processing technique that uses statistical models and probability theory to estimate the transmitted data sequence from the received signal. MLSD works by generating all possible data sequences and comparing them with the received signal to find the most likely transmitted sequence. The MLSD algorithm uses the statistical properties of the signal and channel to calculate the likelihood of each possible data sequence, and the sequence with the highest likelihood is selected as the estimated transmitted data sequence. It is also a complex and computationally intensive technique, requiring significant processing power and memory. However, MLSD can provide significant improvements in signal quality and transmission performance, especially in channels with high noise, interference, and dispersion.

Figure 2: Need for MLSD: Channel Library of 40+ dB IL equalized by 224G SerDes

There are several variants of MLSD, including:

  • Viterbi Algorithm
  • Decision Feedback Sequence Estimation (DFSE)
  • Soft-Output MLSD

The Viterbi Algorithm is a popular MLSD algorithm that uses a trellis diagram to generate all possible data sequences and find the most likely sequence. The Viterbi Algorithm can provide excellent performance in channels with moderate noise and ISI, but it may suffer from error propagation in severe channel conditions.

DFSE is another MLSD algorithm that uses feedback from the decision output to improve the sequence estimation accuracy. DFSE can provide better performance than Viterbi Algorithm in channels with high ISI and crosstalk, but it requires more complex circuitry and higher processing power.

Soft-Output MLSD is a variant of MLSD that provides probabilistic estimates of the transmitted data sequence. It can provide significant improvements in the error-correction performance of the system, especially when combined with FEC techniques such as LDPC. Soft-Output MLSD requires additional circuitry to generate the soft decisions, but it can provide significant benefits in terms of signal quality and error-correction capabilities.

Forward Error Correction Techniques

In addition to DSP methods, Forward Error Correction (FEC) techniques adds redundant data to the transmitted signal to detect and correct errors at the receiver end. FEC is an effective technique to improve the signal quality and ensure reliable transmission. There are various FEC techniques that can be used, including Reed-Solomon (RS) and Low-Density Parity-Check (LDPC).

RS is a block code FEC technique that adds redundant data to the transmitted signal to detect and correct errors. RS is a widely used FEC technique in PAM4 SerDes because it is simple, efficient, and has good error-correction capabilities. LDPC is a more advanced FEC technique that uses a sparse parity-check matrix.

Defining the Future of 224G SerDes Architecture

In summary, the IEEE 802.3df working group and the Optical Internetworking Form (OIF) consortium are focused on the definition of the 224G interface.  The analog front-end bandwidth has increased by 2X for PAM4 or by 1.5X for PAM6 to achieve 224G. ADC with improved accuracy and reduced noise is required. Stronger equalization is needed to compensate for the additional loss due to higher Nyquist frequency, with more taps in the FFE and DFE. MLSD advanced DSP will provide significant improvements in signal quality and transmission performance at 224G. MLSD algorithms such as Viterbi Algorithm, DFSE, and Soft-Output MLSD can be used to improve the sequence estimation accuracy and mitigate channel impairments such as noise, interference, and dispersion. However, MLSD algorithms are computationally intensive and require significant processing power and memory, should carefully trade-off between C2M and cabled host applications.

Synopsys has been a developer of SerDes IP for many generations, playing an integral role in defining PAM4 solution with DSP at 224G. Now, Synopsys has a silicon-proven 224G Ethernet solution that customers can reference to achieve their own silicon success. Synopsys provides integration-friendly deliverables for 224G Ethernet PHY, PCS, and MAC with expert-level support which can make customers’ life easier by reducing the overall design cycle and helping them bring their products to market faster.

Also Read:

Full-Stack, AI-driven EDA Suite for Chipmakers

Power Delivery Network Analysis in DRAM Design

Intel Keynote on Formal a Mind-Stretcher

Multi-Die Systems Key to Next Wave of Systems Innovations

 

Podcast EP151: How Pulsic Automates Analog Layout for Free with Mark Williams

Podcast EP151: How Pulsic Automates Analog Layout for Free with Mark Williams
by Daniel Nenni on 04-07-2023 at 10:00 am

Dan is joined by Mark Williams. Mark is a Founder and Chief Executive Officer at Pulsic. He has over 30 years of experience in the EDA industry and was one of the team that pioneered shape-based routing technology in the 1980s while working at Zuken-Redac.

Mark explains the unique “freemium” model for automating analog layout developed by Pulsic. The Animate product offers this capability. Over the past two years, there have been two versions of the tool released. Mark describes the results of this new and innovative business model and previews what’s coming at DAC this year.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Takeaways from SNUG 2023

Takeaways from SNUG 2023
by Bernard Murphy on 04-07-2023 at 6:00 am
Categories: AI, Chiplet, EDA, Synopsys
2 Comments

Aart keynote

Synopsys pulled out all the stops for this event. I attended the first full day, tightly scripted from Aart’s keynote kick off to 1×1 interviews with Synopsys executives to a fireside chat between Sassine Ghazi (President and COO) and Rob Aitken (ex-Fellow at Arm, now Distinguished Architect at Synopsys). That’s a lot of material; I will condense heavily to just takeaways. My colleague Kalar will cover the main Synopsys.ai theme (especially Aart’s talk).

AI in EDA

The big reveal was broad application of AI in the Synopsys tool suite, under the Synopsys.ai banner. This is exemplified in DSO.ai (design space optimization), VSO.ai (verification space optimization) and TSO.ai (test space optimization). I talked about DSO.ai in an earlier blog, a reinforcement learning method starting from an untrained algorithm. The latest version is now learning through multiple parallel training runs, advancing quickly to better PPAs that customers have been able to find in much less time and needing only one engineer. Synopsys claim similar results for VSO.ai for which the objective is to reduce time to coverage targets and increase coverage, and for TSO.ai for which the objective is to reduce the number of ATPG vectors required for the same or better coverage.

My discussions with execs including Thomas Anderson (VP AI and Machine Learning at Synopsys) suggest that these are all block level optimizations. DSO.ai wraps around Fusion Compiler (a block-level capability) and TSO.ai wraps around TestMax here advertised for the ATPG feature, not BIST. Similarly, the coverage metric for VSO.ai suggests functional coverage, not including higher level coverage metrics. Don’t get me wrong. These are all excellent capabilities, providing a strong base for implementation and verification at the system level.

Aart did talk about optimization for memories, I think in a system context, indicating they are exploring the system level. I think AI application at that level will be harder and will advance incrementally. Advances in performance and power now depend on architecture rather than process, driving a lot of architecture innovation which will impede approaches to optimization which insufficiently understand the architecture. Further, any system-level optimizer will need to collaborate with in-house and commercial generators (for mesh networks and NoCs for example), inevitably slowing progress. Finally, optimization at the system level must conform to a broader set of constraints, including natural language specifications and software-level use-case tests. Speculating on Aart’s memory example, perhaps optimization can be applied to a late-stage design to replace existing IP instances with improved instances. That would certainly be valuable.

What about pushing AI through the field to customers? Alessandra Costa (Sr. VP WW customer success at Synopsys) tells me that at a time when talent scarcity has become an issue for everyone, the hope of increasing productivity is front and center for design teams. She tells me, “There are high expectations and some anxiety on AI to deliver on its promises.”

DSO.ai has delivered, with over 160 tapeouts at this point, encouraging hope that expectations may outweigh anxiety. DSO.ai is now in the curriculum for implementation AEs, driving wider adoption of the technology across market segments and regions. Verification is an area where shortage of customer talent is even more acute. Alessandra expects the same type of excitement and adoption in this space as proven for DSO.ai. Verification AEs are now being trained on VSO.ai and are actively involved in deployment campaigns.

Multi-die systems

Aart talked about this, I also talked with Shekhar Kapoor (Sr. Director of Marketing) to understand multi-die as a fast-emerging parameter in design architecture. These ideas seem much more real now, driven by HPC need, also automotive and mobile. Shekhar had a good mobile example. The system form factor is already set, yet battery sizes are increasing, shrinking the space for chips. At the same time each new release must add more functionality, like support for multiplayer video games. Too much to fit in a single reticle, but you still need high performance and low power at a reasonable unit cost. In HPC, huge bandwidth is always in demand and memory needs to sit close to logic. Multi-die isn’t easy, but customers are now saying they have no choice.

Where does AI fit in all of this? Demand for stacking is still limited but expected to grow. Interfaces between stacked die will support embedded UCIe and HBM interfaces. These high frequency links require signal and power integrity analyses. Stacking limits amplifies thermal problems so thermal analysis is also critical. Over-margining everything becomes increasingly impractical at these complexities, requiring a more intelligent solution. Enter reinforcement learning. Learning still must run the full suite of analyses (just as DSO.ai does with Fusion Compiler), running multiple jobs in parallel to find its way to goal parameters.

There are still open challenges in multi-die as Dan Nenni has observed. How do you manage liability? Mainstream adopters like AMD build all their own die (apart from memories) for their products so can manage the whole process. The industry is still figuring out how to manageably democratize this process to more potential users.

Other notable insights

I had a fun chat with Sassine at dinner the night before. We talked particularly about design business dynamics between semiconductor providers and system companies, whether design activity among the hyperscalers and others is a blip or a secular change. I’m sure he has more experience than I do but he is a good listener and was interested in my views. He made a point that systems companies want vertical solutions, which can demand significant in-house expertise to specify, design and test and of course should be differentiated from competitors.

Rapid advances in systems technology and the scale of those technologies make it difficult for semiconductor component builders to stay in sync. So maybe the change is secular, at least until hyperscalar, Open RAN and automotive architectures settle on stable stacks? I suggested that a new breed of systems startups might step into the gap. Sassine wasn’t so certain, citing even more challenging scale problems and competition with in-house teams. True, though I think development under partnerships could be a way around that barrier.

I had another interesting talk with Alessandra, this time on DEI (diversity, equity and inclusion). Remember her earlier point about lack of talent and the need to introduce more automation? A complementary approach is to start developing interest among kids in high school. University-centric programs may be too late. She has a focus on girls and minorities at that age, encouraging them to play with technologies, through Raspberry Pi or Arduino. I think this a brilliant idea. Some may simply be attracted to the technology for the sake of the technology. Perhaps others could be drawn in by helping them see the tech as a means to an end – projects around agriculture or elder care for example.

Good meeting and my hat is off to the organizers!

Also Read:

Full-Stack, AI-driven EDA Suite for Chipmakers

Power Delivery Network Analysis in DRAM Design

Intel Keynote on Formal a Mind-Stretcher

Multi-Die Systems Key to Next Wave of Systems Innovations

 

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TSMC has spent a lot more money on 300mm than you think

TSMC has spent a lot more money on 300mm than you think
by Scotten Jones on 04-06-2023 at 10:00 am
Categories: Foundries, Semiconductor Services, TechInsights, TSMC
1 Comment

Slide1

Up until November of 2022, IC Knowledge LLC was an independent company and had become the world leader in cost and price modeling of semiconductors. In November 2022 TechInsights acquired IC Knowledge LLC and IC Knowledge LLC is now a TechInsights company.

For many years, IC Knowledge has published a database tracking all the 300mm wafer fabs in the world. Compiled from a variety of public and private sources, we believe the 300mm Watch database is the most detailed database of 300mm wafer fabs available. IC Knowledge LLC also produces the Strategic Cost and Price Model that provides detailed cost and price modeling for 300mm wafer fabs as well as detailed equipment and materials requirements. The ability to utilize both products to analyze a company provides a uniquely comprehensive view and we recently utilized these capabilities to do a detailed analysis of TSMC’s 300mm wafer fabs.

One way we check the modeling results of the Strategic Cost and Price Model is to compare the modeled spending on 300mm fabs for TSMC to their reported spending. Since the early 2000s nearly all of TSMC’s capital spending has been on 300mm wafer fabs and the Strategic Model covers every TSMC 300mm wafer fab.

Figure 1 presents an analysis of TSMC’s cumulative capital spending by wafer fab site from 2000 to 2023 and compares it to the reported TSMC capital spending.

Figure 1. TSMC Wafer Fab Spending by Fab.

In figure 1 there is a cumulative area plot by wafer fab calculated using the Strategic Cost and Price Model – 2023 – revision 01 – unreleased, and a set of bars representing TSMC’s reported capital spending. One key thing to note about this plot is the Strategic Cost and Price Model is a cost and price model and fabs don’t depreciate until they are put on-line, therefore the calculated spending from the model is for when the fabs come on-line whereas the reported TSMC spending is when the expenditure is made regardless of when it comes on-line. TSMC’s capital spending also includes some 200mm fab, and mask and packaging spending. The TSMC reported spending is adjusted as follows:

  1. In the early 2000s estimated 200mm spending is subtracted from the totals. In some cases, TSMC announced what portion of capital spending was 200mm. In the overall cumulative total through 2022 this is a not a material amount of spending.
  2. Recently roughly 10% of TSMC’s capital spending is for masks and packaging, TSMC discloses this and it is subtracted from the total.
  3. When capital equipment is acquired but not yet put on-line, it is accounted for as assets in progress and this number is disclosed in financial filings. We subtract this number from the reported spending because the Strategic Model calculates on-line capital.

Note that fabs 12 and 20 are/will be in Hsinchu – Taiwan, Fabs 14 and 18 are in Tainan – Taiwan, Fab 15 is in Taichung – Taiwan, Fab 16 is in Nanjing – China, Fab 21 is in Arizona – United States, Fab 22 is planned for Kaohsiung – Taiwan and Fab 23 is being built in Kumamoto – Japan.

Some interesting conclusions from this analysis:

TSMC has spent roughly $135 billion dollars on 300mm wafers fabs through 2022. This number should break $200 billion dollars in 2024.

Fab 18 is TSMC’s most expensive fab (5nm and 3nm production), we expect that site to exceed $100 billion dollars in investment next year. Interestingly Fab 18 is right next to Fab 14 where an investment of more than $30 billion dollars has taken place and the combination next year will approach $140 billion dollars!

The capital investment of roughly $135 billion dollars in 300mm fabs just by TSMC is an amazing number, perhaps even more amazing is the investment is accelerating, should break $200 billion dollars in 2024 and could break $400 billion dollars by 2030.

Customers that license our 300mm Watch channel not only get the 300mm watch database along with regular updates, they also get access to this recent TSMC analysis and will also get access to a similar analysis we are doing of Samsung. For information on the 300mm Watch database or Strategic Cost and Price Model please contact sales@techinsights.com

Also Read:

SPIE Advanced Lithography Conference 2023 – AMAT Sculpta® Announcement

IEDM 2023 – 2D Materials – Intel and TSMC

IEDM 2022 – TSMC 3nm

IEDM 2022 – Imec 4 Track Cell

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Interconnect Under the Spotlight as Core Counts Accelerate

Interconnect Under the Spotlight as Core Counts Accelerate
by Bernard Murphy on 04-06-2023 at 6:00 am
Categories: AI, Arteris, Automotive, IP

Core counts min

In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware delivered improved performance/area/power metrics every year, allowing software to expand in complexity and deliver more capability with no downsides. Then the easy wins became less easy. More advanced processes continued to deliver higher gate counts per unit area but gains in performance and power started to flatten out. Since our expectations for innovation didn’t stop, hardware architecture advances have become more important in picking up the slack.

Drivers for increasing core-count

An early step in this direction used multi-core CPUs to accelerate total throughput by threading or virtualizing a mix of concurrent tasks across cores, reducing power as needed by idling or powering down inactive cores. Multi-core is standard today and a trend in many-core (even more CPUs on a chip) is already evident in server instance options available in cloud platforms from AWS, Azure, Alibaba and others.

Multi-/many-core architectures are a step forward, but parallelism through CPU clusters is coarse-grained and has its own performance and power limits, thanks to Amdahl’s law. Architectures became more heterogenous, adding accelerators for image, audio, and other specialized needs. AI accelerators have also pushed fine-grained parallelism, moving to systolic arrays and other domain-specific techniques. Which was working pretty well until ChatGPT appeared with 175 billion parameters with GPT-3 evolving into GPT-4 with 100 trillion parameters  – orders of magnitude more complex than today’s AI systems – forcing yet more specialized acceleration features within AI accelerators.

On a different front, multi-sensor systems in automotive applications are now integrating into single SoCs for improved environment awareness and improved PPA. Here, new levels of autonomy in automotive depend on fusing inputs from multiple sensor types within a single device, in subsystems replicating by 2X, 4X or 8X.

According to Michał Siwinski (CMO at Arteris), sampling over a month of discussions with multiple design teams across a wide range of applications suggests those teams are actively turning to higher core counts to meet capability, performance, and power goals. He tells me they also see this trend accelerating. Process advances still help with SoC gate counts, but responsibility for meeting performance and power goals is now firmly in the hands of the architects.

More cores, more interconnect

More cores on a chip imply more data connections between those cores. Within an accelerator between neighboring processing elements, to local cache, to accelerators for sparse matrix and other specialized handling. Add hierarchical connectivity between accelerator tiles and system level buses. Add connectivity for on-chip weight storage, decompression, broadcast, gather and re-compression. Add HBM connectivity for working cache. Add a fusion engine if needed.

The CPU-based control cluster must connect to each of those replicated subsystems and to all the usual functions – codecs, memory management, safety island and root of trust if appropriate, UCIe if a multi-chiplet implementation, PCIe for high bandwidth I/O, and Ethernet or fiber for networking.

That’s a lot of interconnect, with direct consequences for product marketability. In processes below 16nm, NoC infrastructure now contributes 10-12% in area. Even more important, as the communication highway between cores, it can have significant impact on performance and power. There is real danger that a sub-optimal implementation will squander expected architecture performance and power gains, or worse yet, result in numerous re-design loops to converge.  Yet finding a good implementation in a complex SoC floorplan still depends on slow trial-and-error optimizations in already tight design schedules. We need to make the jump to physically aware NoC design, to guarantee full performance and power support from complex NoC hierarchies and we need to make these optimizations faster.

Physically aware NoC designs keeps Moore’s law on track

Moore’s law may not be dead but advances in performance and power today come from architecture and NoC interconnect rather than from process. Architecture is pushing more accelerator cores, more accelerators within accelerators, and more subsystem replication on-chip. All increase the complexity of on-chip interconnect. As designs increase core counts and move to process geometries at 16nm and below, the numerous NoC interconnects spanning the SoC and its sub-systems can only support the full potential of these complex designs if implemented optimally against physical and timing constraints – through physically aware network on chip design.

If you also worry about these trends, you might want learn more about Arteris FlexNoC 5 IP technology HERE.

 

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AI is Ushering in a New Wave of Innovation

AI is Ushering in a New Wave of Innovation
by Greg Lebsack on 04-05-2023 at 10:00 am
Categories: AI
1 Comment

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Artificial intelligence (AI) is transforming many aspects of our lives, from the way we work and communicate to the way we shop and travel. Its impact is felt in nearly every industry, including the semiconductor industry, which plays a crucial role in enabling the development of AI technology.

One of the ways AI is affecting our daily lives is by making everyday tasks more efficient and convenient. For example, AI-powered virtual assistants such as Alexa and Siri can help us schedule appointments, set reminders, and answer our questions. AI algorithms are also being used in healthcare to analyze patient data and provide personalized treatment plans, as well as in finance to detect fraud and make investment decisions.

AI is also changing the way we work. Many jobs that used to require human labor are now being automated using AI technology. For example, warehouses are increasingly using robots to move and sort goods, and customer service departments are using chatbots to handle routine inquiries.

The semiconductor industry is a critical component of the AI revolution. AI relies on powerful computing processors, such as graphics processing units (GPUs) and deep learning processors (DLPs), to process massive amounts of data and perform complex calculations. The demand for these chips has skyrocketed in recent years, as more companies invest in AI technology.

AI is beginning to have an impact on the design and verification of ICs. AI can be used to improve the overall design process by providing designers with new tools and insights. For example, AI-powered design tools can help designers explore design alternatives and identify tradeoffs between performance, power consumption, and cost. AI can also be used to provide designers with insights into the behavior of complex systems, such as the interaction between software and hardware in an embedded system.

AI is enabling the development of new types of chips and systems. For example, AI is driving the development of specialized chips for specific AI applications, such as image recognition and natural language processing. These specialized chips can perform these tasks much faster and more efficiently than general-purpose processors and are driving new advances in AI technology.

Semiconductor fabrication is the largest expenditure and AI has the greatest potential in this area. AI can help optimize the manufacturing process from design to fabrication by analyzing the process data, identifying defects, and suggesting optimizations.  These insights and changes will allow fans to detect problems earlier, reducing cost, increasing yield, and improving overall efficiency.

There are also many concerns with a technology that is this disruptive.  While this automation can potentially increase productivity and reduce costs, it also raises concerns about job loss and the need for workers to acquire new skills.  There are also a number of ethical concerns associated with AI.  AI systems can collect and analyze large amounts of personal data, raising concerns about privacy and surveillance. There are also concerns about the potential for corporations and governments to misuse this data for their own purposes.

AI is transforming many aspects of our lives, from the way we work and communicate to the way we shop and travel. The semiconductor industry is a critical component of the AI revolution, not only providing the computing power to enable AI, but also benefiting from AI for IC design and manufacturing improvements. As AI technology continues to advance, it is likely that it will continue to play an increasingly important role in the semiconductor design process, enabling new levels of innovation and driving new advances in AI technology.   It is essential to stay informed about AIs impact and ensure that its benefits are realized while minimizing the potential risks.

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