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Intel and TSMC IDM 2024 Discussions

Intel and TSMC IDM 2024 Discussions
by admin on 03-10-2024 at 8:00 am
Categories: Events, Foundries, Intel Foundry, TSMC
6 Comments

TSMC Intel

In December 2023, we published the Intel Revenue forecast for external wafer sales, gave a breakdown on how customers plan to ramp the foundry. The forecast is still valid (it assumes Intel executes on all plans) but since then we have a better understanding of Intel’s strategy and scenarios that could unfold.

The scenarios are based on Intel’s strengths and weaknesses which are quite different than TSMC and quite different than what we expected 2-3 years ago.

Background:

In 2019-2021, it became clear that Intel was a distant follower to TSMC in technology and that they needed to catch up or just outsource everything to TSMC/Samsung/others. Intel BUs complained about technology delay and cost and wanted to work with TSMC.

• It seemed like Intel would move to outsource, but Pat changed the plans based on discussions in 2021. Intel would allow BUs to choose Internal or TSMC. They would (and still do) come up with dual sourcing options and plans until later in the product development lifecycle.

• Intel cannot lead in tech with the small scale of current Intel (Times change, Intel is the third priority for equipment companies). Equipment vendors do much of the process and all of the tool development. You need scale to get their support. So Intel needs to offer foundry services to roughly double the scale of Intel wafer output. Intel needed to go “all in” on being a leading foundry.

• Pat [hypothetically] said: “…Business units say manufacturing is the problem. Manufacturing say BU is the problem. Fine …. Each of you can do what you want…. BUT we will make major decisions based on your execution.”

Hence where we are today: Intel is ramping TSMC on chips for processors of all types. Some leading products are 100% TSMC. And Intel is promoting foundry for others at the same time. 5 nodes in 4 years (not really, but that is a different report).

The BUs are extremely happy with this. So far multiple products have been moved to TSMC and the flexibility in using N5,N3,N2 is something they love. TSMC price is about the same as Intel’s cost, so BU margins will increase.

But how does Intel compete cost effectively with TSMC and ramp foundry and pay for all these fabs?

We overlooked a couple things until our IEDM discussions with various people in December 2023.

• Intel still wants to win and be better than TSMC. It seems unlikely… but it might not matter.

• The US government buys chips for internal products and DoD items. No strategic DoD product has TSMC parts in it. TSMC does not meet the criteria. As a result, those products have technologies that are not close to leading edge. IBM (past), GF and other defense approved companies make chips for those products but they are nowhere near leading edge. They would love to use leading edge but they need a DoD approved US company. While DoD parts are relatively low volume, the government could expand this to any Government supply chain (they track detailed supply chain and factories for all parts). IRS, Social Security, etc. TSMC cannot fill this today and it would require massive regulation to even have Samsung US or TSMC US support it. Trust me, I have done the audits with government products before, it can be extremely painful.

Also, While Intel is not set up from a scale or from a cultural perspective to be a leader in cost, US Government pays cost plus and incredibly high prices for products. Intel could have half filled fabs and still have great margins. You can see this at some government suppliers today.

• The third one also could have been predicted but was missed. Leading edge is too expensive and complex. So many foundries…. GF, UMC, SMIC, Grace, Tower have no ability to provide leading edge or even 2 generations behind technology. Intel can partner with them, provide “more modern” technologies, provide scale etc. All companies not named TSMC or Samsung could GREATLY benefit from partnering with Intel and this allows them to compete with Samsung and TSMC.

Based on the above strategies. Intel could outsource most of its silicon to TSMC to keep the BUs happy and STILL be a leader in foundry just based on being the “US Fab company” and “advanced fabs to other foundries”. These customers are much more compatible with Intel than selling to Apple, AMD, Nvidia, and Broadcom.

This is a different foundry model but one where Intel has a strength and can potentially dominate. This all may or may not work. We have quantitative milestones you can track to see if Intel is successful.

The Three Potential Foundry Scenarios are:

• *Intel Foundry Success*: Intel has competitive processes at competitive prices and ramps up to be another dominant leading edge foundry. Intel is leader and Intel BUs use Intel processes. Revenue and profits grow.

• *Intel fills TSMC gaps*: Intel supplies all other foundries, Intel supplies government. Both have few other options so they pay the price needed. Revenue grows steadily over then next 10-15 years.

• *Intel is IDM2.0 = IBM2.0*: Intel struggles to ramp government work and factories. Intel’s foundry partners decide it’s not worth it to work with them and the processes are unsuccessful. The fabs are given away, or cancelled, or underloaded. Eventually Intel foundry is absorbed.

We have more details on each and in the next few years, the probability of each scenario will change. We have updates on the probability and what tactics, models, and strategies Intel is using. More importantly we provide milestones so others can track progress…. and we track the impact to P&L and Capex.

Foundry Day Update (BREAKING NEWS): All of the presentations and commitments support the background we show, the strategies, and the scenarios.

Mark Webb
www.mkwventures.com

Also Read:

Intel Direct Connect Event

ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability

Intel should be the Free World’s Plan A Not Plan B, and we need the US Government to step in

How Disruptive will Chiplets be for Intel and TSMC?

Podcast EP211:A Look at the Inner Workings of the CHIPS and Science Act with Mike O’Brien

Podcast EP211:A Look at the Inner Workings of the CHIPS and Science Act with Mike O’Brien
by Daniel Nenni on 03-08-2024 at 10:00 am

Dan is joined by Mike O’Brien. Mike was recently the vice president of aerospace and government at Synopsys, He has 40 years of experience in the semiconductor, software and computer industries. In his 27 years in EDA and IP at Synopsys and Cadence, Mike helped build new lines of business including outsourced design services, research collaborations and a government focused vertical.

Currently, Mike is part of a team working for the US Department of Commerce that will play a key role to implement the CHIPS and Science Act’s historic investments in the semiconductor industry.

Mike explains how the significant investments in semiconductor technology are being managed by the US Department of Commerce, both the $39B for semiconductor manufacturing and $11B for semiconductor R&D. He details the infrastructure that manages the programs between government, private sector and financial organizations to achieve the supply chain coordination required to grow and strengthen US semiconductor capabilities from an economic and national security perspective.

Mike explains how the various organizations work together and how private industry can get involved to harness the investments being made. Details of current and future programs are also discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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International Women’s Day with Christelle Faucon VP Sales Agile Analog

International Women’s Day with Christelle Faucon VP Sales Agile Analog
by Daniel Nenni on 03-08-2024 at 6:00 am
Categories: Agile Analog, IP

Agile Analog Christelle Faucon photo

Born in France, now living in the Netherlands, Christelle Faucon has over 25 years’ experience of working across the global semiconductor ecosystem. Currently she is VP of Sales at Agile Analog, the analog IP innovators. Following a Master’s Degree in Electronics Engineering, Christelle began her career as a Design Engineer. She has since held senior product and commercial positions, including 10 years at TSMC and 10 years as President of GUC (Global Unichip) Europe. Dedicated to empowering women in the semiconductor industry, Christelle is also involved in the GSA Women’s Leadership Initiative.

 What was your first job in the semiconductor industry?
My first job was working as a Design Engineer for VLSI Technology, an American company with a division in the South of France. I was focused on developing DSP behavioral models and providing related technical support. I also worked on designing SoC blocks, writing Verilog, performing synthesis, place and route, as well as verification tasks. It was a varied job that enabled me to gain great hands-on technical experience, which has helped me throughout my career as I moved into more commercial roles.

Why do you enjoy working in the semiconductor industry?
The semiconductor industry is a really interesting place to work. In recent times we have seen innovative electronic devices that impact positively on everyday lives. IoT, healthcare sensors, automotive safety systems, remote monitoring solutions – all made possible by advances in semiconductors. And there are many new applications in development. When you work in the semiconductor sector you never get bored! I am delighted to now be working at Agile Analog. Our ground-breaking analog IP technology simplifies semiconductor design and speeds up integration, and looks set to transform the world of analog IP.

What is your main professional goal for 2024?
It’s great to be working with the Agile Analog team to help accelerate adoption of our customizable analog IP products across the globe. I find it so exciting that the company has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications, for any foundry and on any process. Demand is growing fast, especially for our data conversion and power management solutions. My own background as a chip designer will help me to understand the challenges that our customers are facing. My industry experience and strong technical knowledge will also be beneficial. It is very rewarding to be part of Agile Analog at such a pivotal time.

Outside of work – what hobbies do you have?
I love to travel and experience new cultures. I also enjoy horse riding in my spare time. Last November, before I started at Agile Analog, I had the chance to do both during an amazing trip to Nepal which included horse riding in some remote areas. My wish list of countries still to visit is very long!

 What advice would you give to your younger self?
The best advice I could offer my younger self would be: don’t be afraid to step outside of your comfort zone. Believe in yourself. You can achieve much more than you expect. Embrace every opportunity to learn new things.

Tell us about the GSA Women’s Leadership Initiative you are involved with.
March 8th is International Women’s Day. To me it is so disappointing that less than 30% of engineering graduates are female, and quite shocking that less than 5% of leadership positions in the semiconductor sector are held by women.

That’s why I am committed to empowering women in the semiconductor industry, by championing the creation of impactful programs through the Global Semiconductor Alliance GSA Women’s Leadership Initiative that foster diversity. The primary goal is to help cultivate a strong community of women that provides mentoring and calls for equal opportunities. Joining the GSA EMEA Women’s Leadership Council means that I can use my experience to help women in the sector.

The first GSA Women’s Leadership Initiative EMEA event will take place in London on March 13th – the Women in Semiconductors Conference – on day 1 of the GSA International Semiconductor Conference. This aims to highlight the achievements of some of those women who have succeeded in navigating a traditionally male-dominated environment. It should be a really interesting and informative event.

What advice would you give to experienced female engineers and female leaders in the semiconductor industry?
My advice for senior female engineers and women in leadership positions across the global semiconductor industry would be – don’t hide – please come forward to share your experiences and expertise. If possible, speak at career fairs and industry events. Role models are required to inspire the younger generation. It is also vital to support each other and to encourage more women to take on leadership roles in semiconductor companies. That’s why I feel the work of the GSA Women’s Leadership Initiative is so important.

Also Read:

2024 Outlook with Chris Morrison of Agile Analog

Agile Analog Partners with sureCore for Quantum Computing

Agile Analog Visit at #60DAC

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Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips

Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips
by Kalar Rajendiran on 03-07-2024 at 10:00 am
Categories: AI, EDA, IP, Synopsys

Synopsys 1.6T Ethernet IP Solution Image 2

The demand for high-bandwidth, low-latency networking solutions has never been greater. As artificial intelligence (AI) workloads continue to grow exponentially, and hyperscale data centers become the backbone of our digital infrastructure, the need for faster and more efficient communication technologies becomes imperative. 1.6T Ethernet will rapidly be replacing 400G and 800G Ethernet as the backbone of hyperscale data centers.

Hyperscale data centers, which power everything from cloud computing and big data analytics to AI and machine learning, require high-bandwidth, low-latency chips and interfaces to process petabytes of data quickly and efficiently. As the demand for computing power continues to grow, so does the energy consumption of data centers. High power consumption by interconnects leads to increased heat generation, which in turn requires more robust cooling systems to maintain optimal operating temperatures. By reducing interconnect power consumption, less heat is generated, overall energy efficiency can be improved, leading to cost savings and reduced environmental impact. In essence, when it comes to AI and data center infrastructure, it is the latency, power and size trifecta that are of critical importance, in addition to the speed.

Synopsys recently unveiled the industry’s first complete 1.6T Ethernet IP solution that addresses all of the above requirements. Enabling up to 40% latency reduction, 50% interconnect power reduction and 50% area reduction compared to existing solutions, Synopsys’ complete solution includes a pre-verified subsystem, giving a head start to chip designers.

Complete Solution

The complete 1.6T Ethernet IP solution from Synopsys includes a range of innovative technologies designed to optimize performance, reduce power consumption, and accelerate time-to-market for AI and HPC networking chips.

Following is a contextual quote from Mick Posner, VP of Product Management, High Performance Computing IP Solutions at Synopsys.

“The silicon providers behind data center units require adoption of the latest generation of interconnect protocols so that they can optimize their silicon to scale with new workloads. And this is exactly where 1.6 Ethernet comes in.”

Offering customers a complete Ethernet IP solution simplifies integration, reduces complexity, optimizes performance, eases deployment, provides consistent support, enables scalability, and helps mitigate risks. These benefits ultimately lead to greater customer satisfaction and success in deploying and maintaining Ethernet IP networks.

The Synopsys 1.6T Ethernet IP solution features new, optimized MAC and PCS IP

 

1.6T MAC and PCS Ethernet Controllers

Forward Error Correction (FEC) mechanisms play a pivotal role in enhancing the reliability of data transmission over high-speed links, particularly in the context of 1.6Tbps traffic. While FEC helps combat errors and ensures data integrity, its implementation introduces additional considerations such as area, power consumption and latency. Striking the right balance between Bit Error Rate (BER), power efficiency, and latency becomes imperative in designing efficient communication systems for the 1.6T era. By implementing a patented Reed-Solomon FEC architecture, Synopsys is able to decrease area by 50% and reduce latency by 40% on the 1.6T Ethernet MAC and multi-channel, multi-rate PCS Controllers without sacrificing reliability across Ethernet rates from 10G to 1.6T.

224G Ethernet PHY IP

Synopsys’ silicon-proven Ethernet PHY IP delivers robust link performance with exceptional signal integrity, supporting chip-to-chip, chip-to-module, and copper cable connections. The customizable PHY IP optimizes power and performance tradeoffs, providing seamless ecosystem interoperability for multiple channel lengths.

Verification IP

Synopsys’ verification IP for up to 1.6T Ethernet speeds accelerates time-to-market by speeding up the verification process. Implemented in native SystemVerilog and Universal Verification Methodology (UVM), the verification IP provides a comprehensive set of protocol, methodology, and productivity features, ensuring reliable and efficient testing of Ethernet designs. As the industry’s first Ethernet verification IP for up to 1.6T, it helps speed time to first test.

Backward Compatibility

Synopsys’ 1.6T IP solution is backward compatible with 400G and 800G Ethernet solutions, allowing users to upgrade or expand their systems at their own pace without facing costly disruptive changes. Backward compatibility is vital for preserving investments, ensuring smooth transitions, and promoting interoperability in software, hardware, and protocols. By allowing users to seamlessly integrate new technologies with existing systems, the Synopsys solution’s backward compatibility minimizes disruption and reduces the learning curve.

Silicon to Systems Design Solutions

Synopsys’ complete solution includes pre-verified subsystems enabling customers to streamline their development process and reduce time-to-market and development risks. These subsystems, rigorously tested and validated by suppliers, ensure high reliability and adherence to industry standards. Equipped with these, customers can focus on their core competencies while enjoying scalability and flexibility. The accelerated time-to-market enhances the overall return on investment, making pre-verified subsystems a valuable asset for efficient product development by customers large, medium and small alike.

The Synopsys 1.6T Ethernet IP solution subsystem integrates pre-verified MAC, PCS, and PHY

Summary

Synopsys’ complete 1.6T Ethernet IP solution represents a significant milestone in the evolution of networking technologies for AI and hyperscale data centers. By offering innovative solutions that optimize performance, lower latency, reduce power consumption, and accelerate time-to-market, Synopsys is helping to drive the future of AI and high-performance computing, enabling customers to meet current and future demands of the most data-intensive workloads.

For more details, visit Synopsys Complete 1.6T Ethernet IP Solution.

You can access Synopsys’ press release on their complete 1.6T Ethernet IP solution here.

Also Read:

2024 Signal & Power Integrity SIG Event Summary

Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links

Why Did Synopsys Really Acquire Ansys?

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2024 Outlook with Da Chuang of Expedera

2024 Outlook with Da Chuang of Expedera
by Daniel Nenni on 03-07-2024 at 6:00 am
Categories: Expedera, IP

Da Chuang 2

Expedera provides customizable neural engine semiconductor IP that dramatically improves performance, power, and latency while reducing cost and complexity in edge AI inference applications. Da is co-founder and CEO of Expedera. Previously, he was cofounder and COO of Memoir Systems, an optimized memory IP startup, leading to a successful acquisition by Cisco. At Cisco, he led the Datacenter Switch ASICs for Nexus 3/9K, MDS, CSPG products. Da brings more than 25 years of ASIC experience at Cisco, Nvidia, and Abrizio. He holds a BS EECS from UC Berkeley, MS/PhD EE from Stanford. Headquartered in Santa Clara, California, the company has engineering development centers and customer support offices in the United Kingdom, China, Japan, Taiwan, and Singapore.

Tell us a little bit about yourself and your company.

My name is Da Chuang, and I am the co-founder and CEO of Expedera. Founded in 2018, Expedera has built our reputation of providing the premier customizable NPU IP for edge inference applications from edge nodes and smartphones to automotive. Our Origin NPU, now in its 4thgeneration architecture, supports up to 128 TOPS in a single core while providing industry-leading processing and power efficiencies for the widest range of neural networks including RNN, CNN, LSTM, DNN, and LLMs.

-What was the most exciting high point of 2023 for your company?

>>2023 was a year of tremendous growth for Expedera. We added two new physical locations to our company, Bath (UK) and Singapore. Both of these offices are focused on future R&D, developing next-generation AI architectures, plus other things you’ll be hearing about in the months and years to come. While that is very exciting for us, perhaps the most significant high point for Expedera in 2023 was our customer and deployment growth. We started the year with the news that our IP had been shipped in over 10M consumer devices, which is a notable number for any Semiconductor IP startup. Throughout the year, we continued to expand our customer base, which now includes worldwide Tier 1 smartphone OEMs, consumer devices chipsets, and automotive chipmakers. Our NPU solution is recognized globally as the best in the market, and customers come to us when they want the absolute best AI engine for their products.

-What was the biggest challenge your company faced in 2023?

>>The biggest challenge in 2023, along with the biggest opportunity, has been the emergence of Large Language Models (LLMs) and Stable Diffusion (SD) in the edge AI space. LLMs/SD represent a paradigm shift in AI – they require more specialized processing and more processing horsepower than the typical CNN / RNN networks most customers were deploying in 2022 and prior. The sheer number of LLM/SD-based applications our customers are implementing has been incredible to see. However, the main challenge of LLMs and SD on the edge has been allowing those networks to run within the power and performance envelope of a battery-powered edge device.

-How is your company’s work addressing this biggest challenge?

>> Our customers want to feature products that are AI-differentiated; products that bring real value to the consumer with a fantastic user experience. However, significant hits to battery life aren’t accepted as part of the user experience. As we integrated LLM and SD support into our now-available 4th generation architecture, our design emphasis was focused on providing the most memory efficient, highest utilization, lowest latency NPU IP we could possibly build. We drilled in the underlying workings of these new network types; data movements, propagations, dependencies, etc… to understand the right way to evolve our both our hardware and software architectures to best match future needs. As an example of how we’d evolved, our 4th generation architecture features new matrix multiplication and vector blocks optimized for LLMs and SD, while maintaining our market-leading processing efficiencies in traditional RNN and CNN-style networks.

-What do you think the biggest growth area for 2024 will be, and why?

>> One of our biggest growth areas is 2024 is going to be supporting an increasing variety of AI deployments in automobiles. While most are likely familiar with the usage of AI in the autonomous driving stack for visual-based networks, there are a lot more opportunities and uses that are emerging. Certainly, we’re seeing LLM usage in automobiles skyrocketing, like many other markets. However, we’re also seeing increased usage of AI in other aspects of the car – driver attentiveness, rear seat passenger detection, infotainment, predictive maintenance, personalization, and many others.  All of these are aimed at providing the consumer with the best possible user experience, one of the key reasons for the implementation of AI. However, the AI processing needs of all of these uses vary dramatically, not only in actual performance capabilities but also in the types of neural networks the use case presents.

-How is your company’s work addressing this growth?

>> Along with the aforementioned LLM and SD support, Expedera’s 4th generation architecture is also readily customizable. When Expedera engages in a new design-in with a customer, we seek to understand all the application conditions (performance goals, network support required, area and power limitations, future needs, and others) so that we can best customize our IP – essentially, give the customer exactly what they want without having to make sacrifices for things they don’t. If the customer desires a centralized, high-performance engine handing a number of different uses and support for a variety of networks, we can support that. If the customer wants to deploy decentralized engines handling only specific tasks and networks, we can support that as well – or anywhere in between. And this is all from the same IP architecture, done without time-to-market penalties.

-What conferences did you attend in 2023 and how was the traffic?

>>Expedera exhibits at a targeted group of conferences focused on edge AI, including but not limited to the Embedded Vision Summit and AI Hardware & AI Summit, as well as larger events like CES. Traffic at these events seemed on par with 2022, which is to say respectable. AI is obviously a very hot topic within the tech world today, and every company is looking at ways to integrate AI into their products, workflows, and design process. Accordingly, we’ve seen an ever-increasing variety of attendees at these events, all of whom come with different needs and expectations.

-Will you attend conferences in 2024? Same or more?

>>2024 will likely see a slight expansion of our conference plans, especially those focused on technology. As part of the semiconductor ecosystem, Expedera cannot afford to exist in a vacuum. We’ve spoken at past events about our hardware and software stacks, as well as implementations like our security-centric always-sensing NPU for smartphones. This year, we’ll be spending a lot of our time detailing edge implementations of LLMs, including at upcoming conferences later this Spring. We look forward to meeting many of you there!

Also Read:

Expedera Proposes Stable Diffusion as Benchmark for Edge Hardware for AI

WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments

Area-optimized AI inference for cost-sensitive applications

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Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation

Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation
by akanksha soni on 03-06-2024 at 2:00 pm
Categories: Ansys, Inc., EDA, Events

Ansys and Intel Foundry Direct 2024

In the dynamic realm of technological innovation, collaborations and partnerships often serve as catalysts for groundbreaking advancements. Continuing along this trajectory, Ansys, a global leader in engineering simulation software, has forged a partnership with Intel Foundry to enable multiphysics chip design. The two companies share the same set of values: a commitment to science and innovation. To further strengthen this unprecedented collaboration, Ansys proudly participated in the Intel Foundry Direct 2024 event that happened on 21st February in San Jose, USA.

At the event, John Lee, Vice President and General Manager of the Electronics, Semiconductors, and Optics business unit at Ansys, delivered an Executive Keynote address, along with Keynotes from the other Big-4 EDA suppliers: Synopsys, Cadence, and Siemens. Lee started his talk by eloquently discussing the transformative journey of the semiconductor industry and its pervasive influence across diverse sectors such as high-tech, healthcare, and automotive. He emphasized the critical role of semiconductors in meeting the escalating technological demands of the modern world.

In addressing the evolving demands of the modern world, Lee highlighted how current chip design methodologies are insufficient for handling today’s intricate 2.5D/3D-IC designs. Lee identified three primary challenges facing the EDA industry in crafting intricate architectural chip designs: multi-physics, multi-scale, and multi-organizational challenges. He calls these the 3Ms of 2.5D/3D-IC design.

  • Multi-physics hurdles arise from novel physical effects that are not within the experience of most monolithic chip designers. Lee gave Thermal Integrity, EM Signal Integrity, and Mechanical/Structural Integrity as examples of new multiphysics challenges.
  • Multi-scale challenges manifest due to the blurred boundaries between chip, package, and system design. Multi-die assemblies involve the designer at the nanometer device scale, the micrometer chip layout scale, the millimeter packaging scale, all the way to the cm/m system scale. This multi-scale reality across 6 orders of magnitude means that physical effects fundamentally change how they behave at each level. Thermal was given as a good example of a physical simulation that has very different requirements at the chip, package, and system levels.
  • Multi-organizational challenges emanate from the necessity to revamp traditional company structures to align with the demands of contemporary design. This may be the most intractable problem as companies try to fit the physics to the org chart rather than adapting the org chart to match the physics requirements.

Lee suggests that by adopting strategic thinking, the challenges of multi-physics, multi-scale, and multi-organizational aspects can be turned into valuable opportunities. A considered approach is t suggest the three ‘P’s – physics, platforms, and partnerships – as keys to unlocking the complete benefits arising from the transformative shifts in the industry. John Lee highlighted Ansys’ multiphysics broad and mature array of physics simulation solutions, designed to equip designers with the tools necessary to overcome the hurdles of modern chip design.  He stressed the need for the EDA industry to provide open and extensible platforms that allow customers to bring together the best-in-breed solutions from the entire industry and enable these on the cloud.

In a strategic collaboration, Ansys has recently partnered with Intel to deliver multiphysics signoff solutions tailored for Intel’s innovative 2.5D chip assembly technology. Ansys was able to list its products as certified by Intel in supporting their cutting-edge technology for 18A ribbonFETs, Power Vias for backside power delivery, and EMIB (Embedded Multi-die Interconnect Bridge) to establish flexible connections between multiple dies without relying on through-silicon vias (TSVs).

As another example of successful partnership in the EDA industry, John Lee gave the example of the 3-way collaboration between Intel, Synopsys, and Ansys to solve the multiphysics challenge that links IR-drop and timing closure. The joint solution combines golden signoff technology from both companies to deliver IR-STA and IR-ECO integration flow.

The entire event was exciting and high-energy, devoid of any dull moments. Pat Gelsinger, the Chief Executive Officer at Intel, infused the gathering with his visionary outlook for the Intel foundry and a conviction that Moore’s Law is far from dead. He articulated a compelling vision to catapult this iconic company, reinstating its pivotal position in the realm of technology. Gelsinger’s aim was not merely to revitalize Intel but also to spearhead the restoration of Western chip manufacturing on a grand scale. His vision emphasized the creation of a resilient, sustainable, and trusted supply chain, signaling a strategic commitment to a future marked by innovation and reliability.

Over 30 partners, including the ARM, UMC, MediaTek, and Broadcom took part in the Intel Foundry Direct event. Intel orchestrated an outstanding showcase, featuring special speeches from well-known names in the industry such as Sam Altman, Co-founder and CEO of OpenAI, Secretary Gina M. Raimondo, United States Secretary of Commerce, and Satya Nadella, Chairman and Chief Executive Officer of Microsoft.

In conclusion, the event hosted by Intel Foundry stood out as a remarkable gathering, uniting professionals from various sectors of the semiconductor industry to share insights and envision the future. John Lee’s notable presence underscored the robust partnership between Ansys and Intel. As the collaborative efforts between simulation and fabrication continue to evolve, the Ansys-Intel alliance is poised to make a lasting impact on the technological landscape, pushing boundaries and serving as inspiration for the next wave of breakthroughs.

Learn more about the multiphysics analysis and simulation solutions offered by Ansys here: Ansys Semiconductor Solutions | Datasheet

Also Read:

Why Did Synopsys Really Acquire Ansys?

Will the Package Kill my High-Frequency Chip Design?

Keynote Speakers Announced for IDEAS 2023 Digital Forum

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Accelerate AI Performance with 9G+ HBM3 System Solutions

Accelerate AI Performance with 9G+ HBM3 System Solutions
by Kalar Rajendiran on 03-06-2024 at 10:00 am
Categories: AI, Alphawave Semi, IP

HBM3 PHY and Controller Memory Solution

In the technology realm of artificial intelligence (AI) and high-performance computing (HPC), the demand for higher throughput and efficiency has never been greater. To meet these evolving demands, innovative memory solutions have emerged as critical enablers, paving the way for transformative advancements in computing capabilities. Among these solutions, High Bandwidth Memory (HBM) technology has risen to prominence, offering unparalleled performance, efficiency, and scalability.

Alphawave Semi recently hosted a webinar on the topic of accelerating AI performance with HBM3+ systems solutions and Alphawave Semi’s comprehensive IP offerings enabling it. The webinar also covered the inherent challenges in implementing HBM3 technology and the system challenges to overcome.

AI Disruption and the Need for Higher Throughput

The AI revolution has ushered in a new era of computing, where machine learning algorithms power everything from virtual assistants to autonomous vehicles. These AI applications rely heavily on data-intensive tasks such as deep learning and neural network training. As AI algorithms demand rapid access to vast datasets for real-time decision-making, they place immense strain on memory systems. Memory-centric architectures are an ideal choice for unmatched levels of bandwidth and energy efficiency for such applications.

Motivation for HBM Memory

Traditional memory architectures, such as DDR and GDDR, have long been the backbone of computing systems. However, the exponential growth of AI workloads has exposed their limitations in handling vast amounts of data with low latency. Traditional memory architectures struggle to keep pace with the demands of AI and HPC workloads, leading to performance bottlenecks and inefficiencies. HBM memory addresses this challenge by stacking multiple memory dies vertically, dramatically increasing memory bandwidth while minimizing power consumption and footprint.

Components in a HBM System

A comprehensive memory system comprises several critical components, each playing a vital role in ensuring optimal performance, power efficiency and reliability. These components include the HBM memory dies, physical layer (PHY), controller, interposer, and packaging techniques. The PHY serves as the interface between the memory dies and the rest of the system, while the controller manages data transfer and access. Interposers provide the necessary connections between memory dies, enabling high-speed communication, while advanced packaging techniques ensure thermal management and signal integrity. The integration of these components into a cohesive system architecture is essential for achieving optimal performance and reliability in AI and HPC applications. Alphawave Semi’s expertise in these components enables customers to deploy robust and efficient HBM memory systems that meet the demands of AI and high-performance computing workloads.

System Challenges: Overcoming Hurdles to Adoption

Despite its transformative potential, the adoption of HBM memory presents several challenges, including thermal dissipation, signal integrity, and power delivery. As memory bandwidth increases, so too does the need for efficient cooling solutions to dissipate heat generated by high-speed data transfer. Signal integrity becomes paramount to ensure reliable communication between memory dies, while optimized power delivery architectures are essential to meet the stringent power requirements of AI applications. Managing heat dissipation, mitigating signal distortion, and optimizing power distribution are critical considerations in designing HBM-based systems. Addressing these challenges requires innovative solutions and close collaboration between chip makers, memory vendors, and package technology providers.

Alphawave Semi addresses these challenges through continuous research and development, providing customers with the tools and expertise needed to overcome system-level obstacles and unlock the full potential of HBM memory technology.

Alphawave Semi IP Offerings

Alphawave Semi offers a comprehensive suite of HBM IP solutions tailored to meet the diverse needs of AI and HPC applications. From high-performance HBM PHY and Controller IP to advanced interposer and package design solutions, Alphawave Semi provides the essential building blocks for creating cutting-edge computing systems. By delivering best-in-class PHY and controller IP, Alphawave Semi enables customers to optimize memory subsystem performance, scalability, and power efficiency for their specific application requirements.

What’s Coming Next with HBM4

Looking ahead, HBM4 promises to further elevate the performance and efficiency of memory-centric architectures. HBM4 will enable even faster and more energy-efficient AI and high-performance computing systems. As the industry continues to innovate and evolve, HBM4 represents the next frontier in memory technology, driving advancements in computing capabilities. Alphawave Semi is at the forefront of HBM4 development, driving innovation and shaping the next generation of memory technology.

Summary

HBM memory solutions offer unparalleled performance, efficiency, and scalability, making them indispensable components of modern computing systems. With Alphawave Semi’s expertise and industry-leading IP offerings, semiconductor companies can harness the full potential of HBM memory to accelerate innovation and drive the next wave of AI disruption. By addressing the challenges of AI disruption, empowering system designers with advanced solutions, and driving the development of future technologies like HBM4, Alphawave Semi is shaping the future of computing and unlocking new possibilities for AI and HPC applications.

The entire webinar can be accessed on-demand here.

For more details about Alphawave Semi’s HBM related IP offerings, visit http://www.awavesemi.com/silicon-ip

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Siemens Promotes Digital Threads for Electronic Systems Design

Siemens Promotes Digital Threads for Electronic Systems Design
by Bernard Murphy on 03-06-2024 at 6:00 am
Categories: EDA, Siemens EDA

Digital threads min

Many years ago, I remember discussions around islands of automation/silos. Within the scope of any given silo there is plenty of automation to handle tasks relevant to that phase. But managing the full lifecycle from concept through manufacturing to field support must cross between silos, and those transitions are not as clean and automated. Over time more attention was paid to merging silos, through M&A and tighter integration, so now there are fewer but still bumpy and incompletely automated transitions.

Courtesy Siemens

The merging strategy will only take us so far. OEM system architecture, digital design, validation, manufacturing, and OEM product lifecycle management live in worlds which are too different to be pulled into one over-arching platform. Better connecting these phases in the lifecycle must rely on new interoperability standards and ideas. In the ideas department, Siemens proposes a concept of digital threads to interconnect data between silos.

What is a digital thread?

As Siemens puts it:

(Digital threads) collect, integrate, and manage data across the different stages of a product’s lifecycle. The goal is to then to harness that data in more advanced and interactive ways, which is achieved through a digital twin. While the digital thread provides a structured pathway of data across the lifecycle, the digital twin utilizes this data to dynamically mirror the real-world state, behavior, and performance of a particular product.

The digital twin is the engine to mirror the behaviors of a real-world capability (chip, car, factory), and digital threads are bi-directional data pathways weaving through the twin all the way from architecture to deployment. These act as a common source of truth between different product development and manufacturing/deployment phases, connecting both downstream and upstream, aiming to keep all phases through the lifecycle in sync with the most current expectations, assumptions, and implementation choices.

As described in their whitepaper,  Siemens divides digital thread types into those originating or centered in architecture, components, design data, verification, and manufacturing/deployment. Remember that all these threads connect through the digital twin model (enabling shift-left design and optimization) and to the physical implementation (enabling cross correlation between the model and real-world prototype/deployment behavior).

The architecture, component, and design data threads

For me a perfect example (though not the only example) of the kind of data for which a thread makes sense in architecture is for traceability, a topic of great importance in automotive, aerospace and defense among other domains. Here the goal is to trace compliance with original OEM requirements, all the way through the lifecycle. And conversely to reflect unavoidable non-compliant changes made in design, so these become visible and actionable by all stakeholders through the lifecycle. Today much of this is accomplished through human review of natural language documents and spreadsheets.  More sophisticated traceability systems aim for better mechanized compliance checking so that for example a requirement is matched to a design feature (with change notices if required) and to tests to validate compliance.

A second thread connects component data through the lifecycle. In component design, significant detail is generated for functional behavior, electrical, thermal, and other characteristics. After manufacturing, this data is heavily abstracted into PDF datasheets, losing almost all of the detail that an OEM might sometimes need to see, forcing information communication back to the stone age through human-only readable documents. System developers must craft their own databases to attempt (incompletely and inaccurately) to capture some of this detail from other documents and to add their own metrics such as cost and sourcing risk. Standards such as JEDEC JEP30 Part Model Guidelines aim to upgrade from this mess, to make a true component data thread possible. Another very important factor here is trust and (again) traceability for components. A digital thread can be signed, unlike the mess of documents on which we currently rely.

The design thread as I read it in this white paper primarily connects across the system implementation, from multi-die designs, PCB, module, and full electronic system, although I imagine similar value would extend to domain specific SoC design as a component in the overall system. This thread connects electronics, electrical and MCAD to provide a single source of truth for all requirements at this level, to guide design (including cabling), multiphysics analysis, EMC and even security. It also governs accessibility requirements so that sensitive data is available only to those who have been approved to have access to that data.

The verification and manufacturing/deployment threads

For the verification thread, emphasis in this white paper is on the system above the chip/chiplet level and on physical, parametrics and compliance. One example here is full system optimization based on AI methods, in sync with offerings from other vendors. The Siemens solution is called HyperLynx Design Space Exploration, which I’m guessing uses some form of automated Design of Experiments technique through covering arrays (I have talked about this elsewhere). The other important aspect of verification here is traceability, which I mentioned earlier. Mechanized traceability enables repeated and accurate checks against requirements derived directly from the original OEM requirements. This also enables checks to trigger automatically on a design checkin, facilitating continuous integration and deployment (CI/CD) for faster response time to changes.

For the manufacturing (and deployment) thread, the authors point out that while there are well-established standards and processes in support of handing off designs to manufacturing, there is no standardized feedback loop for issues discovered in manufacturing, such as product yield or component solderability. Nor is there a standardized mechanism to feed field discoveries back into the digital twin. We already know that reproducing post-silicon failures in a digital twin is much easier if a trace of circumstances leading up to the failure is available. Supporting post-manufacturing debug on a twin should be a priority at the board/system level as much as at the SoC level. Thinking further ahead, the paper also mentions growing importance of sustainability and recyclability; both concerns will inevitably reach back into earlier stages in the lifecycle chain.

Nice paper with much food for thought. You can access the paper HERE.

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Designing for Security for Fully Autonomous Vehicles

Designing for Security for Fully Autonomous Vehicles
by Kalar Rajendiran on 03-05-2024 at 10:00 am
Categories: Analytics, Automotive, EDA, IoT, Security, Siemens EDA

OSI Seven layer model for securing network communication

With the advent of IoT devices, vehicles have become increasingly interconnected, offering enhanced automation, connectivity, electrification, and shared mobility. However, this progress also brings forth unprecedented challenges, particularly in ensuring the safety and security of automotive electronics. The complexity of modern electrical/electronic systems in vehicles, encompassing Electronic Control Units (ECUs), communication channels, infotainment systems, and driver assist features, amplifies the vulnerabilities to potential cyber-threats. As vehicles become more interconnected, the risk of malicious hacks poses not only a threat to privacy but also to the lives and well-being of passengers. Therefore, ensuring the security of automotive electronics is not merely a matter of competitive advantage; it is a business, legal, and moral imperative.

Siemens EDA recently published a whitepaper that addresses the challenges faced by IC designers in this regard and offers a solution. The whitepaper, authored by Lee Harrison, Director, Tessent Division of Siemens EDA, delves into the realm of automotive hardware security, focusing on the integration of security solutions within the ICs that power essential vehicle components.

Challenges Faced by IC Designers

With a pressing need for robust security measures, IC designers encounter a myriad of challenges in addressing the intricacies of automotive hardware security. The problems they face are often ill-defined and not widely understood, leading to ambiguity in devising effective solutions. Moreover, the rapid evolution of technology exacerbates the challenge, requiring continuous adaptation to emerging threats and vulnerabilities. In this context, the integration of security features within ICs assumes paramount importance in fortifying automotive hardware against potential cyber-attacks.

The Multi-Layered Security Approach

In addressing the complexities of automotive hardware security, a multi-layered approach becomes indispensable. This approach entails integrating security measures at various levels, including hardware, software, and network protocols. At the hardware level, IC designers must embed robust security features within the silicon itself, leveraging technologies such as hardware encryption, secure boot, and tamper-resistant designs. Additionally, software-based security mechanisms, such as intrusion detection systems and secure firmware updates, play a crucial role in safeguarding against cyber threats. Furthermore, implementing secure communication protocols and network segmentation helps mitigate the risk of unauthorized access and data breaches.

Securing the Physical Layer

At the heart of automotive hardware security lies the physical layer, where designers must address vulnerabilities within the supply chain and protect against tampering and side-channel attacks. Design-for-test (DFT) structures and test buses offer mechanisms to safeguard sensitive data and operations, ensuring the integrity of automotive ICs from fabrication to deployment.

Ensuring Trust at the Data Link Layer

The data link layer serves as the root of trust for validating system hardware and software during boot-up. Hardware trusted anchors (HTA), such as Hardware Security Modules (HSM), provide essential security functions like key protection and secure boot, bolstering the integrity and authenticity of automotive systems.

Protecting the Network Layer

The network layer presents a battleground against malicious network transactions and software requests. Firewalls play a crucial role in controlling packet processing and establishing audit points to track attacks.

Future-Proofing Automotive Hardware with Siemens Solutions

Siemens solutions offer comprehensive security features across multiple layers, enhancing protection against cyber threats. To meet evolving security standards and regulations, makers of automotive ICs can leverage Tessent Design-For-Test (DFT) and Tessent Embedded Analytics IP.

Tessent Design-For-Test (DFT) and Embedded Analytics

These technologies offer a multi-layered security framework that can be seamlessly integrated into ICs to identify and address security vulnerabilities. Tessent DFT enables the implementation of built-in self-test capabilities within ICs, facilitating thorough testing and validation of security features throughout the manufacturing process. Tessent Embedded Analytics empowers ICs with real-time monitoring and analysis capabilities, allowing for proactive detection and response to potential security threats. It provides a comprehensive solution for enhancing automotive hardware security, covering various aspects such as authentication, communication, protection, and device lifecycle management. By offering configurable options across test, functional operation, and system-level security, Tessent ensures that automotive systems are resilient against cyber threats while maintaining low latency.

Automotive stakeholders can significantly enhance the security posture of their systems, ensuring robust protection against cyber-attacks.

Summary

As the automotive industry accelerates towards greater automation, connectivity, and electrification, the imperative for ensuring the security of automotive electronics has never been more in focus. IC designers play a pivotal role in fortifying automotive hardware against evolving cyber threats, leveraging advanced technologies such as Tessent DFT and Embedded Analytics to bolster security at the silicon level. By adopting a multi-layered security approach encompassing hardware, software, and network protocols, automotive stakeholders can mitigate risks, safeguard passenger safety, and uphold the trust and integrity of the automotive ecosystem.

You can access the entire whitepaper here.

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INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with advanced analog and mixed-signal EDA technology

INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with advanced analog and mixed-signal EDA technology
by Daniel Nenni on 03-05-2024 at 6:00 am
Categories: EDA, Siemens EDA

siemens symphony interchip large

Customer case studies have always been my favorite source of information. Press releases are a great start but there is always more to the story. Fortunately, I had the opportunity to speak with Sumit Vishwakarma, principal product manager at Siemens EDA about their recent press release with Interchip. I was an advisor to Berkeley Design Automation (Analog FastSPICE author) up until the acquisition by Siemens EDA so this one was of special interest to me.

What are the key products of Interchip?
Interchip is a leading fabless semiconductor company that specializes in high precision, low power oscillator products. Their high precision Crystal Oscillator ICs are deployed globally in a wide range of products, including computers, mobile phones, medical devices, and industrial equipment.

What is a Voltage Controlled Oscillator and how it differs from a Crystal Oscillator?
Voltage Controlled Oscillators (VCXOs) are electronic devices that generate an output signal with a frequency that can be varied by applying a voltage to the device. Crystal Oscillators (XOs) are electronic circuits that use the mechanical resonance of a vibrating crystal of piezoelectric material to create an electrical signal with a very precise frequency.

What makes Interchip Oscillators stand out?
Interchip excels in high speed, high-precision, wide-pulling-range Crystal Oscillators with robust noise performance and low power consumption.

What are the verification challenges of these Oscillator circuits?
Verifying high-precision, wide-pulling-range Voltage Controlled Oscillators (VCOs) poses challenges including maintaining frequency stability, minimizing phase noise and nonlinear effects, balancing power consumption, managing temperature sensitivity and process variability, ensuring wide pulling range performance, minimizing jitter, and addressing integration complexities. Meeting these challenges requires comprehensive simulation, modeling, characterization, and testing across diverse operating conditions.

How did Siemens EDA AFS and Symphony technology help Interchip meet the verification challenges of these designs?
Interchip used Siemens’ Analog FastSPICE (AFS) and Symphony platform to verify its newest IPV Voltage-Controlled Crystal Oscillator (VCXO) integrated circuits and IPS Simple Packaged Crystal Oscillator (SPXO). These tools from Siemens helped INTERCHIP perform silicon-accurate simulations of their designs three times faster compared to their previous solution. This notable acceleration in verification cycles proved pivotal in successfully meeting their aggressive time-to-market objectives.

What is Siemens Analog FastSPICE platform?
Siemens’ Analog FastSPICE platform provides circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. Certified for foundries down to 2nm, the platform can deliver nanometer-scale SPICE accuracy twice as fast as parallel SPICE simulators. The solution includes comprehensive, full-spectrum device noise analysis to help customers achieve silicon-accurate results.

What is Siemens Symphony platform?
Symphony is industry’s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across A/D interfaces at all levels of the design hierarchy and for all IC applications. Symphony’s modular architecture leverages AFS to provide the fastest mixed-signal simulation performance with nm SPICE accuracy, proven on a wide range of ICs and IC subsystems including ADCs, transceivers, PMICs, multi-GHz PLLs/DLLs, and sensors.

And what is Symphony Pro?
Symphony Pro is our advance tier of Symphony. It is built on the proven performance of Symphony and Questa Visualizer™ to augment the support for digital-centric mixed signal verification methodologies such as UVM-AMS and UPF-MS. Symphony Pro’s Visualizer MS environment offers a seamless debug experience across the entire mixed-signal design hierarchy with comprehensive analysis, automation, and ease-of-use for unmatched productivity.

Here are the quotes from the press release:

“As a leading Crystal Oscillator manufacturer serving many of world’s leading consumer, medical and industrial OEMs, our team thrives on overcoming complex engineering hurdles to deliver high speed, high-precision, wide-pulling-range Crystal Oscillators,” said Ryuji Ariyoshi, CEO, INTERCHIP. “We pride ourselves in successfully overcoming complex design challenges such as linearity, frequency pushing, noise performance, aging and power consumption. Siemens’ Analog FastSPICE platform stood out as our top choice for its ability to provide nanometer, SPICE accurate results at a remarkable 3x faster speed than conventional SPICE simulators. Further, Siemens’ Symphony platform enabled us to successfully verify our chip’s complex analog and digital interaction and functionality.”

“High-precision Crystal oscillators play a critical role in advanced IC clock systems, and they are indispensable in modern electronic devices,” said Amit Gupta, vice president and general manager for the Custom IC Verification Division at Siemens Digital Industries Software. “Their accurate timing, stable frequencies and reliable performance are essential for helping to achieve proper operation, data integrity and overall system efficiency in a wide range of applications. It is rewarding to see the pivotal role played by our Analog FastSPICE and Symphony platforms in facilitating INTERCHIP’s development and verification of their latest high-precision oscillator design.”

I was also an advisor for Amit Gupta, CEO of Solido Design, before their acquisition by Siemens EDA.  EDA is a small world, absolutely.

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