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Better Randomizing Constrained Random. Innovation in Verification

Better Randomizing Constrained Random. Innovation in Verification
by Bernard Murphy on 06-28-2023 at 10:00 am

Innovation New

Constrained random methods in simulation are universally popular, still can the method be improved? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Balancing Scalability and Uniformity in SAT Witness Generator. A refined version of the paper was published by Springer in 2015 in “Proceedings of the 21st International Conference on Tools and Algorithms for the Constructions and Analysis of Systems”. The authors are/were from IIT Bombay and Rice University, Houston TX.

Constrained random effectiveness depends on the quality of constraints, also the uniformity of the distribution generated against those constraints since uneven distributions will bias away from triggering bugs in lightly covered states. Unfortunately generation methods tend either to high uniformity but impractical run-times for large designs or to good scalability but weak uniformity. The authors’ paper describes a method to provide approximate guarantees of uniformity with better performance than prior papers on the topic.

The authors also reported a refinement to this method in a later publication apparently only available from Springer-Verlag.

Paul’s view

A key engine at the heart of all commercial logic simulators is the constraint solver, responsible for picking pseudo-random input values each clock cycle in a constrained-random test. These solvers must be ultra-fast but also pick a good spread of random values across the solution space of the constraints. For the scale of constraint complexity in modern commercial SOC tests this is a really hard problem and EDA vendors have a lot of secret sauce in their solvers to tackle it.

Under the hood of these solvers, constraints are munged into Boolean expressions, and constraint solving turns into a Boolean SAT problem. In formal verification we are trying to find just one solution to a massive Boolean expression. In constrained-random simulation we are trying to find a massive number of “uniformly distributed” solutions to smaller Boolean expressions.

The way solvers achieve uniformity is conceptually simple: partition the set of all solutions into n groups of roughly equal size, first pick a random group and then find a solution that belongs to that group. This forces the solver to spread its solutions over all the groups, and hence over the solution space. Implementing this concept is super hard and involves ANDing the Boolean expression to be solved with a nasty XOR-based Boolean expression encoding a special kind of hash function. This hash function algebraically partitions the solution space into the desired number of groups. The smaller the groups (i.e. the larger n is) the more uniform the solver, but the slower the solver is, so picking the right number of groups is not easy and must be done iteratively.

There are two key innovations in this paper: one relates to dramatically reducing the size of the XOR hash function expression, the other to dramatically reducing the number of iterations required to get the right group size. Both innovations come with rigorous proofs that the solver still meets a formal definition of being “uniform”. It’s impressive work and way too complex to explain fully here, but the results are literally 1000x faster than prior work. If you have the energy to muscle through this paper it is well worth it!

Raúl’s view

A “SAT witness” is a satisfying assignment of truth values to variables such that a Boolean formula F evaluates to true. Constraints in Constrained Random Verification (CRV) of digital circuits are encodable as Boolean formulae, so generation of SAT witnesses is essential for CRV. Since the distribution of errors in a design is not known a priori, all solutions to the constraints are equally likely to discover a bug. Hence it is important to sample the solution space uniformly at random, meaning that if there are RF SAT witnesses, the probability PR of generating a value is 1/RF; the paper uses “almost” uniformly defined as 1/(1+ℇ)RF ≤ PR ≤ (1+ ℇ)/RF. Uniformity poses significant technical challenges when scaling to large problem sizes. At the time of publication of the paper (2014) the proposed algorithm, UniGen, was the first to provide guarantees of almost-uniformity and scaling to hundreds of thousands of variables.  The algorithm is based on 3-independent hash-functions and it is beyond the scope of this blog to delve into it; the reader is referred to section 4 in the paper.

The experimental results show that for problems with up to 486,193 variables witnesses can be generated in less than 782 secs with a probability of 0.98 of success. Comparisons with UniWit, the state-of-the-art at the time, show runtimes that are 2-3 orders of magnitude lower. UniGen manages all 12 examples, while UniWit only can complete 7 out of 12. Uniformity is shown by comparing UniGen to a uniform sampler that simply picks solutions out of RF randomly (Figure 1).

The industry has been moving towards increased automation and advanced verification methodologies, making commercial CRV tools more prevalent, particularly for complex digital designs. Constraint solving techniques have been a fundamental part of CRV. Recent advances have focused on improving constraint solving algorithms, optimizing random test generation, and addressing scalability challenges. And although much progress has been achieved since 2014, the reviewed paper (cited 81 times) is an excellent example that illustrates these advances.

Also Read:

Tensilica Processor Cores Enable Sensor Fusion For Robust Perception

Deep Learning for Fault Localization. Innovation in Verification

US giant swoops for British chipmaker months after Chinese sale blocked on national security grounds


Clock Verification for Mobile SoCs

Clock Verification for Mobile SoCs
by Daniel Payne on 06-28-2023 at 6:00 am

Clock duty cycle distortion

The relentless advancement of mobile phone technology continues to push boundaries, demanding SoCs that deliver ever-increasing performance while preserving extensive battery life. To meet these demands, the industry is progressively embracing lower technology nodes with current designs being taped-out at 5nm or below. Designing and verifying clocks at these lower geometries brings mounting complexities and increasing verification challenges. In this rapidly evolving landscape, current clock verification methodologies must be reassessed to ensure optimal clock performance and reliability.

The existing clock methodologies primarily rely on Static Timing Analysis (STA) as a standalone solution or a more advanced approach, that combines STA with a SPICE simulator to analyze critical paths.  This flow necessitates the involvement of a CAD department to establish the flow and a strict methodology to produce accurate and timely results, but even then, for an SoC level clock signal at a lower process node, the simulator may lack capacity and/or accuracy requirements. Moreover, the identification of critical paths relies heavily on the judgment and experience of engineers. This approach leads to unnecessary guard-banding, leaving valuable timing margin untapped and limiting overall performance.

At the 7nm, 5nm and 3nm process nodes both the transistor and interconnect dimensions are reduced, resulting in sensitivities to a variety of design and process-related issues, like rail-to-rail failures and duty cycle distortion in the clock signal.

Rail-to-rail Failures

If a clock net has a weak driver, long interconnect and large capacitive loading, then it can lead to increased insertion delays, and worst-case a rail-to-rail failure. The voltage levels on the clock simply don’t reach the VSS and VDD levels in a rail-to-rail failure. Running STA alone will not detect this failure mechanism because STA measures timing at specific voltage thresholds.

An increase in clock frequency reduces clock period, resulting in a shorter time window for the clock to reach the supply rail voltage levels. Voltage scaling also makes the clock signal more vulnerable to rail-to-rail failure, as the smaller gap between the supply and Vth leads to increase in non-linear operation, reducing the drive strength. Even process variations in Vth, transistor W and L variations, or parasitic capacitances will contribute to rail-to-rail failure. Local power supply levels will bounce around from IR drop effects, which then degrade signal levels and timing in the clock signal.

Clock rail-to-rail failure detection
Clock duty cycle distortion

When a clock signal propagates through a series of gates with asymmetric pull-up and pull-down drive strengths, then it causes duty-cycle-distortion (DCD). An ideal duty cycle for a clock is 50% low and 50% high pulse width. Increased clock frequencies can amplify timing imbalances and cause signal integrity issues like DCD. Clock interconnect is impacted by capacitive and resistive effects, which change the slew rate for rise and fall times, delaying the clock and causing asymmetry, making DCD effects more pronounced. Process variations directly alter interconnects, adding imbalances in circuit timing, adding to DCD.

Clock duty cycle distortion

For process nodes with asymmetric PVT corners the DCD becomes more pronounced. Results from a STA tool are focused on insertion delay, so it is less accurate to report DCD and Minimum-Pulse-Width (MPW).

Slew Rate and Transition Distortion

At lower process nodes, the parasitic interconnect has more pronounced resistive-shielding and capacitive coupling, degrading slew rate and clock edge transitions. STA tools use a simplified model for interconnect parasitics which can then underestimate the clock signal degradations.

Power-supply induced jitter

Noise in the Power Delivery Network (PDN) impacts clock timing, producing jitter which impacts clock performance.  When the power supply experiences fluctuations or noise, it can introduce voltage variations that directly affect the clock signal’s stability and integrity. Power supply induced jitter can lead to timing errors in clock signals, causing them to arrive earlier or later than expected. This can result in setup and hold violations, leading to potential functional failures in the clock.  The increased jitter can also reduce the timing margin, making the design more susceptible to timing violations and potential performance degradation. STA tools primarily focus on analyzing the timing behavior of a design based on a static representation of the circuit and cannot do Jitter. Designers typically use an approximation for jitter effects, so it is really just another guard-band approach.

Power Supply Noise
Topologies using clock grids and spines

Grid and Spine architecture, especially at 7nm and below technology nodes can offer significant advantages including enhanced signal integrity and power and area efficiency.  Grid and spine structures provide a regular and structured framework for routing clock signals, reducing the impact of the increased process variations of lower technology nodes, improving signal integrity and mitigating issues like clock skew, jitter and noise. In addition, grid and spine architecture allows for optimized routing of clock signals.

Circuit simulation is the only accurate method to verify grids and spines, but most commercial SPICE simulators do not handle the capacity for such large meshes.  Designing a lower technology node clock with grids and spines without an adequate, fast and accurate verification methodology can be a risky proposition.

Summary

Mobile devices require mobile processors, and they often drive the bleeding-edge of IC process technology. Meeting PPA goals in a timely manner is paramount to the success of mobile SoCs. At 7nm and below technology nodes, a fresh approach to clock verification becomes imperative. Failing to adopt such an approach entails increased guard-banding, leading to increased area and power requirements. Most importantly, the conservative nature of guard-banding, leaves valuable performance on the table.

Enter Infinisim’s ClockEdge, an off-the-shelf solution specifically engineered for thorough clock verification and analysis. ClockEdge boasts an exceptional ability to analyze every path within the entire clock domain with SPICE-level accuracy. This has the potential to unlock unparalleled analysis opportunities that are otherwise unattainable using conventional methodologies. Moving to 7nm and below technology node is a costly endeavor, yet it offers significant benefits in Power, Performance and Area (PPA) efficiency. However, guard-banding practices can diminish these advantages. Infinisim’s solution identifies all potential failures and optimizes PPA by minimizing the need for excessive guard-banding, thus capitalizing on the advantages afforded by a move to a lower technology node.

With a well-established reputation, Infinisim has a proven track record in the industry. Their solutions have been adopted as a sign-off tool by their mobile SoC customers, solidifying their position as a trusted partner. Infinisim’s expertise in clock analysis spans a wide range of designs, from 28nm to the most advanced 3nm process node. They provide extensive support for all major foundries, including TSMC, Samsung and GlobalFoundries.

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Samsung Foundry on Track for 2nm Production in 2025

Samsung Foundry on Track for 2nm Production in 2025
by Daniel Nenni on 06-27-2023 at 3:00 pm

Samsung Foundry Forum 2023

On the heels of the TSMC Symposium and the Intel Foundry update, Samsung held their Foundry Forum today live in Silicon Valley. As usual it was a well attended event with hundreds of people and dozens of ecosystem partners. The theme was the AI Era which is appropriate. As I have mentioned before, AI will touch most every chip and there will never be enough performance or integrated memory so leading edge process and packaging technology is foundry critical, absolutely.

Samsung Foundry has always met customer needs by being ahead of the technology innovation curve and today we are confident that our gate-all-around (GAA)-based advanced node technology will be instrumental in supporting the needs of our customers using AI applications,” said Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics. “Ensuring the success of our customers is the most central value to our foundry services.”

The Samsung Foundry market breakdown for 2022 was not surprising:

  • Mobile 39%
  • HPC 32%
  • IoT 10%
  • Consumer 9%

Moving forward however HPC is expected to dominate the foundry business ( > 40% ) as AI takes more than their fair share of leading edge wafers.

The most significant announcement was that Samsung 2nm is on track to start production in 2025, which was the date given at the previous Samsung Foundry Forum. Staying on track with the published roadmap is a big part of foundry trust. Remember, if a fabless company is going to bet their company jewels on a foundry partnership they have to trust that the wafers will be delivered on time matching the PDK specifications.

Highlights include:
  • Expanded applications of its 2-nanometer (nm) process and specialty process
  • Expanded production capacity at its Pyeongtaek fab Line 3
  • Launched a new ‘Multi-Die Integration (MDI) Alliance’ for next-generation packaging technology

At the event, Samsung announced detailed plans for the mass production of its 2nm (horizontal nanosheet) process, as well as performance levels. Samsung, like Intel, are their own foundry customer so first production is with internal products versus external foundry customers. This of course is the advantage of an IDM foundry, developing your own silicon in concert with process technologies. Samsung has the added advantage of developing leading edge memories.

Samsung will begin mass production of the 2nm process for mobile applications in 2025, and then expand to HPC in 2026 with backside power delivery, and automotive in 2027. Samsung’s 2nm (SF2) process has shown a 12% increase in performance, a 25% increase in power efficiency, and a 5% decrease in area, when compared to its 3nm process (SF3). Mass production of the follow-on 1.4nm is slated for 2027.

TSMC overwhelming won the 3nm node with the N3X process family, however, the 2nm node is undecided. TSMC N2, Intel 18A, and Samsung 2nm are very competitive on paper and should be ready for external customers in the same time frame. It will all depend on how the PDKs proceed. According to the ecosystem, customers are looking at all three processes so it is a three horse race which is great for the foundry business. No one enjoys a one horse race except for that one horse.

The other big announcement was packaging, another advantage of an IDM foundry. Intel and Samsung have been packaging chips before foundries existed. Now they are opening up their packaging expertise to external foundry customers. We will be writing more about packaging later but it is a very big opportunity for foundries to empower customers.

For packaging Samsung announced the MDI Alliance in collaboration with partner companies as well as major players in 2.5D and 3D,  memory, substrate packaging, and testing. Packaging is now a very important part of the foundry business. With the advent of chiplets and the ability to mix and match die from different processes and foundries, packaging is a new foundry arms race and it is good to see three strong horses competing for our business.

This was an excellent networking event, the food is always great, and the Samsung people are very polite and professional. Samsung Foundry will be at DAC 2023 in San Francisco the week of July 9th. I hope to see you there.

Also Read:

Synopsys Expands Agreement with Samsung Foundry to Increase IP Footprint

Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023

A Memorable Samsung Event


Keysight at #60DAC

Keysight at #60DAC
by Daniel Payne on 06-27-2023 at 10:00 am

ads hsd hpc design cloud min

Keysight EDA will have a large presence at this year’s DAC in San Francisco July 9-13. For a better understanding of what’s happening with Keysight EDA at DAC I talked to my contacts to learn that they have three main messages this year:

• Automate
• Collaborate
• Innovate

Demos: Booth 1531

You may recall that Keysight acquired Cliosoft for their design data and IP management back in February 2023, so that fits into the collaborate category. On the automate and innovate points you can see demos of RF/uW and mmWave IC design using the PathWave Advanced Design System (ADS), and using HPC to accelerate EM and circuit simulations. Find out how Python scripting helps automate your IC design workflow.

Panels

On Monday, July 20th in the DAC Pavilion there’s a panel discussion on FaaS, from 2PM – 2:45PM, and it’s located on level 2 in the Exhibit Hall. Circuit simulations, SI and electromagnetic modeling can all be accelerated using HPC technology. Come and learn about “microservices” and how to avoid “cold start” issues.

Panelists are from Keysight, Rescale, Meta Reality Labs and Eviden, The moderator is Ben Jordan, from JordanDSP.

Design Cloud for cloud-based high-performance computing

This panel discussion takes place on Tuesday, July 11th, from 1PM – 1:45PM in the Transformative Technologies Theater, moderated by Natesan Vekateeswaran from IBM, with panelists from: Keysight, Ansys, Google, Microsoft. Most EDA tools were initially designed for desktop use, not cloud use. Hear about the journey taking EDA tools to cloud-optimized.

On the final day in the Exhibits you can learn from panelists at Keysight, BAE Systems, Raytheon Technologies and Microsoft. Wednesday, July 12th from 10:30AM – 11:15AM at the Transformative Technologies Theater. The DoD created the Rapid Assured Microelectronics Prototypes using Advanced Commercial Capabilities (RAMP) program. Cliosoft was the original EDA vendor in this program, now Keysight.

Tech Talk

Majid Ahad Dolatsara from Keysight is giving a tech talk on Tuesday, July 11th from 10:30AM – 11:15AM in the Transformative Technologies Theater. Learn how ML has been used for optimizing circuit routing, and NLP methods have extracted design information from text specifications. Hear about the techniques of supervised, unsupervised and reinforcement learning for EDA tools and flows.

Theatre Presentation

I’ve walked the exhibit area at many DACs, and one of the most welcome forms of relief is to simply sit down in a chair and take in a live presentation. Every hour there will be a theatre presentation in Keysight’s Booth 1531 to give you an overview of what they offer for RF/uW and mmWave IC designers in terms of automation as well as IP and design data management for collaboration and reuse. The presentation is both informative and entertaining, plus you get to rest those tired legs a bit.

Tuesday DAC Party

One of the best aspects of attending DAC is the social one, where you get to see and talk with your colleagues all in one place, and this year the party is on Tuesday, July 11th from 6PM – 9PM, on the Level 2 lobby area. Listen for the live music and watch for people holding drink glasses.

I Love DAC

Keysight is one of the sponsors of the annual I Love DAC, which means that you can attend several activities for free, like: Keynotes, SKYTalks, TechTalks, Theater, Exhibits, Networking, Training.

Hack@DAC

There’s a hardware security challenge contest, to find and exploit security-critical vulnerabilities in hardware and firmware, where Keysight is a sponsor. Form a team and be the winning hacker.

Customer Meetings

If you are an existing customer or new prospect interested in scheduling time with Keysight experts in their DAC booth,  submit your request online to reserve a meeting time.

Summary

The profile of Keysight has really grown over the years at DAC, and in 2023 I’d say that this is the most involved that I’ve ever seen their company. Discover how they are positioned by attending the three panel discussions or their Tech Talk. View two different demos at Booth 1531 and look for me at the Tuesday night DAC party.

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Transforming the electronics ecosystem with the component digital thread

Transforming the electronics ecosystem with the component digital thread
by Kalar Rajendiran on 06-27-2023 at 6:00 am

Complexity from Disaggregated Electronics Value Chain

The transformation of the vertically integrated electronics value chain to a disaggregated supply chain has brought tremendous value to the electronics industry and benefits to the consumers. This transformation has driven the various players to become highly specialized in order to support the market trends and demands of the marketplace, creating a highly complex and specialized electronics supply chain network.

While this transformation has helped deliver very advanced and highly complex electronics systems, information exchange still relies on outdated methods from decades ago. Thus, component manufacturers and system design companies still use PDF and Excel files to exchange information during the design and manufacturing phases of a product. These means of communication won’t go away, but it is high time they be augmented with high bandwidth, dynamic methods that more tightly bring together the nodes of the value chain, while speeding the delivery and ensuring the quality of data. To make this a reality, the electronics industry is embracing the adoption of component data exchange through a digital thread. A digital thread is the communications framework that allows a connected data flow and an integrated view of product data throughout the product life cycle– spanning ideation, realization, and utilization.

Siemens EDA recently published a whitepaper that examines how the emergent component digital thread will revolutionize the electronics industry by connecting all nodes of the value chain.

Industry Standard for Data Exchange

The component digital thread relies on an industry standard known as the JEDEC JEP30 Part Model. This standard, ratified in 2018, establishes requirements for exchanging part data in the electronics industry. The JEP30 Part Model defines the digital twin for electronic components, connecting the virtual and physical worlds across the value chain. It combines comprehensive component information into an industry-standard-based digital container, allowing seamless data exchange and integration throughout the product creation lifecycle. The adoption of this standard is a game-changer, enabling frictionless value and direct consumption by tools in the electronics industry.

Creating and Driving Value and Trust into the Supply Chain

The component digital thread empowers component manufacturers to provide accurate and intelligent data, eliminating errors and accelerating the design-in process. These threads contain embedded trust and supply chain intelligence, enabling better decision-making throughout the product lifecycle. The industry is embracing the JEDEC JEP30 Part Model standard to create high-bandwidth connections and leverage AI-enabled insights. As more tools become available to support the transition, component manufacturers are shifting towards part model representations to enhance collaboration and streamline processes.

Inserting Trust

As the shift towards digital twins of component data accelerates, establishing trust in the component information becomes crucial. Part models serve as complete digital representations of parts, and in the future, different sections of these part models may assimilate digital signatures to create an immutable ledger that builds trust throughout the design chain. Parts will have a “root of trust” tied to their digital certificates, verifying their authenticity and integrity. Similarly, at the product level, manufacturers will establish a “root of trust” through digital certificates that attest to the integrity of the manufacturing process. The digital thread is essential for enabling this trust-building process, as it ensures transparency and traceability throughout the supply chain.

Digital Data Sheets

The part model approach offers additional benefits in the form of interactive data sheets and application notes in digital form. With interactive data sheets, users can access 3D views of the package, interact with live test setups tailored to their specific application conditions, and evaluate real-time supply chain information. They can also access the latest ECAD and mechanical models derived directly from the source part model.

Interactive Virtual App Notes and Eval Boards

Component manufacturers can enhance the evaluation process by deploying cost-effective and instantly available virtual evaluation boards. These boards can be accessed directly from the manufacturer’s website, eliminating the need for logistics, assembly, and shipping. Virtual evaluation boards offer the advantage of being application-specific, allowing end customers to explore the capabilities of a component in a system context and address performance issues upfront.

Accelerating Resilient Electronics Systems Designs

By leveraging part models, first-pass success rates are improved as risks associated with time delays and human error are minimized. Part models enable advanced searches for specific component features, facilitating easier selection and incorporation into designs. Furthermore, the design capture process is transformed, significantly reducing the time required to capture complex designs. The overall impact is substantial time and budget savings, eliminating the need for extensive model content searching, resolving data integrity errors, decoding naming conventions, and avoiding unnecessary respins.

Summary

The electronics industry is undergoing a significant transformation by converting component data into industry-standard digital twins. This shift from PDF-based interactions to high-bandwidth, intelligent digital part model threads will unleash innovation and revolutionize the industry. It will accelerate the design process, increase profitability, and unlock the full potential of engineering teams. This digital transformation will have a profound impact on all stakeholders in the electronics value chain, enabling greater efficiency and fostering new levels of innovation.

The whitepaper will be a valuable read for everyone involved in the design and manufacturing of electronic products.

Also Read:

DDR5 Design Approach with Clocked Receivers

Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform

Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks


Ansys Revving up for Automotive and 3D-IC Multiphysics Signoff at DAC 2023

Ansys Revving up for Automotive and 3D-IC Multiphysics Signoff at DAC 2023
by Daniel Nenni on 06-26-2023 at 10:00 am

dac 2023 600x100

 

Highlights:

  • Ansys CTO Prith Banerjee will be delivering the Visionary Speaker opening address on Tuesday 11th
  • There will be technical presentations every hour in the Ansys Booth Theater (#1539)
  • Get yourself a complimentary sit-down breakfast and a discussion on automotive electronics by registering for the Ansys DAC Breakfast Panel on Tuesday morning
  • Register for some of the very limited seating at Ansys’ Customer Workshops with 3 technical tracks
  • Ansys customers have contributed over 22 technical papers to the DAC conference Engineering Track

In just a couple of weeks the 2023 Design Automation Conference and Exhibit will start on July 9th – 13th in San Francisco, and Ansys will be attending in full force. Ansys’ chief technology officer, Prith Banerjee, has been honored with an invitation to deliver the Visionary Speaker address at the opening of the conference on Tuesday morning. Prith will be sharing his insights on “Driving Engineering Simulation and Design with AI/ML” and the lessons of Ansys incorporating artificial intelligence and machine learning capabilities with its products.

The Ansys 40×40 booth (#1539) is one of the larger ones in this year’s Exhibit, with its major theme on latest multiphysics technology for 2.5D/3D-IC signoff. This includes Thermal Integrity, Electromagnetic Signal Integrity, and Structural Reliability (stress/warpage). The technology for multi-die, heterogeneous integration has been advancing by leaps and bounds as the semiconductor industry moves to this new design paradigm. Presentations on this and other topics are scheduled every hour in the Ansys DAC Booth Theater for any DAC attendee to sit down and ask questions of the experts presenting. Two information stations will be available for self-guided browsing through the full range of Ansys technology offerings or to engage with any of the Ansys support specialists standing by. Ansys is also sponsoring the Community Connection Zone (#1551) right next door to the Ansys booth where people can sit down, take a break, and relax with a coffee or a bite to eat.

The second theme at this year’s Ansys booth responds to the heightened customer interest around Automotive Electronics. The automotive sector is undergoing tectonic changes as manufacturers rush to adapt to 3 fundamental drivers of innovation: electrification of the power train, autonomous driving, and the over-the-air connected vehicle.  Each of these forces are increasing the electronic and semiconductor content in future vehicles. This aligns with Ansys’ deep and broad set of Automotive solutions; from high performance compute (HPC) chips for AI/ML algorithms, to battery management, mechanical reliability, crash test simulation, lighting, and more.

This year’s edition of the traditional Ansys DAC Breakfast Panel will dive more deeply into the Automotive theme. This event serves a full complimentary breakfast to attendees who register for the panel discussion in the Marriott Marquis on Tuesday July 11th at 7:00am – 8:30am (room Golden Gate B). The topic of this year’s panel discussion is “Driving Design Excellence: The Future of Automotive Electronics”. The discussion will be moderated by Ansys senior chief technologist for automotive Judy Curran who has over 30 years of experience in the automotive industry. A roster of panelists from Rivian, Intel, Synopsys and more. Attendees must register for the Breakfast Event at the Ansys DAC webpage.

The impressively broad usage of Ansys products across the semiconductor industry has once again enabled Ansys customers to submit an equally impressive 22 technical papers that have been accepted by the DAC Conference and will be presented in the Engineering Track. In addition, Ansys product specialist Lang Lin will be joined by researchers from the University of Kobe and the University of Maryland to deliver a tutorial on “Side-Channel Analysis: from Concepts to Simulation and Silicon Validation” on Monday afternoon.

Ansys is organizing a series of technical Customer Workshops in the Ansys Booth conference room. The workshops are 2-hour sessions organized into several tracks where several Ansys customers present detailed technical summaries of their experiences and successes in applying Ansys technology for their production designs. The seating for these valuable workshops is extremely limited and you must reserve your seat as early as possible.

Finally, Ansys is fully engaged with the many discussions and panels that make DAC the valuable must-go event of the year:

So please make sure to register to attend the conference and join Ansys at DAC. Register for one of our exclusive events or schedule a meeting as we reach out to our customers and partners in advancing the state-of-the-art in Electronic Design Automation.

Also Read:

Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023

WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC design technology

Chiplet Q&A with John Lee of Ansys


Assessing EUV Wafer Output: 2019-2022

Assessing EUV Wafer Output: 2019-2022
by Fred Chen on 06-26-2023 at 6:00 am

Assessing EUV Wafer Output 2019 2022

At the 2023 SPIE Advanced Lithography and Patterning conference, ASML presented an update on its EUV lithography systems in the field [1]. The EUV wafer exposure output was presented and is shown below in table form:

From this information, we can attempt to extract and assess the EUV wafer output per quarter. First, since there are quarters with no reported output, we will interpolate with a quartic polynomial fit. A quartic polynomial is used as best fit because five data points are already available.

Cumulative EUV wafers exposures from 2019 to 2022. Quarter 0 corresponds to before Q1 2019.

For each quarter, we can calculate the average wafers per day per EUV tool, by taking the difference between wafers exposed in a pair of consecutive quarters, dividing by the average of the number of available systems of the two quarters, then dividing by 90 days. The resulting trend is shown below:

Average wafers per day per EUV system, for each quarter from 2019 to 2022.

The average EUV exposures per tool broke through 1000 wafers per day in a couple of quarters, but has most recently dropped to 904 wafers per day, or less than 40 wafers per hour. This looks like a surprisingly low throughput, compared to reported values of 120-180 wafers per hour [1], what could this mean?

A first possibility is that the EUV tools are simply not used that often, and are idle most of the time. A second possibility is that the tools are in maintenance most of the time.  However, uptime of >90% has been reported [2]. A third possibility would be higher doses, possibly over 100 mJ/cm2, to address stochastic effects [3]. However, this does seem to go counter to all the work done on achieving published throughput goals. Yet another possibility is that the graph does not count multiple layer exposures on a wafer separately. Hence, 15 EUV layers at 120 wafers per hour each layer would look like 8 wafers per hour, for example. However, compared to ~40 wafers per hour on average, this number is an even lower output rate! Where is the discrepancy? Research and development (R&D) wafers have not been considered. If only 20% of all EUV wafers run were for production, then the numbers could work out more reasonably. A possible breakdown would be below:

An example of EUV use breakdown for Q4 2022. In this case, uptime is allocated as 20% for production, 20% for R&D, 60% idle. The resulting monthly production volume is 933,333 wafers/month. Production assumed to run wafers at 120 WPH, R&D at 128 WPH.

For reference, TSMC monthly output is reported as up to 150,000 wafers/month [4]. If the monthly production volume is not over 900,000 wafer/month but actually ~250,000 wafers/month (so that TSMC’s portion is 60% of global total), the fraction in production needs to be ~5.3%. With the same wafer run rates, the R&D and idle time fraction don’t change appreciably.

In this example, uptime is allocated as 5.3% for production, 28% for R&D, 67% idle. The resulting monthly production volume is 247,333 wafers/month. Production assumed to run wafers at 120 WPH, R&D at 128 WPH.

The noticeable difference is the number of layers per production wafer. On average, it has increased to 57. This must include the multiple exposures for a given layer for many cases. For example, 14 layers with four exposures, and 1 layer with single exposure, to give 15 EUV layers and 57 EUV exposures total.

In both of the above examples, yield loss is not considered. If we assume that the monthly production volume is actually 420,000 wafers, but that yield loss had brought it down to 250,000, the production use is 9%. The 33 EUV exposures could come from 6 layers with four exposures, and 9 layers with single exposure, to give 15 EUV layers total.

In this example, uptime is allocated as 9% for production, 26% for R&D, 65% idle. The resulting monthly production volume is 420,000 wafers/month. Production assumed to run wafers at 120 WPH, R&D at 128 WPH.

The picture that emerges from considering the above scenarios is that there is substantial (>60%) idle time, some yield loss, and a good deal of multiple exposures (multipatterning) for some EUV layers, if we assume the EUV systems are running at least 120 wafers per hour. Otherwise, if the tools are not idle or under maintenance or repair for that much time, the actual running throughput is often (on average) <40 wafers per hour. Very high doses to address stochastic effects naturally result in such low throughputs.

References

[1] C. Smeets et al., Proc. SPIE 12494, 1249406 (2023).

[2] https://semiengineering.com/euv-challenges-and-unknowns-at-3nm-and-below/

[3] https://semiengineering.com/finding-predicting-euv-stochastic-defects/

[4] https://www.digitimes.com/news/a20220323PD215.html

This article first appeared in LinkedIn Pulse: Assessing EUV Wafer Output: 2019-2022

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Podcast EP166: How iDEAL Semiconductor is Revolutionizing Power Device Design & Manufacturing

Podcast EP166: How iDEAL Semiconductor is Revolutionizing Power Device Design & Manufacturing
by Daniel Nenni on 06-23-2023 at 10:00 am

Dan is joined by Ryan Manack, Vice President of Marketing for iDEAL Semiconductor. Prior to iDEAL Ryan spent 15 years at Texas Instruments which I consider one of the most influential companies in the history of semiconductors.

Ryan describes SuperQ, the unique core technology platform of iDEAL Semiconductor. Using the approach defined by SuperQ, advanced power devices can be designed and built with standard CMOS manufacturing technology, avoiding the need to utilize alternate technology platforms that are not as mature or reliable. The result is advanced capabilities with current technology.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Efabless Celebrates AI Design Challenge Winners!

Efabless Celebrates AI Design Challenge Winners!
by Daniel Nenni on 06-23-2023 at 6:00 am

Efabless AI Challenge SemiWiki

The first AI Generated Open-Source Silicon Design Challenge invited participants to use generative AI to design an open-source silicon chip and tape it out in just three weeks. The contestants were required to create Verilog code from natural language prompts, and then implemented their designs using the chipIgnite platform and the OpenLane open-source design flow.

The challenge was a success, with participants from all over the world, some of whom had never designed a chip before, and virtually none of whom had previously used OpenLane. Six designs successfully met all the criteria, and in a very close call, three designs were declared to be the winners by our outside panel of judges based on pre-determined criteria including design completeness, documentation, technical merit, and community interest.

The first-place winner of the contest was QTCore-C1 by Hammond Pearce at New York University. The design is a co-processor that can be used for many applications, such as predictable-time I/O state machines for PIO functions as seen on some microcontrollers developed using the Chip-Chat methodology that the NYU team has published.

The second-place winner of the contest was Cyberrio by Xinze Wang, Guohua Yin, and Yifei Zhu at Tsinghua-Berkeley Shenzhen Institute. This design is a RISC-V CPU, implemented with Verilog code produced via a series of prompts given to ChatGPT-4.

The third-place winner of the contest was Asma Mohsin at Rapid Silicon. The design is a Model Predictive Control (MPC) that is used to predict future behavior and optimize control actions for a regulator control circuit provided in MATLAB code to ChatGPT-4 and then implemented with prompts in Verilog.

The designs were all very impressive, and all the participants successfully demonstrated how tools such as ChatGPT, Bard and others can revolutionize chip design by automating many of the tedious tasks involved in the development process, making it simpler, faster and more efficient.

Efabless will now fabricate the three winning designs on its chipIgnite shuttle. The winners will receive packaged parts and evaluation boards, valued at $9,750 each. In addition, all participants with qualifying designs will receive a free evaluation board and one of the winning AI-generated chips.

Efabless will shortly be featuring videos from the various winning designs and teams describing their experience and lessons learned.

Efabless will also soon release information about the second AI-Generated Design Challenge. The challenge will take place over the summer, with tapeouts expected in September. Stay tuned!

About Efabless

Efabless offers a platform applying open source and community models to enable a global community of chip experts and non-experts to collaboratively design, share, prototype and commercialize special purpose chips. Nearly 1,000 designs and 450 tapeouts have been executed on Efabless over the past two years. The company’s customers include startups, universities, and research institutions around the world.

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Why Generative AI for Chip Design is a Game Changer

Join the AI Generated Open-Source Silicon Design Challenge!

A User View of Efabless Platform: Interview with Matt Venn


Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges

Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges
by Nanette Collins on 06-22-2023 at 10:00 am

CEO Outlook #2
CEO Outlook participants, front row (l-r): Niels Faché, John Lee and Prakash Narain; back row (l-r): Scott Seiden, Director Strategic Marketing at Keysight EDA Portfolio, Dean Drako, John Kibarian, Ed Sperling, Bob Smith, Executive Director of the ESD Alliance, Simon Segars and Joe Sawicki. Source: Julie Rogers, Director of Marketing for SEMI Americas and the ESD Alliance

Chances are anyone who attended the CEO Outlook will say it was an engaging, entertaining and enlightening view of the chip design space, though CEO Outlook may be a misnomer as four of the seven panelists had C-Suite titles other than CEO.

Regardless, the collective view was optimistic, though caution prevailed as the economic downturn could bring unpredictable challenges. The discussion was kept on point by moderator Ed Sperling, editor in chief of Semiconductor Engineering. SEMI’s ESD Alliance sponsored the event and it was hosted by Keysight.

As expected, the conversation covered topical subjects like heterogeneous integration, chiplets, education and manufacturing, but continued to drift back to the role AI is playing in the changing industry dynamics. John Kibrarian, President and CEO of PDF Solutions and a member of the ESD Alliance Governing Council, reinforced the role of AI, predicting the semiconductor industry will grow to $1 trillion by 2030 propelled by increasing AI computer needs.

AI’s impact on the design tool market and the industry cannot be overstated, agreed Dean Drako, President and CEO of IC Manage and former Governing Council member, who believes it will help accelerate productivity. It will be both a challenge with the massive amount of data that AI will generate, he warned.

AI puts the industry in an amazing space to monetize what EDA is doing as well as being able to transform the world, allowed Joe Sawicki, Executive Vice President of Siemens EDA and a Governing Council member. AI comes with a host of chip design-related questions that he quickly ticked off –– What if generative AI comes into the design space and how would it be useful or innovative? How would it discover what’s been done? What’s being pulled together in compelling ways? He finished with the promise: “It’s going to be an amazing ride in terms of how we take advantage of these opportunities.”

John Lee, GM and VP at Ansys and a newly elected ESD Alliance Governing Council member, chose a different angle and said heterogenous integration is both an opportunity and a challenge. Multiphysics around 3D ICs is a big challenge and an opportunity. So too are heterogeneous IC designs.

Kibarian took the manufacturing perspective and sees opportunities to improve production flows. He responded to Lee’s comments by adding heterogeneous development systems will lead to manufacturing challenges. The system package makes manufacturing challenging because the value isn’t in the wafer fab and assembly is a challenging process now due in many ways to geopolitics. The test points are much more complex.

Chiplets and the heterogeneous design have physical challenges that could be electromagnetic, thermal or electrothermal, continued Niels Faché, VP and GM at Keysight EDA and a newly elected Governing Council member. While tools are available, it’s critical that they are applied to solve the problems they’re well suited for and integrated in an overall portfolio, he added. Technologies may be available but may need to be modified for chiplets and 3D ICs. They also need to be in an integrated workflow and so they are not going from one highly specialized group to another specialized group causing data transfer problems. Faché’s advice to designers is to make sure they have the right tool for the right job and those tools are integrated in an overall workflow.

At Faché’s mention of chiplets, Sperling turned to Simon Segars, a former member of the ESD Alliance Governing Council, for his insights on the emerging chiplets market. Segars acknowledged the chiplet momentum and the complexity around chip and physical IP, libraries and memories and in-place blocks for chiplet design. He foretells a shift will be required –– a practical way forward once designers are comfortable using chiplets.

Prakash Narain, President and CEO of Real Intent and a Governing Council member, is a verification expert and firmly believes opportunities are available to further automate shift left or moving verification up much earlier in design. Since it’s a design step, the designer must get involved in this process. Due to time pressures, a verification vendor has to create the best experience for success. The challenge is technology innovation and the industry is responding, he affirmed, by investing in technology and innovation to design the user experience while expanding the size of the business space and engineering innovation.

As the discussion wound down, one attendee asked panelists what they would tell top U.S. policy makers, given the chance. Drako jumped in, describing his chance to talk recently to President Biden. “Basically, I made three points,” he said. “One was that we need education in the United States and that we need to invest so that we are top of the world in education because that’s how we’re going to compete in the long run. That’s how we competed over the last 500 years when we invented the first public education system. Second, AI is going to change video surveillance and we need to invest, reinvest as a country in manufacturing.”

Lee perhaps summed up the discussion best by noting that all the challenges the panelists talked about cannot be solved immediately. It takes a village to solve them or the idea of open extensible platforms as a form of a workable model. “SaaS-based systems talking to each other is the future. We have to embrace all this. Then we can solve more of the problems we face.”

The ESD Alliance Membership Drive

‘Tis the membership drive season for the ESD Alliance, an industry organization devoted to promoting the value of the electronic system and semiconductor design ecosystem as a vital component of the global electronics industry. It offers programs that address technical, marketing, economic and legislative issues affecting the entire industry. For more information, visit the ESD Alliance website. Or contact Bob Smith, Executive Director of the ESD Alliance, at bsmith@semi.org or Paul Cohen, ESD Alliance’s Senior Manager, at pcohen@semi.org.

Follow SEMI ESD Alliance

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