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2024 Outlook with Da Chuang of Expedera

2024 Outlook with Da Chuang of Expedera
by Daniel Nenni on 03-07-2024 at 6:00 am
Categories: Expedera, IP

Da Chuang 2

Expedera provides customizable neural engine semiconductor IP that dramatically improves performance, power, and latency while reducing cost and complexity in edge AI inference applications. Da is co-founder and CEO of Expedera. Previously, he was cofounder and COO of Memoir Systems, an optimized memory IP startup, leading to a successful acquisition by Cisco. At Cisco, he led the Datacenter Switch ASICs for Nexus 3/9K, MDS, CSPG products. Da brings more than 25 years of ASIC experience at Cisco, Nvidia, and Abrizio. He holds a BS EECS from UC Berkeley, MS/PhD EE from Stanford. Headquartered in Santa Clara, California, the company has engineering development centers and customer support offices in the United Kingdom, China, Japan, Taiwan, and Singapore.

Tell us a little bit about yourself and your company.

My name is Da Chuang, and I am the co-founder and CEO of Expedera. Founded in 2018, Expedera has built our reputation of providing the premier customizable NPU IP for edge inference applications from edge nodes and smartphones to automotive. Our Origin NPU, now in its 4thgeneration architecture, supports up to 128 TOPS in a single core while providing industry-leading processing and power efficiencies for the widest range of neural networks including RNN, CNN, LSTM, DNN, and LLMs.

-What was the most exciting high point of 2023 for your company?

>>2023 was a year of tremendous growth for Expedera. We added two new physical locations to our company, Bath (UK) and Singapore. Both of these offices are focused on future R&D, developing next-generation AI architectures, plus other things you’ll be hearing about in the months and years to come. While that is very exciting for us, perhaps the most significant high point for Expedera in 2023 was our customer and deployment growth. We started the year with the news that our IP had been shipped in over 10M consumer devices, which is a notable number for any Semiconductor IP startup. Throughout the year, we continued to expand our customer base, which now includes worldwide Tier 1 smartphone OEMs, consumer devices chipsets, and automotive chipmakers. Our NPU solution is recognized globally as the best in the market, and customers come to us when they want the absolute best AI engine for their products.

-What was the biggest challenge your company faced in 2023?

>>The biggest challenge in 2023, along with the biggest opportunity, has been the emergence of Large Language Models (LLMs) and Stable Diffusion (SD) in the edge AI space. LLMs/SD represent a paradigm shift in AI – they require more specialized processing and more processing horsepower than the typical CNN / RNN networks most customers were deploying in 2022 and prior. The sheer number of LLM/SD-based applications our customers are implementing has been incredible to see. However, the main challenge of LLMs and SD on the edge has been allowing those networks to run within the power and performance envelope of a battery-powered edge device.

-How is your company’s work addressing this biggest challenge?

>> Our customers want to feature products that are AI-differentiated; products that bring real value to the consumer with a fantastic user experience. However, significant hits to battery life aren’t accepted as part of the user experience. As we integrated LLM and SD support into our now-available 4th generation architecture, our design emphasis was focused on providing the most memory efficient, highest utilization, lowest latency NPU IP we could possibly build. We drilled in the underlying workings of these new network types; data movements, propagations, dependencies, etc… to understand the right way to evolve our both our hardware and software architectures to best match future needs. As an example of how we’d evolved, our 4th generation architecture features new matrix multiplication and vector blocks optimized for LLMs and SD, while maintaining our market-leading processing efficiencies in traditional RNN and CNN-style networks.

-What do you think the biggest growth area for 2024 will be, and why?

>> One of our biggest growth areas is 2024 is going to be supporting an increasing variety of AI deployments in automobiles. While most are likely familiar with the usage of AI in the autonomous driving stack for visual-based networks, there are a lot more opportunities and uses that are emerging. Certainly, we’re seeing LLM usage in automobiles skyrocketing, like many other markets. However, we’re also seeing increased usage of AI in other aspects of the car – driver attentiveness, rear seat passenger detection, infotainment, predictive maintenance, personalization, and many others.  All of these are aimed at providing the consumer with the best possible user experience, one of the key reasons for the implementation of AI. However, the AI processing needs of all of these uses vary dramatically, not only in actual performance capabilities but also in the types of neural networks the use case presents.

-How is your company’s work addressing this growth?

>> Along with the aforementioned LLM and SD support, Expedera’s 4th generation architecture is also readily customizable. When Expedera engages in a new design-in with a customer, we seek to understand all the application conditions (performance goals, network support required, area and power limitations, future needs, and others) so that we can best customize our IP – essentially, give the customer exactly what they want without having to make sacrifices for things they don’t. If the customer desires a centralized, high-performance engine handing a number of different uses and support for a variety of networks, we can support that. If the customer wants to deploy decentralized engines handling only specific tasks and networks, we can support that as well – or anywhere in between. And this is all from the same IP architecture, done without time-to-market penalties.

-What conferences did you attend in 2023 and how was the traffic?

>>Expedera exhibits at a targeted group of conferences focused on edge AI, including but not limited to the Embedded Vision Summit and AI Hardware & AI Summit, as well as larger events like CES. Traffic at these events seemed on par with 2022, which is to say respectable. AI is obviously a very hot topic within the tech world today, and every company is looking at ways to integrate AI into their products, workflows, and design process. Accordingly, we’ve seen an ever-increasing variety of attendees at these events, all of whom come with different needs and expectations.

-Will you attend conferences in 2024? Same or more?

>>2024 will likely see a slight expansion of our conference plans, especially those focused on technology. As part of the semiconductor ecosystem, Expedera cannot afford to exist in a vacuum. We’ve spoken at past events about our hardware and software stacks, as well as implementations like our security-centric always-sensing NPU for smartphones. This year, we’ll be spending a lot of our time detailing edge implementations of LLMs, including at upcoming conferences later this Spring. We look forward to meeting many of you there!

Also Read:

Expedera Proposes Stable Diffusion as Benchmark for Edge Hardware for AI

WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments

Area-optimized AI inference for cost-sensitive applications

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Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation

Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation
by akanksha soni on 03-06-2024 at 2:00 pm
Categories: Ansys, Inc., EDA, Events

Ansys and Intel Foundry Direct 2024

In the dynamic realm of technological innovation, collaborations and partnerships often serve as catalysts for groundbreaking advancements. Continuing along this trajectory, Ansys, a global leader in engineering simulation software, has forged a partnership with Intel Foundry to enable multiphysics chip design. The two companies share the same set of values: a commitment to science and innovation. To further strengthen this unprecedented collaboration, Ansys proudly participated in the Intel Foundry Direct 2024 event that happened on 21st February in San Jose, USA.

At the event, John Lee, Vice President and General Manager of the Electronics, Semiconductors, and Optics business unit at Ansys, delivered an Executive Keynote address, along with Keynotes from the other Big-4 EDA suppliers: Synopsys, Cadence, and Siemens. Lee started his talk by eloquently discussing the transformative journey of the semiconductor industry and its pervasive influence across diverse sectors such as high-tech, healthcare, and automotive. He emphasized the critical role of semiconductors in meeting the escalating technological demands of the modern world.

In addressing the evolving demands of the modern world, Lee highlighted how current chip design methodologies are insufficient for handling today’s intricate 2.5D/3D-IC designs. Lee identified three primary challenges facing the EDA industry in crafting intricate architectural chip designs: multi-physics, multi-scale, and multi-organizational challenges. He calls these the 3Ms of 2.5D/3D-IC design.

  • Multi-physics hurdles arise from novel physical effects that are not within the experience of most monolithic chip designers. Lee gave Thermal Integrity, EM Signal Integrity, and Mechanical/Structural Integrity as examples of new multiphysics challenges.
  • Multi-scale challenges manifest due to the blurred boundaries between chip, package, and system design. Multi-die assemblies involve the designer at the nanometer device scale, the micrometer chip layout scale, the millimeter packaging scale, all the way to the cm/m system scale. This multi-scale reality across 6 orders of magnitude means that physical effects fundamentally change how they behave at each level. Thermal was given as a good example of a physical simulation that has very different requirements at the chip, package, and system levels.
  • Multi-organizational challenges emanate from the necessity to revamp traditional company structures to align with the demands of contemporary design. This may be the most intractable problem as companies try to fit the physics to the org chart rather than adapting the org chart to match the physics requirements.

Lee suggests that by adopting strategic thinking, the challenges of multi-physics, multi-scale, and multi-organizational aspects can be turned into valuable opportunities. A considered approach is t suggest the three ‘P’s – physics, platforms, and partnerships – as keys to unlocking the complete benefits arising from the transformative shifts in the industry. John Lee highlighted Ansys’ multiphysics broad and mature array of physics simulation solutions, designed to equip designers with the tools necessary to overcome the hurdles of modern chip design.  He stressed the need for the EDA industry to provide open and extensible platforms that allow customers to bring together the best-in-breed solutions from the entire industry and enable these on the cloud.

In a strategic collaboration, Ansys has recently partnered with Intel to deliver multiphysics signoff solutions tailored for Intel’s innovative 2.5D chip assembly technology. Ansys was able to list its products as certified by Intel in supporting their cutting-edge technology for 18A ribbonFETs, Power Vias for backside power delivery, and EMIB (Embedded Multi-die Interconnect Bridge) to establish flexible connections between multiple dies without relying on through-silicon vias (TSVs).

As another example of successful partnership in the EDA industry, John Lee gave the example of the 3-way collaboration between Intel, Synopsys, and Ansys to solve the multiphysics challenge that links IR-drop and timing closure. The joint solution combines golden signoff technology from both companies to deliver IR-STA and IR-ECO integration flow.

The entire event was exciting and high-energy, devoid of any dull moments. Pat Gelsinger, the Chief Executive Officer at Intel, infused the gathering with his visionary outlook for the Intel foundry and a conviction that Moore’s Law is far from dead. He articulated a compelling vision to catapult this iconic company, reinstating its pivotal position in the realm of technology. Gelsinger’s aim was not merely to revitalize Intel but also to spearhead the restoration of Western chip manufacturing on a grand scale. His vision emphasized the creation of a resilient, sustainable, and trusted supply chain, signaling a strategic commitment to a future marked by innovation and reliability.

Over 30 partners, including the ARM, UMC, MediaTek, and Broadcom took part in the Intel Foundry Direct event. Intel orchestrated an outstanding showcase, featuring special speeches from well-known names in the industry such as Sam Altman, Co-founder and CEO of OpenAI, Secretary Gina M. Raimondo, United States Secretary of Commerce, and Satya Nadella, Chairman and Chief Executive Officer of Microsoft.

In conclusion, the event hosted by Intel Foundry stood out as a remarkable gathering, uniting professionals from various sectors of the semiconductor industry to share insights and envision the future. John Lee’s notable presence underscored the robust partnership between Ansys and Intel. As the collaborative efforts between simulation and fabrication continue to evolve, the Ansys-Intel alliance is poised to make a lasting impact on the technological landscape, pushing boundaries and serving as inspiration for the next wave of breakthroughs.

Learn more about the multiphysics analysis and simulation solutions offered by Ansys here: Ansys Semiconductor Solutions | Datasheet

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Keynote Speakers Announced for IDEAS 2023 Digital Forum

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Accelerate AI Performance with 9G+ HBM3 System Solutions

Accelerate AI Performance with 9G+ HBM3 System Solutions
by Kalar Rajendiran on 03-06-2024 at 10:00 am
Categories: AI, Alphawave Semi, IP

HBM3 PHY and Controller Memory Solution

In the technology realm of artificial intelligence (AI) and high-performance computing (HPC), the demand for higher throughput and efficiency has never been greater. To meet these evolving demands, innovative memory solutions have emerged as critical enablers, paving the way for transformative advancements in computing capabilities. Among these solutions, High Bandwidth Memory (HBM) technology has risen to prominence, offering unparalleled performance, efficiency, and scalability.

Alphawave Semi recently hosted a webinar on the topic of accelerating AI performance with HBM3+ systems solutions and Alphawave Semi’s comprehensive IP offerings enabling it. The webinar also covered the inherent challenges in implementing HBM3 technology and the system challenges to overcome.

AI Disruption and the Need for Higher Throughput

The AI revolution has ushered in a new era of computing, where machine learning algorithms power everything from virtual assistants to autonomous vehicles. These AI applications rely heavily on data-intensive tasks such as deep learning and neural network training. As AI algorithms demand rapid access to vast datasets for real-time decision-making, they place immense strain on memory systems. Memory-centric architectures are an ideal choice for unmatched levels of bandwidth and energy efficiency for such applications.

Motivation for HBM Memory

Traditional memory architectures, such as DDR and GDDR, have long been the backbone of computing systems. However, the exponential growth of AI workloads has exposed their limitations in handling vast amounts of data with low latency. Traditional memory architectures struggle to keep pace with the demands of AI and HPC workloads, leading to performance bottlenecks and inefficiencies. HBM memory addresses this challenge by stacking multiple memory dies vertically, dramatically increasing memory bandwidth while minimizing power consumption and footprint.

Components in a HBM System

A comprehensive memory system comprises several critical components, each playing a vital role in ensuring optimal performance, power efficiency and reliability. These components include the HBM memory dies, physical layer (PHY), controller, interposer, and packaging techniques. The PHY serves as the interface between the memory dies and the rest of the system, while the controller manages data transfer and access. Interposers provide the necessary connections between memory dies, enabling high-speed communication, while advanced packaging techniques ensure thermal management and signal integrity. The integration of these components into a cohesive system architecture is essential for achieving optimal performance and reliability in AI and HPC applications. Alphawave Semi’s expertise in these components enables customers to deploy robust and efficient HBM memory systems that meet the demands of AI and high-performance computing workloads.

System Challenges: Overcoming Hurdles to Adoption

Despite its transformative potential, the adoption of HBM memory presents several challenges, including thermal dissipation, signal integrity, and power delivery. As memory bandwidth increases, so too does the need for efficient cooling solutions to dissipate heat generated by high-speed data transfer. Signal integrity becomes paramount to ensure reliable communication between memory dies, while optimized power delivery architectures are essential to meet the stringent power requirements of AI applications. Managing heat dissipation, mitigating signal distortion, and optimizing power distribution are critical considerations in designing HBM-based systems. Addressing these challenges requires innovative solutions and close collaboration between chip makers, memory vendors, and package technology providers.

Alphawave Semi addresses these challenges through continuous research and development, providing customers with the tools and expertise needed to overcome system-level obstacles and unlock the full potential of HBM memory technology.

Alphawave Semi IP Offerings

Alphawave Semi offers a comprehensive suite of HBM IP solutions tailored to meet the diverse needs of AI and HPC applications. From high-performance HBM PHY and Controller IP to advanced interposer and package design solutions, Alphawave Semi provides the essential building blocks for creating cutting-edge computing systems. By delivering best-in-class PHY and controller IP, Alphawave Semi enables customers to optimize memory subsystem performance, scalability, and power efficiency for their specific application requirements.

What’s Coming Next with HBM4

Looking ahead, HBM4 promises to further elevate the performance and efficiency of memory-centric architectures. HBM4 will enable even faster and more energy-efficient AI and high-performance computing systems. As the industry continues to innovate and evolve, HBM4 represents the next frontier in memory technology, driving advancements in computing capabilities. Alphawave Semi is at the forefront of HBM4 development, driving innovation and shaping the next generation of memory technology.

Summary

HBM memory solutions offer unparalleled performance, efficiency, and scalability, making them indispensable components of modern computing systems. With Alphawave Semi’s expertise and industry-leading IP offerings, semiconductor companies can harness the full potential of HBM memory to accelerate innovation and drive the next wave of AI disruption. By addressing the challenges of AI disruption, empowering system designers with advanced solutions, and driving the development of future technologies like HBM4, Alphawave Semi is shaping the future of computing and unlocking new possibilities for AI and HPC applications.

The entire webinar can be accessed on-demand here.

For more details about Alphawave Semi’s HBM related IP offerings, visit http://www.awavesemi.com/silicon-ip

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Alphawave Semiconductor Powering Progress

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Siemens Promotes Digital Threads for Electronic Systems Design

Siemens Promotes Digital Threads for Electronic Systems Design
by Bernard Murphy on 03-06-2024 at 6:00 am
Categories: EDA, Siemens EDA

Digital threads min

Many years ago, I remember discussions around islands of automation/silos. Within the scope of any given silo there is plenty of automation to handle tasks relevant to that phase. But managing the full lifecycle from concept through manufacturing to field support must cross between silos, and those transitions are not as clean and automated. Over time more attention was paid to merging silos, through M&A and tighter integration, so now there are fewer but still bumpy and incompletely automated transitions.

Courtesy Siemens

The merging strategy will only take us so far. OEM system architecture, digital design, validation, manufacturing, and OEM product lifecycle management live in worlds which are too different to be pulled into one over-arching platform. Better connecting these phases in the lifecycle must rely on new interoperability standards and ideas. In the ideas department, Siemens proposes a concept of digital threads to interconnect data between silos.

What is a digital thread?

As Siemens puts it:

(Digital threads) collect, integrate, and manage data across the different stages of a product’s lifecycle. The goal is to then to harness that data in more advanced and interactive ways, which is achieved through a digital twin. While the digital thread provides a structured pathway of data across the lifecycle, the digital twin utilizes this data to dynamically mirror the real-world state, behavior, and performance of a particular product.

The digital twin is the engine to mirror the behaviors of a real-world capability (chip, car, factory), and digital threads are bi-directional data pathways weaving through the twin all the way from architecture to deployment. These act as a common source of truth between different product development and manufacturing/deployment phases, connecting both downstream and upstream, aiming to keep all phases through the lifecycle in sync with the most current expectations, assumptions, and implementation choices.

As described in their whitepaper,  Siemens divides digital thread types into those originating or centered in architecture, components, design data, verification, and manufacturing/deployment. Remember that all these threads connect through the digital twin model (enabling shift-left design and optimization) and to the physical implementation (enabling cross correlation between the model and real-world prototype/deployment behavior).

The architecture, component, and design data threads

For me a perfect example (though not the only example) of the kind of data for which a thread makes sense in architecture is for traceability, a topic of great importance in automotive, aerospace and defense among other domains. Here the goal is to trace compliance with original OEM requirements, all the way through the lifecycle. And conversely to reflect unavoidable non-compliant changes made in design, so these become visible and actionable by all stakeholders through the lifecycle. Today much of this is accomplished through human review of natural language documents and spreadsheets.  More sophisticated traceability systems aim for better mechanized compliance checking so that for example a requirement is matched to a design feature (with change notices if required) and to tests to validate compliance.

A second thread connects component data through the lifecycle. In component design, significant detail is generated for functional behavior, electrical, thermal, and other characteristics. After manufacturing, this data is heavily abstracted into PDF datasheets, losing almost all of the detail that an OEM might sometimes need to see, forcing information communication back to the stone age through human-only readable documents. System developers must craft their own databases to attempt (incompletely and inaccurately) to capture some of this detail from other documents and to add their own metrics such as cost and sourcing risk. Standards such as JEDEC JEP30 Part Model Guidelines aim to upgrade from this mess, to make a true component data thread possible. Another very important factor here is trust and (again) traceability for components. A digital thread can be signed, unlike the mess of documents on which we currently rely.

The design thread as I read it in this white paper primarily connects across the system implementation, from multi-die designs, PCB, module, and full electronic system, although I imagine similar value would extend to domain specific SoC design as a component in the overall system. This thread connects electronics, electrical and MCAD to provide a single source of truth for all requirements at this level, to guide design (including cabling), multiphysics analysis, EMC and even security. It also governs accessibility requirements so that sensitive data is available only to those who have been approved to have access to that data.

The verification and manufacturing/deployment threads

For the verification thread, emphasis in this white paper is on the system above the chip/chiplet level and on physical, parametrics and compliance. One example here is full system optimization based on AI methods, in sync with offerings from other vendors. The Siemens solution is called HyperLynx Design Space Exploration, which I’m guessing uses some form of automated Design of Experiments technique through covering arrays (I have talked about this elsewhere). The other important aspect of verification here is traceability, which I mentioned earlier. Mechanized traceability enables repeated and accurate checks against requirements derived directly from the original OEM requirements. This also enables checks to trigger automatically on a design checkin, facilitating continuous integration and deployment (CI/CD) for faster response time to changes.

For the manufacturing (and deployment) thread, the authors point out that while there are well-established standards and processes in support of handing off designs to manufacturing, there is no standardized feedback loop for issues discovered in manufacturing, such as product yield or component solderability. Nor is there a standardized mechanism to feed field discoveries back into the digital twin. We already know that reproducing post-silicon failures in a digital twin is much easier if a trace of circumstances leading up to the failure is available. Supporting post-manufacturing debug on a twin should be a priority at the board/system level as much as at the SoC level. Thinking further ahead, the paper also mentions growing importance of sustainability and recyclability; both concerns will inevitably reach back into earlier stages in the lifecycle chain.

Nice paper with much food for thought. You can access the paper HERE.

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Designing for Security for Fully Autonomous Vehicles

Designing for Security for Fully Autonomous Vehicles
by Kalar Rajendiran on 03-05-2024 at 10:00 am
Categories: Analytics, Automotive, EDA, IoT, Security, Siemens EDA

OSI Seven layer model for securing network communication

With the advent of IoT devices, vehicles have become increasingly interconnected, offering enhanced automation, connectivity, electrification, and shared mobility. However, this progress also brings forth unprecedented challenges, particularly in ensuring the safety and security of automotive electronics. The complexity of modern electrical/electronic systems in vehicles, encompassing Electronic Control Units (ECUs), communication channels, infotainment systems, and driver assist features, amplifies the vulnerabilities to potential cyber-threats. As vehicles become more interconnected, the risk of malicious hacks poses not only a threat to privacy but also to the lives and well-being of passengers. Therefore, ensuring the security of automotive electronics is not merely a matter of competitive advantage; it is a business, legal, and moral imperative.

Siemens EDA recently published a whitepaper that addresses the challenges faced by IC designers in this regard and offers a solution. The whitepaper, authored by Lee Harrison, Director, Tessent Division of Siemens EDA, delves into the realm of automotive hardware security, focusing on the integration of security solutions within the ICs that power essential vehicle components.

Challenges Faced by IC Designers

With a pressing need for robust security measures, IC designers encounter a myriad of challenges in addressing the intricacies of automotive hardware security. The problems they face are often ill-defined and not widely understood, leading to ambiguity in devising effective solutions. Moreover, the rapid evolution of technology exacerbates the challenge, requiring continuous adaptation to emerging threats and vulnerabilities. In this context, the integration of security features within ICs assumes paramount importance in fortifying automotive hardware against potential cyber-attacks.

The Multi-Layered Security Approach

In addressing the complexities of automotive hardware security, a multi-layered approach becomes indispensable. This approach entails integrating security measures at various levels, including hardware, software, and network protocols. At the hardware level, IC designers must embed robust security features within the silicon itself, leveraging technologies such as hardware encryption, secure boot, and tamper-resistant designs. Additionally, software-based security mechanisms, such as intrusion detection systems and secure firmware updates, play a crucial role in safeguarding against cyber threats. Furthermore, implementing secure communication protocols and network segmentation helps mitigate the risk of unauthorized access and data breaches.

Securing the Physical Layer

At the heart of automotive hardware security lies the physical layer, where designers must address vulnerabilities within the supply chain and protect against tampering and side-channel attacks. Design-for-test (DFT) structures and test buses offer mechanisms to safeguard sensitive data and operations, ensuring the integrity of automotive ICs from fabrication to deployment.

Ensuring Trust at the Data Link Layer

The data link layer serves as the root of trust for validating system hardware and software during boot-up. Hardware trusted anchors (HTA), such as Hardware Security Modules (HSM), provide essential security functions like key protection and secure boot, bolstering the integrity and authenticity of automotive systems.

Protecting the Network Layer

The network layer presents a battleground against malicious network transactions and software requests. Firewalls play a crucial role in controlling packet processing and establishing audit points to track attacks.

Future-Proofing Automotive Hardware with Siemens Solutions

Siemens solutions offer comprehensive security features across multiple layers, enhancing protection against cyber threats. To meet evolving security standards and regulations, makers of automotive ICs can leverage Tessent Design-For-Test (DFT) and Tessent Embedded Analytics IP.

Tessent Design-For-Test (DFT) and Embedded Analytics

These technologies offer a multi-layered security framework that can be seamlessly integrated into ICs to identify and address security vulnerabilities. Tessent DFT enables the implementation of built-in self-test capabilities within ICs, facilitating thorough testing and validation of security features throughout the manufacturing process. Tessent Embedded Analytics empowers ICs with real-time monitoring and analysis capabilities, allowing for proactive detection and response to potential security threats. It provides a comprehensive solution for enhancing automotive hardware security, covering various aspects such as authentication, communication, protection, and device lifecycle management. By offering configurable options across test, functional operation, and system-level security, Tessent ensures that automotive systems are resilient against cyber threats while maintaining low latency.

Automotive stakeholders can significantly enhance the security posture of their systems, ensuring robust protection against cyber-attacks.

Summary

As the automotive industry accelerates towards greater automation, connectivity, and electrification, the imperative for ensuring the security of automotive electronics has never been more in focus. IC designers play a pivotal role in fortifying automotive hardware against evolving cyber threats, leveraging advanced technologies such as Tessent DFT and Embedded Analytics to bolster security at the silicon level. By adopting a multi-layered security approach encompassing hardware, software, and network protocols, automotive stakeholders can mitigate risks, safeguard passenger safety, and uphold the trust and integrity of the automotive ecosystem.

You can access the entire whitepaper here.

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INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with advanced analog and mixed-signal EDA technology

INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with advanced analog and mixed-signal EDA technology
by Daniel Nenni on 03-05-2024 at 6:00 am
Categories: EDA, Siemens EDA

siemens symphony interchip large

Customer case studies have always been my favorite source of information. Press releases are a great start but there is always more to the story. Fortunately, I had the opportunity to speak with Sumit Vishwakarma, principal product manager at Siemens EDA about their recent press release with Interchip. I was an advisor to Berkeley Design Automation (Analog FastSPICE author) up until the acquisition by Siemens EDA so this one was of special interest to me.

What are the key products of Interchip?
Interchip is a leading fabless semiconductor company that specializes in high precision, low power oscillator products. Their high precision Crystal Oscillator ICs are deployed globally in a wide range of products, including computers, mobile phones, medical devices, and industrial equipment.

What is a Voltage Controlled Oscillator and how it differs from a Crystal Oscillator?
Voltage Controlled Oscillators (VCXOs) are electronic devices that generate an output signal with a frequency that can be varied by applying a voltage to the device. Crystal Oscillators (XOs) are electronic circuits that use the mechanical resonance of a vibrating crystal of piezoelectric material to create an electrical signal with a very precise frequency.

What makes Interchip Oscillators stand out?
Interchip excels in high speed, high-precision, wide-pulling-range Crystal Oscillators with robust noise performance and low power consumption.

What are the verification challenges of these Oscillator circuits?
Verifying high-precision, wide-pulling-range Voltage Controlled Oscillators (VCOs) poses challenges including maintaining frequency stability, minimizing phase noise and nonlinear effects, balancing power consumption, managing temperature sensitivity and process variability, ensuring wide pulling range performance, minimizing jitter, and addressing integration complexities. Meeting these challenges requires comprehensive simulation, modeling, characterization, and testing across diverse operating conditions.

How did Siemens EDA AFS and Symphony technology help Interchip meet the verification challenges of these designs?
Interchip used Siemens’ Analog FastSPICE (AFS) and Symphony platform to verify its newest IPV Voltage-Controlled Crystal Oscillator (VCXO) integrated circuits and IPS Simple Packaged Crystal Oscillator (SPXO). These tools from Siemens helped INTERCHIP perform silicon-accurate simulations of their designs three times faster compared to their previous solution. This notable acceleration in verification cycles proved pivotal in successfully meeting their aggressive time-to-market objectives.

What is Siemens Analog FastSPICE platform?
Siemens’ Analog FastSPICE platform provides circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. Certified for foundries down to 2nm, the platform can deliver nanometer-scale SPICE accuracy twice as fast as parallel SPICE simulators. The solution includes comprehensive, full-spectrum device noise analysis to help customers achieve silicon-accurate results.

What is Siemens Symphony platform?
Symphony is industry’s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across A/D interfaces at all levels of the design hierarchy and for all IC applications. Symphony’s modular architecture leverages AFS to provide the fastest mixed-signal simulation performance with nm SPICE accuracy, proven on a wide range of ICs and IC subsystems including ADCs, transceivers, PMICs, multi-GHz PLLs/DLLs, and sensors.

And what is Symphony Pro?
Symphony Pro is our advance tier of Symphony. It is built on the proven performance of Symphony and Questa Visualizer™ to augment the support for digital-centric mixed signal verification methodologies such as UVM-AMS and UPF-MS. Symphony Pro’s Visualizer MS environment offers a seamless debug experience across the entire mixed-signal design hierarchy with comprehensive analysis, automation, and ease-of-use for unmatched productivity.

Here are the quotes from the press release:

“As a leading Crystal Oscillator manufacturer serving many of world’s leading consumer, medical and industrial OEMs, our team thrives on overcoming complex engineering hurdles to deliver high speed, high-precision, wide-pulling-range Crystal Oscillators,” said Ryuji Ariyoshi, CEO, INTERCHIP. “We pride ourselves in successfully overcoming complex design challenges such as linearity, frequency pushing, noise performance, aging and power consumption. Siemens’ Analog FastSPICE platform stood out as our top choice for its ability to provide nanometer, SPICE accurate results at a remarkable 3x faster speed than conventional SPICE simulators. Further, Siemens’ Symphony platform enabled us to successfully verify our chip’s complex analog and digital interaction and functionality.”

“High-precision Crystal oscillators play a critical role in advanced IC clock systems, and they are indispensable in modern electronic devices,” said Amit Gupta, vice president and general manager for the Custom IC Verification Division at Siemens Digital Industries Software. “Their accurate timing, stable frequencies and reliable performance are essential for helping to achieve proper operation, data integrity and overall system efficiency in a wide range of applications. It is rewarding to see the pivotal role played by our Analog FastSPICE and Symphony platforms in facilitating INTERCHIP’s development and verification of their latest high-precision oscillator design.”

I was also an advisor for Amit Gupta, CEO of Solido Design, before their acquisition by Siemens EDA.  EDA is a small world, absolutely.

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A Game-Changer for IP Designers: Design Stage Verification

A Game-Changer for IP Designers: Design Stage Verification
by Kalar Rajendiran on 03-04-2024 at 10:00 am
Categories: EDA, IP, Siemens EDA

Calibre Shift Left Solutions Enable Reducing TTM

In today’s rapidly evolving semiconductor industry, the design and integration of intellectual property (IP) play a pivotal role in achieving competitive advantage and market success. Whether sourced from commercial IP providers or developed in-house, ensuring that IP designs are compliant with signoff requirements and seamlessly integrable into larger designs is paramount. From managing design complexity to ensuring power efficiency and security, IP designers must navigate a multitude of factors while striving to meet tight deadlines and maintain quality standards. Additionally, the rise of third-party IP usage and design reuse further complicates the landscape, necessitating interoperability and compatibility across different IP blocks and design modules. The complexity and competitiveness of the IP design landscape necessitate efficient verification processes that minimize time-to-market and resource requirements. Siemens EDA addresses this topic in-depth in a recently published technical whitepaper.

The Importance of Early Verification

Commercial IP design is a fiercely competitive arena, while in-house IP development offers the opportunity for design companies to differentiate themselves by incorporating innovative functionality into their integrated circuit (IC) designs. Regardless of the source, ensuring that IP designs are signoff-compliant and ready for integration into larger designs is essential for maintaining a competitive edge. In addition, Block/chip designers and designers working on three-dimensional integrated circuits (3DICs) also encounter unique verification challenges that require specialized solutions. Reducing the time and resources required for design, implementation, and verification directly impacts marketability and profitability.

One of the key strategies for streamlining the IP design process is the early detection and correction of physical verification issues. By identifying and addressing these issues in the initial stages of the design process, designers can minimize the risk of costly errors and delays during later stages.

Siemens EDA’s Calibre Shift Left Solutions

Calibre Shift Left solutions provide a comprehensive approach to streamlining the IP design process. These solutions combine proven Calibre technology with innovative strategies to support consistent and thorough verification of IP designs while maximizing productivity and efficiency. By shifting select physical verification and design optimization tasks earlier in the design and implementation workflows, Calibre Shift Left solutions empower design teams to accelerate time-to-market and achieve volume production faster.

Calibre Shift Left Solutions Enable Enhanced Productivity and Reduced Time to Market

 

From early detection of design issues to comprehensive verification of IP designs, Calibre Shift Left solutions provide the flexibility and scalability needed to meet the diverse needs of semiconductor design teams. Calibre Shift Left solutions offer advanced tools and methodologies to facilitate early detection of physical verification issues, enabling designers to proactively address these challenges and ensure compliance with signoff requirements.

Shift Left Physical Verification in IP Design Flows

Prioritizing and Categorizing Design Issues

Efficient resolution of design issues is essential for maintaining productivity and meeting project deadlines. Prioritizing and categorizing design issues allows designers to focus their efforts on resolving critical issues first, minimizing time and resource wastage. Calibre Shift Left solutions provide functionalities to prioritize and categorize design issues, enabling designers to allocate resources effectively and accelerate the resolution process.

Tailored Benefits for Different IP Design Types

Calibre Shift Left solutions offer specific advantages tailored to different IP design types. For hard IP designers, early verification enables rapid identification and resolution of modified IP components, minimizing retesting requirements and ensuring smooth integration into larger designs. Soft IP designers benefit from early SRAM IP integrity validation, mitigating compilation issues before finalizing the design. Custom IP designers can leverage tools like Calibre RealTime Custom and Calibre Pattern Matching to streamline verification processes and reduce runtime and debug cycles.

Aligning IP Cell Verification with Larger Chip Designs

Ensuring consistency and alignment between IP cell verification and larger chip designs is crucial for seamless integration and optimal performance. Calibre Shift Left solutions enable designers to align IP cell verification with the same intent as larger chip designs, ensuring compatibility and interoperability across different design components. By leveraging Calibre’s proven technology, designers can streamline the verification process and minimize discrepancies between IP cells and larger chip designs.

Extending Beyond IP Design

Beyond IP design, block/chip designers and 3DIC designers can also benefit from Calibre Shift Left solutions to address their unique verification challenges. These solutions enable designers to apply early verification stages efficiently within familiar environments, ensuring high-quality results while accelerating the design process. Calibre Shift Left solutions not only optimize resource utilization but also enhance design agility and competitiveness in today’s dynamic semiconductor landscape.

Optimizing Performance and Automation

Performance optimization and automation play a crucial role in enhancing the efficiency of early design-stage verification. Calibre Shift Left solutions offer advanced optimization techniques and automation capabilities to minimize runtimes and maximize resource efficiency. By integrating Calibre tools into design and implementation environments, designers can streamline verification processes and accelerate design closure while ensuring signoff-quality results.

Summary

In a competitive semiconductor landscape, the Calibre Shift Left solution emerges as a game changer for streamlining the IP design process and enhancing overall efficiency. By addressing key challenges such as early detection of physical verification issues, efficient resolution of design issues, and alignment of IP cell verification with larger chip designs, Calibre Shift Left solutions empower designers to deliver high-quality IP designs in a timely manner. By streamlining verification processes, minimizing time-to-market, and optimizing resource utilization, Calibre Shift Left solutions allow companies to stay ahead of the curve.

Siemens EDA’s whitepaper titled “A game-changer for IP designers: design-stage verification” is essential reading for designers, engineers, and engineering managers aiming to streamline and enhance the efficiency and accuracy of their design processes.

Also Read:

AI and SPICE Circuit Simulation Applications

Mastering Mixed-Signal Verification with Siemens Symphony Platform

Cryogenic Semiconductor Designs for Quantum Computing

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How MZ Technologies is Making Multi-Die Design a Reality

How MZ Technologies is Making Multi-Die Design a Reality
by Mike Gianfagna on 03-04-2024 at 6:00 am
Categories: EDA, MZ Technologies
2 Comments

How MZ Technologies is Making Multi Die Design a Reality

The next design revolution is clearly upon us. Traditional Moore’s Law is slowing, but the exponential demand for innovation and form factor density is not. When you can no longer get it done with a single monolithic chip, moving to a multi-die approach is the answer. This emerging design methodology has many challenges – supply chain-oriented, materials-oriented, and standards-oriented to name a few. There is promising innovation from EDA, IP and standards organizations. Sitting above all this work is a substantial challenge. With so many options to implement new system-level silicon, which set of options are best?  2.5D, 3D, technology choices, IP/chiplet choices and so on. It’s a vexing problem since starting with the wrong options can lead to huge cost and schedule impact. The problem has been referred to as pathfinding, and that is the topic of this post. Read on to see how MZ Technologies is making multi-die design a reality.

About MZ Technologies

I mentioned pathfinding. In the context here, the term refers to identifying the optimal technology choices to implement a 2.5D or 3D multi-die design. The problem has been around for quite a while. Here is a discussion of it from the 2009 IEEE International Symposium on System-on-Chip. I have some experience with these problems as well. Around this same time frame while I was at Atrenta, we developed an early tool to address the pathfinding problem. And later, while at eSilicon, I got an up-close look at how challenging 2.5D design can be.

MZ Technologies was founded in 2014 by a team of leading EDA, IC, and package co-design experts. The goal was to build new technology from scratch to deal with the I/O planning and optimization phase of the physical implementation of complex 2.5D and 3D integrated circuits. That is, solve the pathfinding problem. A bit about the name of the company, which is shorthand for monozukuri. In Japanese, “monozukuri” is a compound word comprising “mono”, which literally means “things” (“products”), and “zukuri”, which means “process of making” or “creation”.

The company is a European EDA provider delivering GENIO™ a unified cockpit for 2.5D & 3D chiplet-based system design. GENIO is a tool that fills the pathfinding gap for multi-die design. It doesn’t compete with existing technologies, but rather interfaces with them to create a broader, more holistic capability. The tool has been around through several releases and has seen application across a wide range of multi-die designs. More on that in a bit.

What MZ Technologies Does

GENIO addresses the system architecture and IC/package co-development flow. This is the part of the design process that typically sits above existing tools and IP. It answers critical questions about the best implementation approach from a form factor, energy, performance, and cost point of view. Getting these things right early in the process can be the margin of victory for a complex design. Starting with a sub-optimal approach will create re-work, overruns, and a good chance the project will fail.

The figure below shows how GENIO fits into the overall design flow with existing tools.

GENIO Design Flow

The tool fits in the flow from concept to design to deliver a first time right optimal result. The goal is to create better manufacturability with optimal resources usage and better yield. GENIO works across the complete design ecosystem from silicon to package to PCB, with integrated design flows.

Digging a bit deeper, system architecture exploration is supported for planning, implementation, and analysis across different engineering domains. What-if analysis is provided for 2D, 2.5D and 3D interconnect management, I/O planning, and optimization. For example, planar vs. SI-based vs. 3D-stack. The optimization algorithms tame multi-die design computational complexity. Early estimations of electrical, mechanical, and thermal behavior are also provided.

With GENIO, it is possible to optimize in one shot through the full system hierarchy, from the top level to subsystems and components. A sophisticated GUI allows cross-highlight and scripting, among other functions, with the ability to go back in the design history to tag the most promising configurations.  The figure below shows an example of the GUI.

GENIO GUI

GENIO has delivered a remarkable 60x reduction of architectural design time. The table below illustrates the types of designs GENIO has been applied to.

GENIO Applications

Here is a summary of the current version and next generation of the tool:

GENIO V1.x (commercially available today with a back-end orientation)

  • Comprehensive system view spans the entire design ecosystem
    • Cross-fabric platform, integrated with traditional IC, package & PCB design tools
  • System-level architecture exploration
    • Identifies the more efficient and cost-effective option into 3D system offering
  • Single, consistent Interconnect Manager
    • Represent and maintain the 3D model of the entire system
  • Cross-hierarchical 3D-aware pathfinding
    • Constraint-driven, proprietary optimization algorithms
  • 3D chiplet-based design flow with multiple IP libraries
    • Die stacking and silicon-to-silicon vertical communications – mix-and-match “LEGO-like” assembly 

GENIO EVO (Next Evolution release; introduces simulation-aware optimization)

  • Complete 3D system view across physical implementation and analysis
  • Super-fast parasitic estimation for early analysis
    • What-if analysis before physical implementation starts
  • State-of-the-art TSV modeling
    • Including electrical performance (R/C) and mechanical/thermal behavior
  • Thermal modeling
    • Based on power dissipation map and TSVs contribution
  • Mechanical stress
  • Voltage and temperature monitor placement according to identified thermal hotspots
    • Critical net group spotting and prioritization
  • 3DBlox language support
  • 3D-system partitioning flow
    • Support to system partitioning in the early stages of RTL & synthesis
  • 3D-stack floor planning
    • Best positioning of system components/chiplets across the stack planes

To Learn More

MZ Technologies licenses its software with a time-based model. Additional services for custom integration, custom module development, and customer training are also available. If you are planning to tackle a multi-die design, you should contact them. I can tell you from first-hand experience the problem MZ solves is very real and can become a fatal flaw if not addressed early. You can reach out at info@monozukuri.eu. And that’s how MZ Technologies is making multi-die design a reality.

Also Read: 

Outlook 2024 with Anna Fontanelli Founder & CEO MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies

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SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?

SPIE Let there be Light! High NA Kickoff! Samsung Slows? “Rapid” Decline?
by Robert Maire on 03-03-2024 at 6:00 am
Categories: Events, Semiconductor Advisors, Semiconductor Services
3 Comments

High NA EUV 2024

– High NA EUV’s coming out party – “Dawn” of the Angstrom Era
– Well attended, positive vibes, not much new but good progress
– Concerns about Samsung slowing spend while Intel accelerates
– KLA reticle inspection quandary – Risky business in China

SPIE was a High-NA “coming out” party

We would view this years SPIE 2024 conference as the official launch of High-NA EUV technology, both figuratively as well as in reality.

It was announced by Ann Kelleher of Intel that “first light” was achieved by an ASML High-NA tool in Veldhoven (soon to be followed by Intel’s first High-NA tool).

In her presentation we attended we saw a strange set of banana shaped light images on a wafer that were evidence of the first EUV light through a recently assembled tool.

Although its sounds simple, its a big step on the way

Ann also gave a great overview of where the industry and specifically Intel was at and reiterated the five nodes in four years mantra which seems to be underscored by solid progress. It was one of the better overviews talks we have seen.

Tribute to Gordon Moore

There was also an “all star” cast of industry titans who gave a very heartfelt tribute to the late Gordon Moore, father of the semiconductor industry’s heartbeat of “Moore’s Law”. Perhaps the most touching was from Craig Barrett, former CEO of Intel.

It was very appropriate timing as High-NA represents the gateway to the Angstrom era which is proof positive of the continued life and legacy of Moore’s Law and its continued progress

No “New” news

The conference was very well attended and bounced back even more than its pre covid highs. The number of “poster” presentations appeared to more than double. However, there were no major announcements that moved the industry as in some past SPIE conferences.

Many of the presentations were on one aspect of EUV or High-NA or another. DUV was left in the dust along with “I-Line” lithography and other ancient technologies. Photoresist, reticles, metrology and other accoutrements to EUV were the majority of the topics of presentations.

A tale of “two semis”

We heard from a number of people in the equipment industry and supply chain that Samsung has slowed, canceled or delayed many orders. It also seems to be not just the memory side of Samsung that is slowing but the logic/foundry side as well.

It seems fairly clear to us that memory still has a lot of excess fab capacity and that situation has not gotten much better or at least better enough to start capacity purchases.

What is more interesting is that the foundry/logic side is also weak. We could speculate about the continued foundry weakness and would bet that TSMC is likely taking share from Samsung during this weaker period.

We have mentioned this before as second tier foundries get overflow business when things are hot and TSMC can’t service everyone. But when things slow, customers come back to TSMC. We saw other evidence of this with GlobalFoundries  projected decline which could be a foreshadowing of Samsung foundry weakness.

On the other side of the coin, Intel seems to be cranking on all cylinders, and going in the opposite direction from Samsung’s slowing spend.

Perhaps Intel being more positive while Samsung cools nets out to the flattish projections we heard from semiconductor equipment makers reporting their December quarter

Applied continues to call SCULPTA etch tool a patterning tool -NOT-

Applied had a repeat performance of its etch tool called SCULPTA which it continues to palm off as a patterning tool by talking about it at SPIE.

Last year, dumb analysts, trashed ASML’s stock by predicting the end of double patterning and the reduction of ASML sales due to SCULPTA which obviously didn’t happen so there was no stupid knee jerk reaction this year….just a ho hum.

A “RAPID” decline? Photons are better than electrons

We continue to express concern and warn about the long term direction of the “RAPID” division of KLA (reticle inspection) which was one of the two founding pillars of the company.

It sounds like the 8xx, E beam reticle inspection tool, which was most likely to be an interim placeholder while waiting for the delayed Actinic inspection 7xx is now dead at two key customers.

It also sounds like the optical market that the 6xx plays in has become more of a commodity horse race which has negatively impacted pricing.

On the bright side it sounds like the long anticipated 7xx Actinic tool may be close to experiencing its version of EUV “first light”….light at the end of a very long tunnel.

Also on the bright side for KLA, the rumored Zeiss Actinic inspection tool that we first reported on sounds like it could be a bit over hyped with too high expectations and may struggle much as their first “AIMS” review tool.

It may still be a race to see who gets the second Actinic tool on the market, KLAC or Zeiss, years after the Lasertec tool. Stay tuned.

Risky business in China

We have long warned about the risk and exposure of 45% of the industry’s semiconductor equipment business being in China. The risk is compounded by potential for prohibited behavior consequences.

Back in the fall it was reported that AMAT was under investigation for violating export regulations on China by cross shipping to China through Korea. We had noted at the time, and no one else seemed to pick up on, the additional risk to CHIPS act awards due to potentially prohibited behavior.

Yesterday, it was widely reported in the news that not only has Applied received more subpoenas regarding the original concerns but the investigation has broadened to now include the SEC.

As we had predicted, the company also just reported that it also received subpoenas related to “certain federal award applications”, which sounds like the feds may be wondering about Applied getting CHIPS act money if they are violating China restrictions ….this could be a “triple play”…..

Link to Reuters article on AMAT subpoenas

The Stocks

There was not a whole lot of impactful news at SPIE this week but the other China news clearly underscores the continued risks.

We also remain concerned that weakness from Samsung may slow any recovery which is hoped for in the second half of the year.

The stocks in general remain fully to well over valued in our view and continue to be swept up in the Nvidia/AI tsunami

We wonder if or when investors will start to separate out those stocks with more or less exposure especially if the recovery takes longer than the expected end of year timeframe.

The China risk continues as a cloud over the industry as evidenced by Applied.

While we still adore Nvidia, and personally own it, other semiconductor stocks may not deserve the same adoration simply through association of being in the same semiconductor industry.

We do still like both ASML, now the biggest equipment maker, and TSMC, by far the biggest and best foundry….but we get a bit more picky as we go down the list especially at nose bleed valuations

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

AMAT – Flattish QTR Flattish Guide – Improving 2024 – Memory and Logic up, ICAPs Down

KLAC- OK Quarter & flat guide- Hopefully 2025 recovery- Big China % & Backlog

LRCX- In line Q4 & flat guide- No recovery yet- China still 40%- Lags Litho

ASML – Strong order start on long road to 2025 recovery – 24 flat vs 23 – EUV shines

Podcast EP210: How VSORA is Opening New Horizons for Generative AI and ADAS Applications

Podcast EP210: How VSORA is Opening New Horizons for Generative AI and ADAS Applications
by Daniel Nenni on 03-01-2024 at 10:00 am

Dan is joined by Jan Pantzar vice president of sales and marketing at VSORA, a provider of high-performance generative AI and ADAS chip solutions based in France. Mr. Pantzar gained extensive experience in the semiconductor, IP and software industries through building and managing organizations around the globe. Previous experience includes executive positions at Ericsson, Cypress and STMicroelectronics.

Jan provides details about the unique processor chips VSORA is developing. The primary markets for these devices is initially generative AI and automotive/autonomous driving, but VSORA technology can be applied in other areas as well. The focus is on very high performance and low power, opening the door to new levels of local processing capability.

Jan discusses the challenges faced today for generative AI and ADAS applications and explains how VSORA’s technology is removing processing and power barriers. He previews what the company will be delivering over the next year and where the impact will be.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.