HCL is an interesting organization. You may know them as an Indian company that provides software and hardware services. At about $10B US and over 110,000 employees working around the world, they are indeed a force in the industry. They’ve also created a software company called HCL Software that develops tools and technologies… Read More
Tag: webinar
WEBINAR: Moving UVM Verification Up To The Next Level
Tom Fitzpatrick, a Strategic Verification Architect at Mentor, a Siemens Business, has worked on IEEE and Accellera standards like Verilog 1364, System Verilog 1800, UVM 1800.2 and is Vice Chair of the Portable Stimulus working group, so when I heard that he was doing a webinar on how PSS can be used to create better stimulus for … Read More
Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems
During the COVID-19 pandemic I’m using Zoom and attending more webinars to keep updated on semiconductor industry trends, and one huge trend is the importance of AI applied to SoCs. Using more cores to handle ML and DL makes sense, but then how do you keep the chips within their power and reliability limits while at the same … Read More
Webinar Recap: IP Security Threats in your SoC
Three years ago my youngest son purchased a $17 smart watch on eBay, but then my oldest son read an article warning about how that watch would sync with your phone, then send all of your contact info to an address in China. My youngest son then wisely turned the watch off, and never used it again. Hackers have been able to spoof and hide … Read More
WEBINAR REPLAY: AWS (Amazon) and ClioSoft Describe Best Cloud Practices
ClioSoft has been working with the leading cloud computing providers running experiments on various EDA cloud architectures for a while now. One example of that was a project with Google I previously wrote a blog about, For EDA Users: The Cloud Should Not Be Just a Compute Farm. Since then, ClioSoft has also teamed up with Amazon … Read More
Rapid growth of AI/ML based systems requires memory and interconnect IP
Artificial intelligence and machine learning (AI/ML) are working their way into a surprising number of areas. Probably the one you think of first is autonomous driving, but we are seeing a rapidly growing number of other applications as time goes on. Among these are networking, sensor fusion, manufacturing, data mining, numerical… Read More
WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for… Read More
Free webinar – Accelerating data processing with FPGA fabrics and NoCs
FPGAs have always been a great way to add performance to a system. They are capable of parallel processing and have the added bonus of reprogramability. Achronix has helped boost their utility by offering on-chip embedded FPGA fabric for integration into SoCs. This has had the effect of boosting data rates through these systems… Read More
Debugging SoCs at the RTL, Gate and SPICE Netlist Levels
Debugging an IC is never much fun because of all the file formats used, the levels of hierarchy and just the sheer design size, so when an EDA tool comes around that allows me to get my debugging done quicker, then I take notice and give it a look. I was already familiar with debugging SPICE netlists using a tool called SPICEVision Pro,… Read More
Webinar: OCV and Timing Closure Sign-off by Silvaco on Oct 10 at 10AM
The old adage that goes the one constant thing you can always count on is change, could easily be reworded for semiconductor design to say the one constant thing you can count on is variation. This is doubly true. Not only is variation, in all its forms, a constant factor in design, additionally the methods of analyzing and dealing … Read More