Constrain all you want, we’ll solve more

Constrain all you want, we’ll solve more
by Don Dingee on 07-24-2013 at 8:30 pm

EDA tool development is always pushing the boundaries, driven in part by bigger, faster chips and more complex IP. For several years now, the trend has been developing tools that spot problems faster without waiting for the “big bang” synthesis result that takes hours and hours. Vendors, with help from customers, are tuning tools… Read More


Debugging Verification Constraints

Debugging Verification Constraints
by Paul McLellan on 07-23-2013 at 3:44 pm

In his DAC keynote last year (2012) Mike Mueller of ARM compared how much CPU was required to verify the first ARM versus one of the latest ARM Cortex CPUs. Of course the newer CPU is hundreds of times larger than the first ARM but the amount of verification required was millions of times as much, requiring ARM to construct their own datacenter… Read More


Multi-level abstraction accelerates verification turnaround

Multi-level abstraction accelerates verification turnaround
by Pawan Fangaria on 05-02-2013 at 8:30 pm

Often a question is raised about how SystemC improves verification time when the design has to go through RTL in any case. A simple answer is that with SystemC, designs can be described at a higher level of abstraction and then automatically synthesized to RTL. When the hands-on design and verification activity is at a higher level,… Read More


Mentor Shines at DVCon

Mentor Shines at DVCon
by Beth Martin on 02-18-2013 at 12:30 am

Mentor Graphics will be all over DVCon next week (February 25-28) at the DoubleTree hotel in San Jose.

In addition to attending all the panels, tutorials, posters, and the keynote, you can visit Mentor in booth 901 on the exhibit floor.
Here’s the lineup of Mentor-related events:… Read More


Scoreboards and Results Predictors in UVM

Scoreboards and Results Predictors in UVM
by Daniel Nenni on 07-15-2012 at 10:56 am

If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case.

Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that… Read More