TSMC (Lincoln) vs Samsung (Clinton) vs Intel (Washington)

TSMC (Lincoln) vs Samsung (Clinton) vs Intel (Washington)
by Daniel Nenni on 02-28-2013 at 9:00 am

Usually I sleep on long flights, if not, I watch movies and read. The Lincoln movie was playing on EVA Air this week which reminded me that Abraham Lincoln was one of the greatest U.S. Presidents. If I was asked to pick a U.S. President as a spokesperson for TSMC it would be Honest Abe Lincoln. Chairman Morris Chang said it best during … Read More


Intel and Altera Sign on for 14nm

Intel and Altera Sign on for 14nm
by Ed McKernan on 02-25-2013 at 5:00 pm

The announcement today that Intel will be a Foundry for Altera at 14nm is a significant turning point for the Semiconductor Industry and Intel’s Foundry fortunes of which the full ramifications are not likely to be understood by analysts. As a long time follower of Intel and a former co-founder of an FPGA startup (Cswitch), it has… Read More


The New "Mobile Foundry" Era: Whose Wheelhouse?

The New "Mobile Foundry" Era: Whose Wheelhouse?
by Ed McKernan on 02-25-2013 at 1:12 pm

Nothing seems to raise the Visceral Ire of Semiwiki readers like the two words: Intel and Foundry. To get maximum steam coming out of the ears make sure you combine the two words in a sentence. Something along the lines like: Intel is Now Going to be a Leader in the Foundry Business. Pause…..Ok catch your breadth and now let’s move on … Read More


Who Allegedly Broke Tela’s Patents: Is Samsung or Qualcomm the Real Villain?

Who Allegedly Broke Tela’s Patents: Is Samsung or Qualcomm the Real Villain?
by Randy Smith on 02-25-2013 at 1:08 pm

I recently blogged about the actions filed by Tela Innovations at both the US International Trade Commission (USITC) and in federal district court. Those actions allege that five mobile phone manufacturers -HTC, LG, Motorola Mobility, Pantech, and Nokia – were importing handsets into the US which infringed on seven of… Read More


TSMC ♥ Cadence

TSMC ♥ Cadence
by Daniel Nenni on 02-19-2013 at 11:00 am

In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.

Rick… Read More


Using Soft IP and Not Getting Burned

Using Soft IP and Not Getting Burned
by Daniel Payne on 02-07-2013 at 10:11 am

The most exciting EDA + Semi IP company that I ever worked at was Silicon Compilers in the 1980’s because it allowed you to start with a concept then implement to physical layout using a library of parameterized IP, the big problem was verifying that all of the IP combinations were in fact correct. Speed forward to today and our… Read More


Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs

Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs
by Eric Esteve on 02-01-2013 at 8:25 am

ASIC design service companies are an essential piece of the SC ecosystem, as well as Silicon Foundries, EDA and IP vendors. Their customers range from pure fabless with no ASIC design resources, who need a third party to turn a concept into a real product (IC) and then market and sale it, to large IDM temporarily lacking design resource… Read More


TSMC ♥ Oasys

TSMC ♥ Oasys
by Paul McLellan on 01-31-2013 at 8:05 pm

Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling … Read More


Double Patterning for IC Design, Extraction and Signoff

Double Patterning for IC Design, Extraction and Signoff
by Daniel Payne on 01-21-2013 at 3:27 pm

TSMC and Synopsys hosted a webinar in December on this topic of double patterning and how it impacts the IC extraction flow. The 20nm process node has IC layout geometries so closely spaced that the traditional optical-based lithography cannot be used, instead lower layers like Poly and Metal 1 require a new approach of using two… Read More


Wafer Costs: Out of Control or Not?

Wafer Costs: Out of Control or Not?
by Paul McLellan on 01-01-2013 at 8:30 pm

I didn’t attend the International Electronic Device Meeting (IEDM) earlier this month, but there have been a lot of reports on the inter webs especially about 20nm and 14nm processes. Some of this is really geeky stuff but I think that perhaps the most interesting thing I’ve read about is summarized in this chart:

This… Read More