Process shrinks, which have served us well for most of the Moore’s Law journey, are reaching their limits. For switching transistors, the biggest problems of leakage current and gate oxide vulnerability in planar MOSFETs have led the industry to new 3D microstructures such as FinFET. For non-volatile memory, the problem is generally… Read More
Tag: tsmc
TSMC OIP: Registration Open
It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges.… Read More
September is Semiconductor Design Webinar Month!
The nice thing about webinars is that if you register for the live one and you can’t attend you will still get first notice when the replay goes up. The other nice thing is that you can read a blog review of a webinar or whitepaper on SemiWiki first to see if it is worth your time. If you do attend a webinar you can also post a review of… Read More
Granite River Labs and TSMC Expand Agreement
For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to recover the huge capital investment a modern fab entails. With many SoCs having over… Read More
A Deeper Insight into Quantus QRC Extraction Solution
Last month Cadenceannounced its fastest parasitic extraction tool (minimum 5 times better performance compared to other available tools) which can handle growing design sizes with interconnect explosion, number of parasitics and complexities at advanced process nodes including FinFETs, without impacting accuracy of … Read More
When TSMC advocates FD-SOI…
I found a patent recently (May,14 2013) granted to TSMC “Planar Compatible FDSOI Design Architecture”, the following sentences, directly extracted from this patent, advertise FDSOI design better than a commercial promotion! “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including… Read More
Intel Versus TSMC 14nm Processes
Intel has begun to release some details on their 14nm process. I thought it would be interesting to contrast what Intel has disclosed to TSMC’s 16nm process disclosure from last year’s IEDM (TSMC calls their 14nm process 16nm).
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Should we pay the price of Innovation?
I agree that this question sounds stupid: nobody is forcing me to buy an innovative product, or even a gadget, if I don’t want to pay a high price, I just don’t buy the product. But it seems that some people don’t really think that way. The story is related to Qualcomm sales in China, and recently announced partnership with SMIC…
The Partnership… Read More
Who will Manufacture Apple’s Next SoC?
Just to review: The brain inside the current Apple iPhone 5s is the A7 SoC manufactured by Samsung using a 28nm process. The A6 (iPhone 5) and A5 (iPhone 4s) are based on Samsung 32nm. The rest of the Apple SoCs also used Samsung processes. I think we can all now agree that the coming Apple A8 SoC (iPhone 6) will use the TSMC 20nm process.… Read More
eSilicon and the Ten Minute Quote
One of the challenges in bringing a design into production is getting a quote that includes all the various stages of the process. The quote cycle typically takes a couple of weeks. It is also pretty wasteful. A typical design might be quoted by 3 manufacturers and so 2 out of 3 quotes are wasted expense because the design is lost to a … Read More