SPIE 2017: EUV Readiness for High Volume Manufacturing

SPIE 2017: EUV Readiness for High Volume Manufacturing
by Scotten Jones on 03-03-2017 at 12:00 pm

The SPIE Advanced Lithography Conference is the world’s leading conference addressing photolithography. This year on the opening day of the conference, Samsung and Intel presented papers summarizing the readiness of EUV for high volume manufacturing (HVM). In this article, I will begin by summarizing the EUV plans … Read More


TSMC Design Platforms Driving Next-Gen Applications

TSMC Design Platforms Driving Next-Gen Applications
by Daniel Nenni on 03-03-2017 at 7:00 am

Coming up is the 23rd annual TSMC Technology Symposium where you can get first-hand updates on advanced and specialty technologies, advanced backend capabilities, future development plans, and network with hundreds of TSMC’s customers and partners. This year the Silicon Valley event kicks off at the Santa Clara Convention… Read More


EUV is NOT Ready for 7nm!

EUV is NOT Ready for 7nm!
by Daniel Nenni on 02-27-2017 at 8:00 am

The annual SPIE Advanced Lithography Conference kicked off last night with vendor sponsored networking events and such. SPIE is the international society for optics and photonics but this year SPIE Advanced Lithography is all about the highly anticipated EUV technology. Scotten Jones and I are at SPIE so expect more detailedRead More


Scott Jones ISS Talk – Moore’s Law Lives!

Scott Jones ISS Talk – Moore’s Law Lives!
by Scotten Jones on 02-07-2017 at 12:00 pm

I was invited to give a talk at this year’s ISS conference, the talk seemed to be very well received and I was asked to blog about it for SemiWiki. Parts of the talk will be familiar to SemiWiki readers from some of my previous blogs but I also went into more detail around some scaling challenges. The following is a summary of what… Read More


SPIE Advanced Lithography and Synopsys!

SPIE Advanced Lithography and Synopsys!
by Daniel Nenni on 02-01-2017 at 7:00 am

SPIE is the premier event for lithography held in Silicon Valley and again Scotten Jones and I will be attending. EUV is generally the star of the show and this year will be no different now that TSMC has committed to EUV production in 2019.

Last year at SPIE, TSMC presented the history of EUV development from the beginning in 1985 as … Read More


AAPl Vs QCOM Who wins?

AAPl Vs QCOM Who wins?
by Daniel Nenni on 01-26-2017 at 7:00 am

Things just got interesting in the iPhone supply chain with the $1B AAPL Vs QCOM legal action filed this week. For the life of me I could not understand why Apple second sourced the normally QCOM modem in the iPhone 7. It caused quite a stir in the technical community but we could only surmise that it was a price issue on the business side.… Read More


DARPA Flex Logix and TSMC!

DARPA Flex Logix and TSMC!
by Daniel Nenni on 01-23-2017 at 10:00 am

When I first saw emerging semiconductor IP company Flex Logix actively involved with TSMC I knew something big was coming and boy was I right. DARPA announced today that an agreement is in place with Flex Logix to develop EFLX eFPGA technology on TSMC 16FFC for use by companies or Government agencies designing chips for the US Government.… Read More


Another Interesting Thing From TSMC!

Another Interesting Thing From TSMC!
by Daniel Nenni on 01-21-2017 at 7:00 am

As I mentioned in my previous post, the TSMC investor call this month was very interesting and Morris Chang was in fine form during the Q&A. As a semiconductor professional I think some of the questions are ridiculous but maybe they have value to the financial people. This one question from Randy, who I think is very astute, is … Read More


Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration

Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration
by Mitch Heins on 01-20-2017 at 12:00 pm

I caught up with John Ferguson of Mentor Graphics this week to learn more about a recent announcement that TSMC has extended its collaboration with Mentor in the area of Fan-Out Wafer Level Processing (FOWLP).

In March of last year Mentor and TSMC announced that they were collaborating on a design and verification flow for TSMC’s… Read More


Analog Bits and TSMC!

Analog Bits and TSMC!
by Daniel Nenni on 01-10-2017 at 12:00 pm

TSMC Wafer

As a long time semiconductor IP professional I can tell you for a fact that it is one of the most challenging segments of semiconductor design. Given the growing criticality of semiconductor IP, the challenges of being a leading edge IP provider are increasing and may be at a breaking point. The question now is: What does it take to … Read More