Flexible ASIC Strategy!

Flexible ASIC Strategy!
by Daniel Nenni on 04-21-2012 at 9:00 pm

During my last Taiwan trip I also spent time with Global Unichip. Clearly, in order for the semiconductor industry to thrive we must enable design starts. With the rising costs and complexity of semiconductor design and manufacturing this is a much greater challenge which is why I’m so interested in GUC, for the greater good of the… Read More


The Carbon Decade

The Carbon Decade
by Paul McLellan on 04-19-2012 at 6:00 am

Carbon Design Systems celebrates its 10th anniversary this month. It is a celebration that the company has survived a decade but also bittersweet that the company hasn’t been acquired for a juicy premium. But we just have to accept that EDA is not a business where you can throw together a company in 18 months and sell it for $1B… Read More


Introduction to FinFET technology Part I

Introduction to FinFET technology Part I
by Tom Dillinger on 04-18-2012 at 6:00 pm

This is the first of a multi-part series, to introduce FinFET technology to SemiWiki readers. These articles will highlight the technology’s key characteristics, and describe some of the advantages, disadvantages, and challenges associated with this transition. Topics in this series will include FinFET fabrication,Read More


Laker Wobegon, where all the layout is above average

Laker Wobegon, where all the layout is above average
by Paul McLellan on 04-17-2012 at 4:00 am

TSMC’s technnology symposium seems to be the new time to make product announcements, with ARM and Atrenta yesterday and Springsoft today.

There is a new incarnation of Springsoft’s Laker layout family, Laker[SUP]3[/SUP] (pronounced three, not cubed). The original version ran on its own proprietary database.… Read More


Soft Error Rate (SER) Prediction Software for IC Design

Soft Error Rate (SER) Prediction Software for IC Design
by Daniel Payne on 04-16-2012 at 10:00 am

My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate… Read More


Arteris evangelization High Speed Interfaces!

Arteris evangelization High Speed Interfaces!
by Eric Esteve on 04-15-2012 at 4:36 am

Kurt Shuler from Arteris has written a short but useful blog about the various high speed interface protocols currently used in the wireless handset (and smartphone) IP ecosystem. Arteris is well known for their flagship product, the Network-on-Chip (NoC), and the Mobile Application Processor market segment represent the … Read More


Chip in the Clouds – "Gathering"

Chip in the Clouds – "Gathering"
by Kalar Rajendiran on 04-13-2012 at 1:29 pm


Cloud computing is the talk of the tech world nowadays. I even hear commentaries about how entrepreneurs are turned down by venture capitalists for not including a cloud component into their business plan no matter what the core business may be. The commentary goes “It’s cloudy without any clouds.” Add some clouds to your strategy… Read More


Doing what others don’t do

Doing what others don’t do
by Paul McLellan on 04-12-2012 at 2:56 pm

Wally Rhines’ keynote at U2U, the Mentor users’ group meeting, was about Mentor’s strategy of focusing on what other people don’t do. This is partially a defensive approach, since Mentor has never had the financial firepower to have the luxury of focusing all their development on sustaining their products and then make … Read More


Oasys Gets Funding from Intel and Xilinx

Oasys Gets Funding from Intel and Xilinx
by Paul McLellan on 04-10-2012 at 8:00 am

Oasys announced that it closed its series B funding round with investments from Intel Capital and Xilinx. The fact that any EDA company has closed a funding round is newsworthy these days; companies running out of cash and closing the doors seems to be a more common story.

Oasys has been relatively quiet, which some people have taken… Read More


EDPS: SoC FPGAs

EDPS: SoC FPGAs
by Paul McLellan on 04-09-2012 at 4:00 am

Mike Hutton of Altera spends most of his time thinking about a couple of process generations out. So a lot of what he worries about is not so much the fine-grained architecture of what they put on silicon, but rather how the user is going to get their system implemented. 2014 is predicted to be the year in which over half of all FPGAs will… Read More