Managing Test Power for ICs

Managing Test Power for ICs
by Beth Martin on 11-07-2011 at 12:17 pm

The goal for automatic test pattern generation (ATPG) is to achieve maximum coverage with the fewest test patterns. This conflicts with the goals of managing power because during test, the IC is often operated beyond its normal functional modes to get the highest quality test results. When switching activity exceeds a device’s… Read More


High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!
by Daniel Nenni on 11-01-2011 at 9:00 am

Hello Daniel,
I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER
Read More


EDA Company Selected as One of the Fastest Growing Companies in North America by Deloitte’s 2011 Technology Fast 500™!?!?!?!

EDA Company Selected as One of the Fastest Growing Companies in North America by Deloitte’s 2011 Technology Fast 500™!?!?!?!
by Daniel Nenni on 10-31-2011 at 11:07 am

Wow! We always hear semiconductor companies complain about the lack of innovation amongst the EDA leaders. Placing high on the Deloitte 500 list shows that innovation is alive and well in EDA and it IS possible to have a meaningful impact regardless of your overall size. It is worth noting that there are very few EDA companies that… Read More


What’s New with Semiconductor Test and Failure Analysis at Mentor?

What’s New with Semiconductor Test and Failure Analysis at Mentor?
by Daniel Payne on 10-28-2011 at 6:03 pm

ISTFA
Silicon Valley is a great location for trade shows and technical conferences, so if you have an interest in test and failure analysis then don’t miss out on the 37th annual International Symposium for Testing and Failure Analysis. This year ISTFA will be held from Sunday, November 13th thru Thursday, November 17th … Read More


ARM TechCon 2011 Trip Report and Sailing Semiconductors!

ARM TechCon 2011 Trip Report and Sailing Semiconductors!
by Daniel Nenni on 10-26-2011 at 9:37 pm

This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat… Read More


Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 10-20-2011 at 9:56 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow

DRC Wiki

Graphical DRC vs Text-based DRC

Getting Real time Calibre DRC Results with Custom IC Editing

Transistor-level Electrical Rule Checking

Who Needs a 3D Field Solver for IC Design?

Prevention is BetterRead More


SICAS capacity data loses TSMC and UMC

SICAS capacity data loses TSMC and UMC
by Bill Jewell on 10-19-2011 at 10:26 am

SICAS (Semiconductor Industry Capacity Statistics) has released its 2Q 2011 data with significant changes in membership. The data is available through the SIA at: SICASdata The SICAS membership list no longer includes the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) or UnitedRead More


Apple is Giving Samsung Semiconductor A Splitting Headache

Apple is Giving Samsung Semiconductor A Splitting Headache
by Ed McKernan on 10-18-2011 at 5:00 pm

Vertical integration, as I have noted in previous blogs, is the way to domination and maximum profitability. That is unless someone else has beaten you to the punch with an even bettermodel. Apple is now executing a product and manufacturing supplier strategy that will force Samsung to lose lots of money and then ultimately split… Read More


Mentor at the TSMC Open Innovation Platform Ecosystem Forum

Mentor at the TSMC Open Innovation Platform Ecosystem Forum
by Daniel Payne on 10-17-2011 at 3:14 pm

EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.

Tomorrow in San Jose
you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.

Here are some of the topics that will interest IC designers… Read More


A New Name: ‘Si2Con’ Arrives October 20th!

A New Name: ‘Si2Con’ Arrives October 20th!
by Daniel Nenni on 10-11-2011 at 7:58 pm

In case you have not heard, the 16th Si2-hosted conference highlighting industry progress in design flow interoperability comes to Silicon Valley (Santa Clara, CA) on October 20th. Si2Con will showcase recent progress of members in the critical areas of:

[LIST=1]

  • Design tool flow integration (OpenAccess)
  • DRC / DFM / Parasitics
  • Read More