In the fabless world of semiconductor design, IP components have become indispensable partners and have enabled the development of complex billion gate SoCs. IP business in general is exhibiting a very high growth rate since couple of years and it is going to increase; the same is being reflected by a growing number of IP vendors… Read More
Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec … Read More
The Electronic Design Process Symposium is an annual workshop run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. I presented there because it’s devoid of product marketing pitches, and is two days of discussion on technical and process issues in SoC design. My slides are here:… Read More
Tanner EDA is making waves at their customer’s sites as the mixed-signal design suite from Tanner EDA, Incentia Design Systems, Inc. and Aldec, Inc. helps ASIC Design House lower cost and increase efficiency with no compromise in performance. In today’s ‘always on’, Internet of Things connected world, the demand for high-performance,… Read More
First, I wish there were more conferences/workshops like this. This is much more about sharing ideas and brainstorming than the stark commercialism of DAC. I presented Atrenta’s role in enabling 3[SUP]rd[/SUP]-party IP qualification for the TSMC soft IP library.
My presentation slides are located here:
http://www.eda.org/edps/Papers/5-3%20Bernard%20Murphy.pdf… Read More
Please join me for an IP conversation in collaboration with ClioSoft on Wednesday, April 30th, 2014 @ 11:00 AM PST. At the EDPS Workshop IP day there were two interesting presentations on IP reuse. The first one was by Warren Savage of IPextreme: Top Ten Reasons Why Internal IP Reuse Fails. The second was by Ranjit Adhikary of ClioSoft:… Read More
A number of technical and business trends are converging to create a booming market for solid state drives (SSDs), with gigabytes of flash memory capacity along with the related control electronics packaged in the form factor of a 1.8”‐, 2.5”‐ or 3.5”. storage device. The first is the emergence of tablets and pervasiveness of smart… Read More
In an era of SoCs with millions of gates, hundreds of IPs and multiple ways to verify designs through several stages of transformations at different levels of hierarchies, it is increasingly difficult to handle such large data in a consistent and efficient way. The hardware and software, and their interactions, have to be consistent… Read More
In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle… Read More
The semiconductor design sizes, these days, can easily be of the order of several hundred millions of cells, adding into the complexity of verification. Amid ever growing design sizes, it’s a must that the timing verification is done accurately. Normally Static Timing Analysis (STA) is done to check whether all clocks and signals… Read More
