PCIe design workflow debuts simulation-driven virtual compliance

PCIe design workflow debuts simulation-driven virtual compliance
by Don Dingee on 07-16-2024 at 6:00 am

PCIe classical workflow

PCIe design complexity continues rising as the standard for intrasystem communication evolves. An urgent need for more system bandwidth drives PCIe interconnects to multi-lane, multi-link, multi-level signaling. Classical PCIe design workflows leave designers with most of the responsibility for getting the requisite… Read More


PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels

PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels
by Kalar Rajendiran on 02-14-2023 at 6:00 am

Multi Level Challenges

As the premier high-speed communications and system design conference, DesignCon 2023 offered deep insights from various experts on a number of technical topics. In the area of high-speed communications, PCIe has a played a crucial role over the years in supporting increasingly higher communications speed with every new revision.… Read More