Power Management Gets Tricky in IP Driven World

Power Management Gets Tricky in IP Driven World
by Pawan Fangaria on 07-08-2015 at 7:00 pm

Today, an SoC can have multiple instances of an IP and also instances of many different IPs from different vendors. Every instance of an IP can work in a separate mode and requires a dedicated power arrangement which may only be formalized at the implementation stage. The power intent, if specified earlier, will need to be re-generated… Read More


What’s New in Functional Verification Debug

What’s New in Functional Verification Debug
by Daniel Payne on 06-28-2015 at 7:00 am

We often think of EDA vendors competing with each other and using proprietary data formats to make it difficult for users to mix and match tools, or even create efficient flows of tools. At the recent DAC event in San Francisco I was pleasantly surprised to hear that two EDA vendors decided to cooperate instead of create incompatible… Read More


Predicting Lifetime of Analog ICs

Predicting Lifetime of Analog ICs
by Pawan Fangaria on 06-22-2015 at 12:30 pm

With the increase of transistors per unit area, high density interconnects and manufacturing variability at lower nodes, the electronic devices have become more vulnerable to failures. The devices that operate under extreme conditions such as automotive devices that operate at high temperatures need to be robust enough to… Read More


Can FD-SOI Change the Rule of Game?

Can FD-SOI Change the Rule of Game?
by Pawan Fangaria on 06-18-2015 at 12:00 pm

It appears so. Why there is so much rush towards FD-SOI in recent days? Before talking about the game, let me reflect a bit on the FD-SOI technology first. The FD-SOI at 28nm claims to be the most power-efficient and lesser cost technology compared to any other technology available at that node. There are many other advantages from… Read More


Eyes Meet Innovations at DAC

Eyes Meet Innovations at DAC
by Pawan Fangaria on 06-14-2015 at 7:00 am

It gives me a very nice, somewhat nostalgic, feeling after attending the 52[SUP]nd[/SUP] DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D… Read More


Why silicon photonics and 2.5D design go together

Why silicon photonics and 2.5D design go together
by Beth Martin on 06-10-2015 at 4:30 pm

Silicon photonics is one of the upstart “More than Moore” technologies designed to enable the next generation of high-performance devices. Photonic design is the art of moving and transforming signals in the form of photons, allowing the message to literally travel at the speed of light, and bringing the promise of significant… Read More


Experts Talk at Mentor Booth

Experts Talk at Mentor Booth
by Pawan Fangaria on 05-11-2015 at 7:00 pm

It’s less than four weeks to go at DAC 2015 and the program is final now. So I started investigating new technologies, trends, methodologies, and tools that will be unveiled and discussed in this DAC. In the hindsight of the semiconductor industry over the last year, I see 14nm technologies in the realization stage and 10nm beckoning… Read More


Calibre xACT Shakes Up 16nm and Below Extraction Game

Calibre xACT Shakes Up 16nm and Below Extraction Game
by Tom Simon on 05-09-2015 at 8:00 am

Mentor Graphics made a big announcement regarding SOC extraction at their User2User conference in San Jose during April. Before I get to the meat of the announcement, I’d like to reflect back on the early days of Calibre-DRC at Mentor. I was in Sales at Mentor around 1999, and Calibre-DRC was the new kid on the block. We had to go convince… Read More


Are There Trojans in Your Silicon? You Don’t Know

Are There Trojans in Your Silicon? You Don’t Know
by Paul McLellan on 04-22-2015 at 7:00 am

Yesterday was the Mentor users’ group U2U. As usual, Wally Rhines gave the keynote, this year entitled Secure Silicon, Enabler for the Internet of Things. Wally started off saying it was a challenge to find a new angle. The number of news articles on cloud computing has exploded from nothing to 72,000 last year. On IoT from … Read More


TSV Modeling Key for Next Generation SOC Module Performance

TSV Modeling Key for Next Generation SOC Module Performance
by Tom Simon on 04-20-2015 at 1:00 pm

The use of silicon interposers is growing. Several years ago Xilinx broke new ground by employing interposers in their Virtex®-7 H580T FPGA. Last August Samsung announced what they say is the first DDR4 module to use 3D TSV’s for enterprise servers. Their 64GB double data rate-4 modules will be used for high end computing where … Read More