ASML- A Semiconductor Market Leader-Strong Demand Across all Products/Markets

ASML- A Semiconductor Market Leader-Strong Demand Across all Products/Markets
by Robert Maire on 07-25-2021 at 6:00 am

asml logo 20120410 1

– Strong demand across logic/memory & leading/trailing edge
– Customers want units fast-no time to test
– The main question is can ASML ramp to meet demand?

Revenue & Earnings low due to systems being rushed to customers
ASML reported Euro 4B in sales and Euro 1B in net income which while within guidance… Read More


Stochastic Origins of EUV Feature Edge Roughness

Stochastic Origins of EUV Feature Edge Roughness
by Fred Chen on 07-11-2021 at 10:00 am

Stochastic Origins of EUV Feature Edge Roughness

Due to the higher energy of EUV (13.3-13.7 nm wavelength) compared to ArF (193 nm wavelength) light, images produced by EUV are more susceptible to photon shot noise.

Figure 1. (Left) 40 nm dense (half-pitch) line image projected onto wafer at 35 mJ/cm2; (Right) 20 nm dense (half-pitch) line image projected onto wafer at 70 mJ/cm2.Read More


Contrast Reduction vs. Photon Noise in EUV Lithography

Contrast Reduction vs. Photon Noise in EUV Lithography
by Fred Chen on 05-30-2021 at 6:00 am

Contrast Reduction vs. Photon Noise in EUV Lithography

The stochastic behavior of images formed in EUV lithography has already been highlighted by a number of authors [1-3]. How serious it appears depends on the pixel size with which the photons are bunched. Generally, though, for features of around 20 nm or less, even 1 nm can have at least a +/- 15% gradient across it, which is still a

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SPIE 2021 – ASML DUV and EUV Updates

SPIE 2021 – ASML DUV and EUV Updates
by Scotten Jones on 03-17-2021 at 10:00 am

SPIE DUV 2021 ASML NXT4 DryWet Presentation final noWPD2 Page 42

At the SPIE Advanced Lithography Conference held in February, ASML presented the latest information on their Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) exposure systems. I recently got to interview Mike Lercel of ASML to discuss the presentations.

DUV

Despite all the attention EUV is getting, most layers are still… Read More


ASML – Strong DUV Throwback While EUV Slows- Logic Dominates Memory

ASML – Strong DUV Throwback While EUV Slows- Logic Dominates Memory
by Robert Maire on 01-24-2021 at 6:00 am

ASML SMIC TSMC EUV DUV

ASML has good quarter driven by DUV & Logic (@72%)
– SMIC & other major customer slow EUV plans
– Logic (read that as TSMC) remains key demand led driver
– We are happy memory remains muted given cyclical potential

A very solid quarter with a continued road to growth
The quarter came in at Euro4,254B… Read More


ASML More Covid Concerns and Impact

ASML More Covid Concerns and Impact
by Robert Maire on 07-19-2020 at 6:00 am

ASML Covid
  • Covid related Revenue Rec causes rev/EPS miss
  • Sharp order drop reflects H2 industry uncertainty
  • EUV remains solid- Memory/Logic mix is better

Results were in line after correcting Covid Caused Revenue Rec issue-
ASML reported revenues of Euro3.3B and EPS of Euro1.79 as revenues from two EUV systems was not recognized, due to … Read More


The Stochastic Impact of Defocus in EUV Lithography

The Stochastic Impact of Defocus in EUV Lithography
by Fred Chen on 06-28-2020 at 6:00 am

The Stochastic Impact of Defocus in EUV Lithography

The stochastic nature of imaging has received a great deal of attention in the area of EUV lithography. The density of EUV photons reaching the wafer is low enough [1] that the natural variation in the number of photons arriving at a given location can give rise to a relatively large standard deviation.

In recent studies [2,3], it … Read More


The Uncertain Phase Shifts of EUV Masks

The Uncertain Phase Shifts of EUV Masks
by Fred Chen on 05-13-2020 at 10:00 am

The Uncertain Phase Shifts of EUV Masks

EUV (Extreme UltraViolet) lithography has received attention within the semiconductor industry since its development inception in 1997 with the formation of the EUV LLC [1], and more recently, since the 7nm node began, with limited use by Samsung and TSMC being touted as key advantages [2, 3]. As with any key critical technology,

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Lithography Resolution Limits – Arrayed Features

Lithography Resolution Limits – Arrayed Features
by Fred Chen on 04-17-2020 at 6:00 am

Lithography Resolution Limits Arrayed Features

State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More


Lithography Resolution Limits: Paired Features

Lithography Resolution Limits: Paired Features
by Fred Chen on 04-07-2020 at 10:00 am

Lithography Resolution Limits Paired Features

As any semiconductor process advances to the next generation or “node”, a sticky point is how to achieve the required higher resolution. As noted in another article [1], multipatterning (the required use of repeated patterning steps for a particular feature) has been practiced already for many years, and many have… Read More