Ensuring Safety Distinctive Design & Verification

Ensuring Safety Distinctive Design & Verification
by Pawan Fangaria on 12-21-2014 at 12:00 pm

In today’s world where every device functions intelligently, it automatically becomes active on any kind of stimulus. The problem with such intelligence is that it can function unfavorably on any kind of bad stimulus. As the devices are complex enough in the form of SoCs (which at advanced process nodes are more susceptible to … Read More


An Approach to Top-Down SoC Verification

An Approach to Top-Down SoC Verification
by Daniel Payne on 12-19-2014 at 1:00 pm

We’ve blogged dozens of times about UVM– Universal Verification Methodology at SemiWiki, and all of the major EDA vendors support UVM, so you may be lulled into thinking that UVM is totally adequate for top-down SoC verification. Yesterday I had a phone discussion with Frank Schirrmeister of Cadence about a new approach… Read More


A Closer Look at the QCOM $40M Investment in China!

A Closer Look at the QCOM $40M Investment in China!
by Daniel Nenni on 12-14-2014 at 7:00 am

Last Thursday night was the 20[SUP]th[/SUP] annual GSA Awards Dinner which probably hosts one of the largest collections of semiconductor executives. Think of a movie or music awards show with all of the trimmings including Jay Leno as the keynote. I don’t know the exact head count but there were 160 dinner tables with 10 plates … Read More


What makes the world smart?

What makes the world smart?
by Pawan Fangaria on 11-25-2014 at 4:00 pm

The simple answer is when everything in the world is smart. But if you think deeply, you would find that the continuous progression to make things easy in life is what makes the world smarter day-by-day – the sky is the limit. In the world of computing, consider the 17[SUP]th[/SUP] century era when humanbrain was used as a computer … Read More


Semiconductor IP Information Flow!

Semiconductor IP Information Flow!
by Daniel Nenni on 11-13-2014 at 9:00 pm

One of the biggest challenges in the IP business, or any other business for that matter, is managing the information flow. Semiconductor IP is a critical piece of the fabless semiconductor ecosystem so anybody and everybody can write about it. Unfortunately, anybody and everybody ARE writing about it. From day one IP has been a … Read More


Using Cadence PVS for Signoff at TowerJazz

Using Cadence PVS for Signoff at TowerJazz
by Daniel Payne on 11-11-2014 at 7:00 pm

TowerJazzis a specialty foundry that provides IC manufacturing into several markets, like: RF, high-performance analog, power, imaging, consumer, automotive, medical, industrial and aerospace/defense. In June there was a presentation from Ofer Tamir of TowerJazz at DACin the Cadence theatre, so I had a chance this week … Read More


How Sonics Uses Jasper Formal Verification

How Sonics Uses Jasper Formal Verification
by Paul McLellan on 11-11-2014 at 7:00 am

The Jasper part of Cadence announced jointly with Sonics a relationship whereby Sonics uses JasperGold Apps as part of their verification. I talked to Drew Wingard, the CTO, about how they use it.

One way is during the day when their design engineers use Jasper as part of their verification arsenal. Interestingly it is the design… Read More


Semiconductor Safety

Semiconductor Safety
by Daniel Nenni on 11-06-2014 at 7:00 am

Semiconductors and automotive are now like peanut butter and jelly. Certainly you can have one without the other but why would you? I remember when a car first talked to me telling me that the door was ajar. It sounded more like, “the door is a jar” but I got the point. Now my car tells me just about everything including what is wrong with… Read More


In-Design DFM Signoff for 14nm FinFET Designs

In-Design DFM Signoff for 14nm FinFET Designs
by Pawan Fangaria on 11-04-2014 at 4:00 pm

While FinFET yield controversy is going on, I see a lot being done to improve that yield by various means. One prime trend today, it must be, it’s worthwhile, is to pull up various signoffs as early as possible during the design cycle. And DFM signoff is a must with respect to yield of fabrication. This reminds me about my patents filed… Read More


What Presentations to Attend During IP-SoC 2014 ?

What Presentations to Attend During IP-SoC 2014 ?
by Eric Esteve on 11-01-2014 at 11:00 am

Will you go to Grenoble next week to attend to IP-SoC? I will do it and will certainly listen to these Keynote Talks:

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