CDN is Live in Silicon Valley!

CDN is Live in Silicon Valley!
by Daniel Nenni on 03-03-2015 at 10:00 pm

As big of a fan as I am of Social Media there is still nothing like getting up close and personal when collaborating with the fabless semiconductor ecosystem. After 30+ years in Silicon Valley if there is one thing I have learned it’s that “showing up” is the #1 key to success, absolutely.

Speaking of showing up, each year there are three… Read More


High Level Synthesis Gets Stronger

High Level Synthesis Gets Stronger
by Daniel Payne on 02-24-2015 at 1:00 pm

High Level Synthesis (HLS) tools have been around for at least two decades now, and you may recall that about one year ago Cadence acquired Forte. The whole promise of HLS is to provide more design and verification productivity by raising the design abstraction from RTL code up to SystemC, C or C++ code. With any acquisition it is natural… Read More


IoT Sensor Node Designs Call for Highly Integrated Flows

IoT Sensor Node Designs Call for Highly Integrated Flows
by Tom Simon on 02-21-2015 at 7:00 pm

Applications for IoT sensors are becoming more sophisticated, especially for industrial usage. Building optimal sensors for different applications requires multi-domain design, optimization and verification flows. The sensor devices are usually MEMS, and as such have electrical properties that need to be tailored to … Read More


Earnings Calls: Behind the Scenes

Earnings Calls: Behind the Scenes
by Paul McLellan on 02-19-2015 at 7:00 am

Last weekend I wrote about the Applied Materials earnings call. And over the last couple of years I’ve written about lots of other earnings calls. Most people have never been on an earnings call, I mean in the conference room where the call is being conducted, not just listening. So I thought it might be interesting to describe how … Read More


Physically Aware DFT Improves PPA

Physically Aware DFT Improves PPA
by Pawan Fangaria on 02-16-2015 at 7:00 pm

Introducing on-chip test circuitry has become a necessary criteria for an ASIC’s post manufacture testability. The test circuitry is usually referred as DFT (Design-for-Test) circuit. A typical methodology for introducing DFT circuit in a design is to replace usual flip-flops with special types of flip-flops called ‘scan… Read More


Cadence 2014 Results

Cadence 2014 Results
by Paul McLellan on 02-05-2015 at 7:01 pm

Cadence announced their Q4 and 2014 results yesterday. They are the only one of the big 3 EDA companies whose fiscal year is the calendar year so Synopsys and Mentor will not be joining them in announcing them this week.

I won’t go into the numbers in detail, you can find them all easily enough. But it is a pity that statements like… Read More


Concept: From Schematics to Debug

Concept: From Schematics to Debug
by Paul McLellan on 02-05-2015 at 7:00 am

In the late 1990s I was the VP Engineering at Ambit Design Systems. We had a synthesis product (called BuildGates, nobody ever forgot the name). Both our own engineers and our customers wanted to be able to take a look at the gate-level netlist that was generated from their RTL. We used a product from a company called Concept Engineering… Read More


Temperature Monitoring IP to Revamp SoCs

Temperature Monitoring IP to Revamp SoCs
by Pawan Fangaria on 02-04-2015 at 3:00 pm

With increasing density and functionality of chips at extremely thin silicon and metal layers, temperature has become critical. The temperature situation can become worse with wireless enabled 24/7 power-on devices. In such a scenario, a device must manage its thermal profile dynamically to keep the temperature within tolerable… Read More


Sigrity Focuses on LPDDR4 Compliance Analysis in 2015 Release

Sigrity Focuses on LPDDR4 Compliance Analysis in 2015 Release
by Tom Simon on 01-27-2015 at 10:00 am

It was back in July of 2012 that the acquisition of Sigrity by Cadence was announced. Although Cadence is a dominant player in both IC and board layout tools, they did not have an electromagnetic (EM) signal integrity solution in their portfolio. This acquisition marks a turning point for the EM/SI sector – tight integration… Read More


FDSOI jump-start 2015 in Tokyo this week

FDSOI jump-start 2015 in Tokyo this week
by Eric Esteve on 01-19-2015 at 4:38 am

This news in May 2014 that Samsung had licensed FD-SOI Technology from ST-Microelectronics was really amazing, as most of the industry was expecting this kind of agreement, but not with the #2 SC Company. But since May 2014 the news flow has been quite reduced, we can imagine that both SC companies had a lot work to do for transforming… Read More