A No-Fudge ML Architecture for Arm

A No-Fudge ML Architecture for Arm
by Bernard Murphy on 11-12-2019 at 5:00 am

Ethos applications

At TechCon I had a 1×1 with Steve Roddy, VP of product marketing in the Machine Learning (ML) Group at Arm. I wanted to learn more about their ML direction since I previously felt that, amid a sea of special ML architectures from everyone else, they were somewhat fudging their position in this space. What I heard earlier was that… Read More


ReRAM Revisited

ReRAM Revisited
by Bernard Murphy on 11-06-2019 at 6:00 am

Memory

I met with Sylvain Dubois (VP BizDev and Marketing of Crossbar) at TechCon to get an update on his views on ReRAM technology. I’m really not a semiconductor process guy so I’m sure I’m slower than the experts to revelations in this area. But I do care about applications so I hope I can add an app spin on the topic, also Sylvain’s views on… Read More


Arm Reveals Custom Instructions, Mbed Partner Governance

Arm Reveals Custom Instructions, Mbed Partner Governance
by Bernard Murphy on 10-30-2019 at 6:00 am

Tipping the scale

At TechCon Arm announced two more advances against competitive threats, one arguably tactical and the other strategic, at least in this writer’s view.  The tactical move was to add support for custom instructions, the ability to collapse multiple instructions into a single instruction through customer-added logic which hooks… Read More


Accelerating Functional Safety Verification

Accelerating Functional Safety Verification
by Bernard Murphy on 10-24-2019 at 6:00 am

FuSa Verification

Verifying a design for functional safety requirements for an IP or SoC per ISO 26262 is a complex process that can’t be encapsulated in one tool. Process complexities depend on whether the Tier1 or OEM is targeting safety-levels ASIL-A , B, C or D, where ASIL-D applies to anything truly safety-critical such as airbag controls or … Read More


Safety and Platform-Based Design

Safety and Platform-Based Design
by Bernard Murphy on 10-22-2019 at 5:00 am

Safety infrastructure in platform design

I was at Arm TechCon as usual this year and one of the first panels I covered was close to the kickoff, hosted by Andrew Hopkins (Dir System Technology at Arm), Kurt Shuler (VP marketing at Arteris IP) and Jens Benndorf (Managing Dir and COO at Dream Chip Technologies). The topic was implementing ISO 26262-compliant AI SoCs with Arm… Read More


Virtualizing 5G Infrastructure Verification

Virtualizing 5G Infrastructure Verification
by Bernard Murphy on 10-17-2019 at 5:00 am

5G backhaul, midhaul, fronthaul

Mentor have pushed the advantages of virtualized verification in a number of domains, initially in verifying advanced networking devices supporting multiple protocols and software-defined networking (SDN), and more recently for SSD controllers, particularly in large storage systems for data centers. There are two important… Read More


Formal in the Field: Users are Getting More Sophisticated

Formal in the Field: Users are Getting More Sophisticated
by Bernard Murphy on 10-15-2019 at 5:00 am

Formal SIG 2019 meeting at Synopsys

Building on an old chestnut, if sufficiently advanced technology looks like magic, there are a number of technology users who are increasingly looking like magicians. Of course when it comes to formal, neither is magical, just very clever. The technology continues to advance and so do the users in their application of those methods.… Read More


Accellera IP Security Standard: A Start

Accellera IP Security Standard: A Start
by Bernard Murphy on 10-10-2019 at 5:00 am

IPSA Workflow

I mentioned some time ago (a DVCon or two ago) that Accellera had started working on a standard to quantify IP security. At the time I talked about some of the challenges in the task but nevertheless applauded the effort. You’ve got to start somewhere and some way to quantify this is better than none, as long as it doesn’t deliver misleading… Read More


Design Perspectives on Intermittent Faults

Design Perspectives on Intermittent Faults
by Bernard Murphy on 10-08-2019 at 5:00 am

Faults

Bugs are an inescapable reality in any but the most trivial designs and usually trace back to very deterministic causes – a misunderstanding of the intended spec or an incompletely thought-through implementation of some feature, either way leading to reliably reproducible failure under the right circumstances. You run diagnostics,… Read More


Acceleration in a Heterogenous Compute Environment

Acceleration in a Heterogenous Compute Environment
by Bernard Murphy on 10-02-2019 at 5:00 am

Acceleration

Heterogenous compute isn’t a new concept. We’ve had it in phones and datacenters for quite a while – CPUs complemented by GPUs, DSPs and perhaps other specialized processors. But each of these compute engines has a very specific role, each driven by its own software (or training in the case of AI accelerators). You write software… Read More