Podcast EP87: How Axiomise Addresses the Verification Challenge

Podcast EP87: How Axiomise Addresses the Verification Challenge
by Daniel Nenni on 06-16-2022 at 10:00 am

Dan is joined by GD Bansal, COO at Axiomise.  Dan explores the Axiomise business model to provide training and consulting services for formal verification with GD. The benefits and challenges of using formal verification on complex designs are discussed, along with the benefits of the Axiomize vendor-neutral approach to … Read More


Accelerating Exhaustive and Complete Verification of RISC-V Processors

Accelerating Exhaustive and Complete Verification of RISC-V Processors
by Ashish Darbari on 08-29-2021 at 6:00 am

FIG 1 spec bug

As processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands has increased massively. We have no doubt that in next 5 years, we will see RISC-V based laptops and desktops in the market. But would these processors… Read More


RISC-V Formal Verification for ISA Compliance

RISC-V Formal Verification for ISA Compliance
by Daniel Nenni on 07-07-2020 at 10:00 am

RISC-V is an open standard instruction set architecture introduced in 2010. It has experienced exponential growth in recent years, enabling users to design custom processors more quickly and cost effectively to meet today’s demand for more technological innovations in the CPU, GPU, AI, ML spaces.

However, verification of … Read More