Semiconductor IP Dilemma?

Semiconductor IP Dilemma?
by Daniel Nenni on 01-01-2012 at 3:00 pm

Just how many hands have touched your SoC design by the time it goes to manufacturing? Clearly the more hands that touch it, the more complex the design is, making it more difficult to meet your product requirements. The commercial semiconductor IP dilemma is that not only are you using the same IP as your competitors, you are exponentially… Read More


TSMC ASIC versus IBM ASIC!

TSMC ASIC versus IBM ASIC!
by Daniel Nenni on 10-30-2011 at 3:00 pm

Lunch with Jim Lai, President of Global Unichip(GUC), was the highlight of my week, I had a very nice crab cake salad. As you may have read, GUC announced itself as the “Flexible ASIC Leader” taking direct aim at the traditional ASIC market led by the likes of IBM, ST Micro, TI, Renesas, and Samsung. This will be like “shooting fish inRead More


Once Upon A Time… ASIC designers developed IC for Supercomputer in the 80’s

Once Upon A Time… ASIC designers developed IC for Supercomputer in the 80’s
by Eric Esteve on 07-07-2011 at 10:41 am

During last week-end, I had the good surprise to meet with one of my oldest friend, Eric, who remind me the old time, when we were working together as ASIC designers for… a Supercomputer project.

In France, in a French company (Thomson CSF) active in the military segment and being able to spend which was at that time a fortune ($25M) Read More


SOC Realization: How Chips Are Really Designed

SOC Realization: How Chips Are Really Designed
by Paul McLellan on 05-09-2011 at 10:00 pm

If you just casually peruse most marketing presentations by EDA companies, you’d come to the conclusion most SoCs are designed from scratch, wrestlilng the monster to the ground with bare hands. But the reality is that most SoCs consist of perhaps 90% IP blocks (many of them memories). That still leaves the remaining 10% … Read More


Ivo Bolsens of Xilinx and Crossover Designs

Ivo Bolsens of Xilinx and Crossover Designs
by Paul McLellan on 04-27-2011 at 4:14 pm

I was at Mentor’s u2u (user group) meeting and one of the keynotes was by Ivo Bolsens of Xilinx. The other was by Wally Rhines and is summarized here.

Ivo started off talking analogizing SoCs as the sports-cars of the industry (fast but expensive), and FPGAs as the station wagons (not cool). In fact he even said that when Xilinx… Read More


The World’s Smallest Printed Circuit Boards: interposers

The World’s Smallest Printed Circuit Boards: interposers
by Paul McLellan on 04-27-2011 at 1:38 pm

Have you ever had the experience where you look up some unusual word in the dictionary since you don’t remember seeing it before. And then, in the next few weeks you keep coming across it. Twice in the last week I have been in presentations about the economics of putting die onto silicon interposers and the possibility of a new… Read More


Clock Domain Crossing (CDC) Verification

Clock Domain Crossing (CDC) Verification
by Paul McLellan on 02-21-2011 at 6:12 pm

Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors–errors that canRead More