As the size and complexity of System On Chip design has rapidly expanded in recent years, the need to use cache memory to improve throughput and reduce power has increased as well. Originally, cache memory was used to prevent what was then a single processor from making expensive off chip access for program or data memory. With the… Read More
Tag: arm
21 months lining up OPNFV-on-ARM for telecom
Telecom infrastructure is one area where X86 architecture hasn’t dominated historically. Infrastructure gear is spread across MIPS, Power, and SPARC architectures, with some X86, and a relative newcomer: ARM, already claiming 15% share. That’s a stunning figure considering only a bit less than 5 years ago… Read More
From Zero to IoT Prototype in One Month
The best things in life may not always be free, but they don’t have to be incredibly difficult to get to. A challenge for IoT designers has been that their bubbling excitement over the potential of their new gizmo is quickly tempered by the complexities of actually building the hardware. Not exactly what they have come to expect in … Read More
ARM vs Intel: The New War Frontiers
With Intel’s exit from smartphone processor market, the competitive zones are redefined with its rivalry with ARM. Is ARM’s domination the only reason for Intel’s exit? With no competing architecture, is ARM a monopoly in smartphone processor IP market? What are the new areas of competition between ARM and Intel? I will attempt… Read More
Two New Announcements from Tanner EDA at #53DAC
Most mergers and acquisitions in the EDA world simply don’t work out financially a year or two after the deal is done, however I was pleasantly surprised to learn that Tanner EDA is doing quite well at #53DAC this year after the acquisition by Mentor Graphics back in March 2015. Everyone that I’ve been meeting with at … Read More
Is the Intel Cash Cow in Danger?
There was an interesting panel at the Silicon Summit sponsored by the Global Semiconductor Alliance (GSA) on “Designing for the Cloud.” It was led by Linley Gwennap (The Linley Group) with Ivo Bolsons (Xilinx), Ian Ferguson (ARM), and Steve Pawloski (Micron). Missing of course was Intel which derives close to 30% of its revenue… Read More
Highlights of the 22nm FD-SOI San Jose Presentations
This is part 2 (of 2) of my coverage of the recent FD-SOI Symposium in San Jose (April 2016), this time looking at the 22nm presentations by GlobalFoundries, ARM (finally!!), VLSI Research Inc and Sigma Designs. (Part 1 looked at the 28nm presentations.) Most are now available on the SOI Consortium website – click here to see the full… Read More
Arteris Unveils Solution for Heterogeneous Cache Coherent SOC’s
Designing SOC’s for markets like automotive and mobile electronics requires taking advantage of every opportunity for optimization. One way to do this is through building a cache coherent system to boost speed and reduce power. Recently, NXP decided to go about this on their automotive MCU based SOC’s by using Arteris’ just-announced… Read More
ARM tests out TSMC 10FinFET – with two cores
About 13 months ago, the leak blogs posted news of “Artemis” on an alleged ARM roadmap slide, supposedly a new 16FF ARM core positioned as the presumptive successor to the Cortex-A57. Now, we’re finding out what “Artemis” may actually be, inside a multi-core PPA test chip on TSMC 10FinFET.… Read More
Cache Coherent Systems Get a Boost from New Technology
The speed and power penalties for accessing system RAM affect everything from artificial intelligence platforms to IoT sensor nodes. There is a huge power and performance overhead when the various IP blocks in an SOC need to go to DRAM. Memory caches have become essential to SOC design to reduce these adverse effects. However, … Read More