Understanding the electromagnetic (EM) coupling between various elements of a high-frequency semiconductor device is vital for meeting design specifications and ensuring reliable operation in the field. These EM interactions include not only the silicon chip but also extend to the package that encloses it. However, it may… Read More
As we all know, hearing directly from the people who actually use EDA tools, people who are solving real world problems with the latest technologies are the best source of information. Thus EDA User group meetings are always first on my event list every year which brings us to Ansys Ideas.
As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently… Read More
The 15th TSMC Open Innovation Platform® (OIP) was held last week. In preparation we did a podcast with one of the original members of the TSMC OIP team Dan Kochpatcharin. Dan and I talked about the early days before OIP when we did reference flows together. Around 20 years ago I did a career pivot and focused on Strategic Foundry Relationships.… Read More
Dan is joined by William Ruby, director of product management for Synopsys Power Analysis products. He has extensive experience in the area of low-power IC design and design methodology, and has held senior engineering and product marketing positions with Cadence, ANSYS, Intel, and Siemens. He also has a patent in high-speed… Read More
Cadence hosted a panel at DAC on how EDA, MCAD and industrial software have come together, a topic I always find interesting. Many years ago, I worked on a NAVAIR contract bid team, an eye-opener for a young engineer who thought that innovation started and ended with electronic design. I remember CATIA (3D modeling) being a component… Read More
As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering… Read More
In the 3D-IC (Three-dimensional integrated circuit) chip design method, chiplets or wafers are stacked vertically on top of each other and are connected using Through Silicon Vias (TSVs) or hybrid bonding.
The 2.5D-IC design method places multiple chiplets alongside each other on a silicon interposer. Microbumps and interconnect… Read More
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.
With… Read More
